Lines Matching refs:sor
399 int (*probe)(struct tegra_sor *sor);
400 void (*audio_enable)(struct tegra_sor *sor);
401 void (*audio_disable)(struct tegra_sor *sor);
484 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset) in tegra_sor_readl() argument
486 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl()
488 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
493 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
496 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
497 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
500 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) in tegra_sor_set_parent_clock() argument
504 clk_disable_unprepare(sor->clk); in tegra_sor_set_parent_clock()
506 err = clk_set_parent(sor->clk_out, parent); in tegra_sor_set_parent_clock()
510 err = clk_prepare_enable(sor->clk); in tegra_sor_set_parent_clock()
519 struct tegra_sor *sor; member
543 struct tegra_sor *sor = pad->sor; in tegra_clk_sor_pad_set_parent() local
546 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
559 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
567 struct tegra_sor *sor = pad->sor; in tegra_clk_sor_pad_get_parent() local
571 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_get_parent()
594 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor, in tegra_clk_sor_pad_register() argument
601 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL); in tegra_clk_sor_pad_register()
605 pad->sor = sor; in tegra_clk_sor_pad_register()
609 init.parent_names = tegra_clk_sor_pad_parents[sor->index]; in tegra_clk_sor_pad_register()
610 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]); in tegra_clk_sor_pad_register()
615 clk = devm_clk_register(sor->dev, &pad->hw); in tegra_clk_sor_pad_register()
620 static void tegra_sor_filter_rates(struct tegra_sor *sor) in tegra_sor_filter_rates() argument
622 struct drm_dp_link *link = &sor->link; in tegra_sor_filter_rates()
644 static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes) in tegra_sor_power_up_lanes() argument
653 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
656 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
657 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2])); in tegra_sor_power_up_lanes()
659 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
660 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]); in tegra_sor_power_up_lanes()
663 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
665 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
668 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
670 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
672 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
677 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_up_lanes()
682 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_up_lanes()
695 static int tegra_sor_power_down_lanes(struct tegra_sor *sor) in tegra_sor_power_down_lanes() argument
701 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
704 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
709 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_down_lanes()
714 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_down_lanes()
727 static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes) in tegra_sor_dp_precharge() argument
732 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
735 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
736 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2])); in tegra_sor_dp_precharge()
738 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
739 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]); in tegra_sor_dp_precharge()
742 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
744 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
747 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
749 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
751 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
755 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
758 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
761 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor) in tegra_sor_dp_term_calibrate() argument
766 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
768 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
770 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
772 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
777 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
780 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
784 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
791 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
794 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
797 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
799 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
804 struct tegra_sor *sor = container_of(link, struct tegra_sor, link); in tegra_sor_dp_link_apply_training() local
806 const struct tegra_sor_soc *soc = sor->soc; in tegra_sor_dp_link_apply_training()
814 u8 shift = sor->soc->lane_map[i] << 3; in tegra_sor_dp_link_apply_training()
820 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu) in tegra_sor_dp_link_apply_training()
821 tx_pu = sor->soc->tx_pu[pc][vs][pe]; in tegra_sor_dp_link_apply_training()
854 tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_dp_link_apply_training()
855 tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0); in tegra_sor_dp_link_apply_training()
858 tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0); in tegra_sor_dp_link_apply_training()
860 tegra_sor_writel(sor, pattern, SOR_DP_TPG); in tegra_sor_dp_link_apply_training()
862 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
866 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
875 struct tegra_sor *sor = container_of(link, struct tegra_sor, link); in tegra_sor_dp_link_configure() local
884 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_dp_link_configure()
887 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_dp_link_configure()
889 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_dp_link_configure()
896 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_dp_link_configure()
901 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
918 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
921 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_link_configure()
928 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_link_configure()
930 err = tegra_sor_power_down_lanes(sor); in tegra_sor_dp_link_configure()
932 dev_err(sor->dev, "failed to power down lanes: %d\n", err); in tegra_sor_dp_link_configure()
937 err = tegra_sor_power_up_lanes(sor, lanes); in tegra_sor_dp_link_configure()
939 dev_err(sor->dev, "failed to power up %u lane%s: %d\n", in tegra_sor_dp_link_configure()
944 tegra_sor_dp_precharge(sor, lanes); in tegra_sor_dp_link_configure()
954 static void tegra_sor_super_update(struct tegra_sor *sor) in tegra_sor_super_update() argument
956 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); in tegra_sor_super_update()
957 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0); in tegra_sor_super_update()
958 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); in tegra_sor_super_update()
961 static void tegra_sor_update(struct tegra_sor *sor) in tegra_sor_update() argument
963 tegra_sor_writel(sor, 0, SOR_STATE0); in tegra_sor_update()
964 tegra_sor_writel(sor, 1, SOR_STATE0); in tegra_sor_update()
965 tegra_sor_writel(sor, 0, SOR_STATE0); in tegra_sor_update()
968 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) in tegra_sor_setup_pwm() argument
972 value = tegra_sor_readl(sor, SOR_PWM_DIV); in tegra_sor_setup_pwm()
975 tegra_sor_writel(sor, value, SOR_PWM_DIV); in tegra_sor_setup_pwm()
977 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
982 tegra_sor_writel(sor, value, SOR_PWM_CTL); in tegra_sor_setup_pwm()
987 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
997 static int tegra_sor_attach(struct tegra_sor *sor) in tegra_sor_attach() argument
1002 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
1005 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
1006 tegra_sor_super_update(sor); in tegra_sor_attach()
1009 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
1011 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
1012 tegra_sor_super_update(sor); in tegra_sor_attach()
1017 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_attach()
1027 static int tegra_sor_wakeup(struct tegra_sor *sor) in tegra_sor_wakeup() argument
1035 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_wakeup()
1047 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) in tegra_sor_power_up() argument
1051 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
1053 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_up()
1058 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
1083 static int tegra_sor_compute_params(struct tegra_sor *sor, in tegra_sor_compute_params() argument
1151 static int tegra_sor_compute_config(struct tegra_sor *sor, in tegra_sor_compute_config() argument
1180 if (tegra_sor_compute_params(sor, ¶ms, i)) in tegra_sor_compute_config()
1199 dev_dbg(sor->dev, in tegra_sor_compute_config()
1214 dev_err(sor->dev, in tegra_sor_compute_config()
1219 dev_err(sor->dev, "watermark too high, forcing to %u\n", in tegra_sor_compute_config()
1237 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, in tegra_sor_compute_config()
1243 static void tegra_sor_apply_config(struct tegra_sor *sor, in tegra_sor_apply_config() argument
1248 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1251 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1253 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); in tegra_sor_apply_config()
1270 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); in tegra_sor_apply_config()
1272 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
1275 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
1277 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1280 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1283 static void tegra_sor_mode_set(struct tegra_sor *sor, in tegra_sor_mode_set() argument
1287 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); in tegra_sor_mode_set()
1291 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_mode_set()
1337 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_mode_set()
1345 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); in tegra_sor_mode_set()
1352 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); in tegra_sor_mode_set()
1359 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); in tegra_sor_mode_set()
1366 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); in tegra_sor_mode_set()
1369 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe); in tegra_sor_mode_set()
1372 static int tegra_sor_detach(struct tegra_sor *sor) in tegra_sor_detach() argument
1377 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1379 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1380 tegra_sor_super_update(sor); in tegra_sor_detach()
1385 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_detach()
1394 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1396 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1397 tegra_sor_super_update(sor); in tegra_sor_detach()
1400 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1402 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1403 tegra_sor_super_update(sor); in tegra_sor_detach()
1408 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_detach()
1421 static int tegra_sor_power_down(struct tegra_sor *sor) in tegra_sor_power_down() argument
1426 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1429 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_down()
1434 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1445 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_power_down()
1447 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_power_down()
1451 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1453 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1457 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1459 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
1461 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1464 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1471 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) in tegra_sor_crc_wait() argument
1478 value = tegra_sor_readl(sor, SOR_CRCA); in tegra_sor_crc_wait()
1491 struct tegra_sor *sor = node->info_ent->data; in tegra_sor_show_crc() local
1492 struct drm_crtc *crtc = sor->output.encoder.crtc; in tegra_sor_show_crc()
1504 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_show_crc()
1506 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_show_crc()
1508 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1510 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1512 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_show_crc()
1514 tegra_sor_writel(sor, value, SOR_TEST); in tegra_sor_show_crc()
1516 err = tegra_sor_crc_wait(sor, 100); in tegra_sor_show_crc()
1520 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA); in tegra_sor_show_crc()
1521 value = tegra_sor_readl(sor, SOR_CRCB); in tegra_sor_show_crc()
1653 struct tegra_sor *sor = node->info_ent->data; in tegra_sor_show_regs() local
1654 struct drm_crtc *crtc = sor->output.encoder.crtc; in tegra_sor_show_regs()
1670 offset, tegra_sor_readl(sor, offset)); in tegra_sor_show_regs()
1689 struct tegra_sor *sor = to_sor(output); in tegra_sor_late_register() local
1691 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_sor_late_register()
1693 if (!sor->debugfs_files) in tegra_sor_late_register()
1697 sor->debugfs_files[i].data = sor; in tegra_sor_late_register()
1699 drm_debugfs_create_files(sor->debugfs_files, count, root, minor); in tegra_sor_late_register()
1708 struct tegra_sor *sor = to_sor(output); in tegra_sor_early_unregister() local
1710 drm_debugfs_remove_files(sor->debugfs_files, count, in tegra_sor_early_unregister()
1712 kfree(sor->debugfs_files); in tegra_sor_early_unregister()
1713 sor->debugfs_files = NULL; in tegra_sor_early_unregister()
1736 struct tegra_sor *sor = to_sor(output); in tegra_sor_connector_detect() local
1738 if (sor->aux) in tegra_sor_connector_detect()
1739 return drm_dp_aux_detect(sor->aux); in tegra_sor_connector_detect()
1773 struct tegra_sor *sor = to_sor(output); in tegra_sor_connector_get_modes() local
1776 if (sor->aux) in tegra_sor_connector_get_modes()
1777 drm_dp_aux_enable(sor->aux); in tegra_sor_connector_get_modes()
1781 if (sor->aux) in tegra_sor_connector_get_modes()
1782 drm_dp_aux_disable(sor->aux); in tegra_sor_connector_get_modes()
1808 struct tegra_sor *sor = to_sor(output); in tegra_sor_encoder_atomic_check() local
1826 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, in tegra_sor_encoder_atomic_check()
1859 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor, in tegra_sor_hdmi_write_infopack() argument
1881 dev_err(sor->dev, "unsupported infoframe type: %02x\n", in tegra_sor_hdmi_write_infopack()
1889 tegra_sor_writel(sor, value, offset); in tegra_sor_hdmi_write_infopack()
1901 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1906 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1911 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor, in tegra_sor_hdmi_setup_avi_infoframe() argument
1920 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1924 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1927 &sor->output.connector, mode); in tegra_sor_hdmi_setup_avi_infoframe()
1929 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); in tegra_sor_hdmi_setup_avi_infoframe()
1935 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err); in tegra_sor_hdmi_setup_avi_infoframe()
1939 tegra_sor_hdmi_write_infopack(sor, buffer, err); in tegra_sor_hdmi_setup_avi_infoframe()
1942 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1945 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1950 static void tegra_sor_write_eld(struct tegra_sor *sor) in tegra_sor_write_eld() argument
1952 size_t length = drm_eld_size(sor->output.connector.eld), i; in tegra_sor_write_eld()
1955 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i], in tegra_sor_write_eld()
1965 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR); in tegra_sor_write_eld()
1968 static void tegra_sor_audio_prepare(struct tegra_sor *sor) in tegra_sor_audio_prepare() argument
1978 tegra_sor_writel(sor, value, SOR_INT_ENABLE); in tegra_sor_audio_prepare()
1979 tegra_sor_writel(sor, value, SOR_INT_MASK); in tegra_sor_audio_prepare()
1981 tegra_sor_write_eld(sor); in tegra_sor_audio_prepare()
1984 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE); in tegra_sor_audio_prepare()
1987 static void tegra_sor_audio_unprepare(struct tegra_sor *sor) in tegra_sor_audio_unprepare() argument
1989 tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE); in tegra_sor_audio_unprepare()
1990 tegra_sor_writel(sor, 0, SOR_INT_MASK); in tegra_sor_audio_unprepare()
1991 tegra_sor_writel(sor, 0, SOR_INT_ENABLE); in tegra_sor_audio_unprepare()
1994 static void tegra_sor_audio_enable(struct tegra_sor *sor) in tegra_sor_audio_enable() argument
1998 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL); in tegra_sor_audio_enable()
2005 if (sor->format.channels != 2) in tegra_sor_audio_enable()
2012 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL); in tegra_sor_audio_enable()
2015 tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE); in tegra_sor_audio_enable()
2018 static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor) in tegra_sor_hdmi_enable_audio_infoframe() argument
2027 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err); in tegra_sor_hdmi_enable_audio_infoframe()
2031 frame.channels = sor->format.channels; in tegra_sor_hdmi_enable_audio_infoframe()
2035 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err); in tegra_sor_hdmi_enable_audio_infoframe()
2039 tegra_sor_hdmi_write_infopack(sor, buffer, err); in tegra_sor_hdmi_enable_audio_infoframe()
2041 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_enable_audio_infoframe()
2044 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_enable_audio_infoframe()
2049 static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor) in tegra_sor_hdmi_audio_enable() argument
2053 tegra_sor_audio_enable(sor); in tegra_sor_hdmi_audio_enable()
2055 tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL); in tegra_sor_hdmi_audio_enable()
2060 tegra_sor_writel(sor, value, SOR_HDMI_SPARE); in tegra_sor_hdmi_audio_enable()
2064 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW); in tegra_sor_hdmi_audio_enable()
2068 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH); in tegra_sor_hdmi_audio_enable()
2072 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2074 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2075 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320); in tegra_sor_hdmi_audio_enable()
2076 tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320); in tegra_sor_hdmi_audio_enable()
2078 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441); in tegra_sor_hdmi_audio_enable()
2079 tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441); in tegra_sor_hdmi_audio_enable()
2081 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882); in tegra_sor_hdmi_audio_enable()
2082 tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882); in tegra_sor_hdmi_audio_enable()
2084 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764); in tegra_sor_hdmi_audio_enable()
2085 tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764); in tegra_sor_hdmi_audio_enable()
2087 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2088 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480); in tegra_sor_hdmi_audio_enable()
2089 tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480); in tegra_sor_hdmi_audio_enable()
2091 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2092 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960); in tegra_sor_hdmi_audio_enable()
2093 tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960); in tegra_sor_hdmi_audio_enable()
2095 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2096 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920); in tegra_sor_hdmi_audio_enable()
2097 tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920); in tegra_sor_hdmi_audio_enable()
2099 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2101 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2103 tegra_sor_hdmi_enable_audio_infoframe(sor); in tegra_sor_hdmi_audio_enable()
2106 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor) in tegra_sor_hdmi_disable_audio_infoframe() argument
2110 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2112 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2115 static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor) in tegra_sor_hdmi_audio_disable() argument
2117 tegra_sor_hdmi_disable_audio_infoframe(sor); in tegra_sor_hdmi_audio_disable()
2121 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency) in tegra_sor_hdmi_find_settings() argument
2125 for (i = 0; i < sor->num_settings; i++) in tegra_sor_hdmi_find_settings()
2126 if (frequency <= sor->settings[i].frequency) in tegra_sor_hdmi_find_settings()
2127 return &sor->settings[i]; in tegra_sor_hdmi_find_settings()
2132 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor) in tegra_sor_hdmi_disable_scrambling() argument
2136 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2139 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2142 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor) in tegra_sor_hdmi_scdc_disable() argument
2144 drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, false); in tegra_sor_hdmi_scdc_disable()
2145 drm_scdc_set_scrambling(&sor->output.connector, false); in tegra_sor_hdmi_scdc_disable()
2147 tegra_sor_hdmi_disable_scrambling(sor); in tegra_sor_hdmi_scdc_disable()
2150 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor) in tegra_sor_hdmi_scdc_stop() argument
2152 if (sor->scdc_enabled) { in tegra_sor_hdmi_scdc_stop()
2153 cancel_delayed_work_sync(&sor->scdc); in tegra_sor_hdmi_scdc_stop()
2154 tegra_sor_hdmi_scdc_disable(sor); in tegra_sor_hdmi_scdc_stop()
2158 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor) in tegra_sor_hdmi_enable_scrambling() argument
2162 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2165 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2168 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor) in tegra_sor_hdmi_scdc_enable() argument
2170 drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, true); in tegra_sor_hdmi_scdc_enable()
2171 drm_scdc_set_scrambling(&sor->output.connector, true); in tegra_sor_hdmi_scdc_enable()
2173 tegra_sor_hdmi_enable_scrambling(sor); in tegra_sor_hdmi_scdc_enable()
2178 struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work); in tegra_sor_hdmi_scdc_work() local
2180 if (!drm_scdc_get_scrambling_status(&sor->output.connector)) { in tegra_sor_hdmi_scdc_work()
2182 tegra_sor_hdmi_scdc_enable(sor); in tegra_sor_hdmi_scdc_work()
2185 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); in tegra_sor_hdmi_scdc_work()
2188 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor) in tegra_sor_hdmi_scdc_start() argument
2190 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc; in tegra_sor_hdmi_scdc_start()
2193 mode = &sor->output.encoder.crtc->state->adjusted_mode; in tegra_sor_hdmi_scdc_start()
2196 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); in tegra_sor_hdmi_scdc_start()
2197 tegra_sor_hdmi_scdc_enable(sor); in tegra_sor_hdmi_scdc_start()
2198 sor->scdc_enabled = true; in tegra_sor_hdmi_scdc_start()
2206 struct tegra_sor *sor = to_sor(output); in tegra_sor_hdmi_disable() local
2210 tegra_sor_audio_unprepare(sor); in tegra_sor_hdmi_disable()
2211 tegra_sor_hdmi_scdc_stop(sor); in tegra_sor_hdmi_disable()
2213 err = tegra_sor_detach(sor); in tegra_sor_hdmi_disable()
2215 dev_err(sor->dev, "failed to detach SOR: %d\n", err); in tegra_sor_hdmi_disable()
2217 tegra_sor_writel(sor, 0, SOR_STATE1); in tegra_sor_hdmi_disable()
2218 tegra_sor_update(sor); in tegra_sor_hdmi_disable()
2223 if (!sor->soc->has_nvdisplay) in tegra_sor_hdmi_disable()
2226 value &= ~SOR_ENABLE(sor->index); in tegra_sor_hdmi_disable()
2232 err = tegra_sor_power_down(sor); in tegra_sor_hdmi_disable()
2234 dev_err(sor->dev, "failed to power down SOR: %d\n", err); in tegra_sor_hdmi_disable()
2236 err = tegra_io_pad_power_disable(sor->pad); in tegra_sor_hdmi_disable()
2238 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); in tegra_sor_hdmi_disable()
2240 host1x_client_suspend(&sor->client); in tegra_sor_hdmi_disable()
2249 struct tegra_sor *sor = to_sor(output); in tegra_sor_hdmi_enable() local
2261 err = host1x_client_resume(&sor->client); in tegra_sor_hdmi_enable()
2263 dev_err(sor->dev, "failed to resume: %d\n", err); in tegra_sor_hdmi_enable()
2268 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_hdmi_enable()
2270 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_hdmi_enable()
2274 div = clk_get_rate(sor->clk) / 1000000 * 4; in tegra_sor_hdmi_enable()
2276 err = tegra_io_pad_power_enable(sor->pad); in tegra_sor_hdmi_enable()
2278 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); in tegra_sor_hdmi_enable()
2282 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2284 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2288 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2290 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2292 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2295 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2297 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2299 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2303 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2306 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2310 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2313 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2316 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2325 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2328 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2335 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2348 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2353 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2356 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2358 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2363 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2367 tegra_sor_writel(sor, value, SOR_SEQ_CTL); in tegra_sor_hdmi_enable()
2371 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); in tegra_sor_hdmi_enable()
2372 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); in tegra_sor_hdmi_enable()
2374 if (!sor->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2377 tegra_sor_writel(sor, value, SOR_REFCLK); in tegra_sor_hdmi_enable()
2382 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | in tegra_sor_hdmi_enable()
2385 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); in tegra_sor_hdmi_enable()
2386 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_hdmi_enable()
2395 err = clk_set_parent(sor->clk_pad, sor->clk_dp); in tegra_sor_hdmi_enable()
2397 dev_err(sor->dev, "failed to select pad parent clock: %d\n", in tegra_sor_hdmi_enable()
2404 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); in tegra_sor_hdmi_enable()
2406 dev_err(sor->dev, "failed to select SOR parent clock: %d\n", in tegra_sor_hdmi_enable()
2412 err = clk_set_parent(sor->clk, sor->clk_parent); in tegra_sor_hdmi_enable()
2414 dev_err(sor->dev, "failed to select output parent clock: %d\n", in tegra_sor_hdmi_enable()
2420 rate = clk_get_rate(sor->clk_parent); in tegra_sor_hdmi_enable()
2427 clk_set_rate(sor->clk, rate); in tegra_sor_hdmi_enable()
2429 if (!sor->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2436 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); in tegra_sor_hdmi_enable()
2443 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); in tegra_sor_hdmi_enable()
2464 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode); in tegra_sor_hdmi_enable()
2466 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); in tegra_sor_hdmi_enable()
2469 tegra_sor_hdmi_disable_audio_infoframe(sor); in tegra_sor_hdmi_enable()
2472 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2475 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2478 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2480 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2483 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); in tegra_sor_hdmi_enable()
2485 dev_err(sor->dev, "no settings for pixel clock %d Hz\n", in tegra_sor_hdmi_enable()
2490 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2497 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2500 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2506 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2508 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2517 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2523 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_hdmi_enable()
2529 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_hdmi_enable()
2531 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2535 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2537 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2540 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2543 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2545 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2583 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2586 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2588 err = tegra_sor_power_up(sor, 250); in tegra_sor_hdmi_enable()
2590 dev_err(sor->dev, "failed to power up SOR: %d\n", err); in tegra_sor_hdmi_enable()
2593 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2596 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2599 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2602 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2604 tegra_sor_mode_set(sor, mode, state); in tegra_sor_hdmi_enable()
2606 tegra_sor_update(sor); in tegra_sor_hdmi_enable()
2609 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2611 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2613 err = tegra_sor_attach(sor); in tegra_sor_hdmi_enable()
2615 dev_err(sor->dev, "failed to attach SOR: %d\n", err); in tegra_sor_hdmi_enable()
2620 if (!sor->soc->has_nvdisplay) in tegra_sor_hdmi_enable()
2623 value |= SOR_ENABLE(sor->index); in tegra_sor_hdmi_enable()
2628 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2631 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2636 err = tegra_sor_wakeup(sor); in tegra_sor_hdmi_enable()
2638 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); in tegra_sor_hdmi_enable()
2640 tegra_sor_hdmi_scdc_start(sor); in tegra_sor_hdmi_enable()
2641 tegra_sor_audio_prepare(sor); in tegra_sor_hdmi_enable()
2654 struct tegra_sor *sor = to_sor(output); in tegra_sor_dp_disable() local
2666 err = drm_dp_link_power_down(sor->aux, &sor->link); in tegra_sor_dp_disable()
2668 dev_err(sor->dev, "failed to power down link: %d\n", in tegra_sor_dp_disable()
2672 err = tegra_sor_detach(sor); in tegra_sor_dp_disable()
2674 dev_err(sor->dev, "failed to detach SOR: %d\n", err); in tegra_sor_dp_disable()
2676 tegra_sor_writel(sor, 0, SOR_STATE1); in tegra_sor_dp_disable()
2677 tegra_sor_update(sor); in tegra_sor_dp_disable()
2680 value &= ~SOR_ENABLE(sor->index); in tegra_sor_dp_disable()
2684 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_dp_disable()
2688 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_dp_disable()
2689 tegra_sor_update(sor); in tegra_sor_dp_disable()
2692 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_dp_disable()
2694 dev_err(sor->dev, "failed to set safe clock: %d\n", err); in tegra_sor_dp_disable()
2696 err = tegra_sor_power_down(sor); in tegra_sor_dp_disable()
2698 dev_err(sor->dev, "failed to power down SOR: %d\n", err); in tegra_sor_dp_disable()
2700 err = tegra_io_pad_power_disable(sor->pad); in tegra_sor_dp_disable()
2702 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); in tegra_sor_dp_disable()
2704 err = drm_dp_aux_disable(sor->aux); in tegra_sor_dp_disable()
2706 dev_err(sor->dev, "failed disable DPAUX: %d\n", err); in tegra_sor_dp_disable()
2711 host1x_client_suspend(&sor->client); in tegra_sor_dp_disable()
2718 struct tegra_sor *sor = to_sor(output); in tegra_sor_dp_enable() local
2731 err = host1x_client_resume(&sor->client); in tegra_sor_dp_enable()
2733 dev_err(sor->dev, "failed to resume: %d\n", err); in tegra_sor_dp_enable()
2738 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_dp_enable()
2740 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_dp_enable()
2742 err = tegra_io_pad_power_enable(sor->pad); in tegra_sor_dp_enable()
2744 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err); in tegra_sor_dp_enable()
2748 err = drm_dp_aux_enable(sor->aux); in tegra_sor_dp_enable()
2750 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err); in tegra_sor_dp_enable()
2752 err = drm_dp_link_probe(sor->aux, &sor->link); in tegra_sor_dp_enable()
2754 dev_err(sor->dev, "failed to probe DP link: %d\n", err); in tegra_sor_dp_enable()
2756 tegra_sor_filter_rates(sor); in tegra_sor_dp_enable()
2758 err = drm_dp_link_choose(&sor->link, mode, info); in tegra_sor_dp_enable()
2760 dev_err(sor->dev, "failed to choose link: %d\n", err); in tegra_sor_dp_enable()
2765 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2767 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2771 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2773 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2775 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2777 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2779 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2782 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2786 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2789 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2791 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_dp_enable()
2799 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_dp_enable()
2803 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_enable()
2811 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_enable()
2814 tegra_sor_writel(sor, 0, SOR_LVDS); in tegra_sor_dp_enable()
2816 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2822 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2826 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | in tegra_sor_dp_enable()
2829 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); in tegra_sor_dp_enable()
2830 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_dp_enable()
2839 err = clk_set_parent(sor->clk_pad, sor->clk_parent); in tegra_sor_dp_enable()
2841 dev_err(sor->dev, "failed to select pad parent clock: %d\n", in tegra_sor_dp_enable()
2848 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); in tegra_sor_dp_enable()
2850 dev_err(sor->dev, "failed to select SOR parent clock: %d\n", in tegra_sor_dp_enable()
2856 err = clk_set_parent(sor->clk, sor->clk_parent); in tegra_sor_dp_enable()
2858 dev_err(sor->dev, "failed to select output parent clock: %d\n", in tegra_sor_dp_enable()
2864 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_dp_enable()
2867 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_dp_enable()
2870 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_dp_enable()
2872 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_dp_enable()
2874 tegra_sor_dp_term_calibrate(sor); in tegra_sor_dp_enable()
2876 err = drm_dp_link_train(&sor->link); in tegra_sor_dp_enable()
2878 dev_err(sor->dev, "link training failed: %d\n", err); in tegra_sor_dp_enable()
2880 dev_dbg(sor->dev, "link training succeeded\n"); in tegra_sor_dp_enable()
2882 err = drm_dp_link_power_up(sor->aux, &sor->link); in tegra_sor_dp_enable()
2884 dev_err(sor->dev, "failed to power up DP link: %d\n", err); in tegra_sor_dp_enable()
2890 err = tegra_sor_compute_config(sor, mode, &config, &sor->link); in tegra_sor_dp_enable()
2892 dev_err(sor->dev, "failed to compute configuration: %d\n", err); in tegra_sor_dp_enable()
2894 tegra_sor_apply_config(sor, &config); in tegra_sor_dp_enable()
2895 tegra_sor_mode_set(sor, mode, state); in tegra_sor_dp_enable()
2901 tegra_sor_writel(sor, value, SOR_CSTM); in tegra_sor_dp_enable()
2904 err = tegra_sor_setup_pwm(sor, 250); in tegra_sor_dp_enable()
2906 dev_err(sor->dev, "failed to setup PWM: %d\n", err); in tegra_sor_dp_enable()
2909 tegra_sor_update(sor); in tegra_sor_dp_enable()
2911 err = tegra_sor_power_up(sor, 250); in tegra_sor_dp_enable()
2913 dev_err(sor->dev, "failed to power up SOR: %d\n", err); in tegra_sor_dp_enable()
2916 err = tegra_sor_attach(sor); in tegra_sor_dp_enable()
2918 dev_err(sor->dev, "failed to attach SOR: %d\n", err); in tegra_sor_dp_enable()
2921 value |= SOR_ENABLE(sor->index); in tegra_sor_dp_enable()
2926 err = tegra_sor_wakeup(sor); in tegra_sor_dp_enable()
2928 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); in tegra_sor_dp_enable()
2947 static int tegra_sor_enable_regulator(struct tegra_sor *sor, struct regulator *reg) in tegra_sor_enable_regulator() argument
2955 return devm_add_action_or_reset(sor->dev, tegra_sor_disable_regulator, reg); in tegra_sor_enable_regulator()
2958 static int tegra_sor_hdmi_probe(struct tegra_sor *sor) in tegra_sor_hdmi_probe() argument
2962 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp"); in tegra_sor_hdmi_probe()
2963 if (IS_ERR(sor->avdd_io_supply)) in tegra_sor_hdmi_probe()
2964 return dev_err_probe(sor->dev, PTR_ERR(sor->avdd_io_supply), in tegra_sor_hdmi_probe()
2967 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply); in tegra_sor_hdmi_probe()
2969 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", in tegra_sor_hdmi_probe()
2974 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll"); in tegra_sor_hdmi_probe()
2975 if (IS_ERR(sor->vdd_pll_supply)) in tegra_sor_hdmi_probe()
2976 return dev_err_probe(sor->dev, PTR_ERR(sor->vdd_pll_supply), in tegra_sor_hdmi_probe()
2979 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply); in tegra_sor_hdmi_probe()
2981 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", in tegra_sor_hdmi_probe()
2986 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); in tegra_sor_hdmi_probe()
2987 if (IS_ERR(sor->hdmi_supply)) in tegra_sor_hdmi_probe()
2988 return dev_err_probe(sor->dev, PTR_ERR(sor->hdmi_supply), in tegra_sor_hdmi_probe()
2991 err = tegra_sor_enable_regulator(sor, sor->hdmi_supply); in tegra_sor_hdmi_probe()
2993 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); in tegra_sor_hdmi_probe()
2997 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work); in tegra_sor_hdmi_probe()
3009 static int tegra_sor_dp_probe(struct tegra_sor *sor) in tegra_sor_dp_probe() argument
3013 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp"); in tegra_sor_dp_probe()
3014 if (IS_ERR(sor->avdd_io_supply)) in tegra_sor_dp_probe()
3015 return PTR_ERR(sor->avdd_io_supply); in tegra_sor_dp_probe()
3017 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply); in tegra_sor_dp_probe()
3021 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll"); in tegra_sor_dp_probe()
3022 if (IS_ERR(sor->vdd_pll_supply)) in tegra_sor_dp_probe()
3023 return PTR_ERR(sor->vdd_pll_supply); in tegra_sor_dp_probe()
3025 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply); in tegra_sor_dp_probe()
3041 struct tegra_sor *sor = host1x_client_to_sor(client); in tegra_sor_init() local
3046 if (!sor->aux) { in tegra_sor_init()
3047 if (sor->ops == &tegra_sor_hdmi_ops) { in tegra_sor_init()
3051 } else if (sor->soc->supports_lvds) { in tegra_sor_init()
3056 if (sor->output.panel) { in tegra_sor_init()
3066 sor->link.ops = &tegra_sor_dp_link_ops; in tegra_sor_init()
3067 sor->link.aux = sor->aux; in tegra_sor_init()
3070 sor->output.dev = sor->dev; in tegra_sor_init()
3072 drm_connector_init_with_ddc(drm, &sor->output.connector, in tegra_sor_init()
3075 sor->output.ddc); in tegra_sor_init()
3076 drm_connector_helper_add(&sor->output.connector, in tegra_sor_init()
3078 sor->output.connector.dpms = DRM_MODE_DPMS_OFF; in tegra_sor_init()
3080 drm_simple_encoder_init(drm, &sor->output.encoder, encoder); in tegra_sor_init()
3081 drm_encoder_helper_add(&sor->output.encoder, helpers); in tegra_sor_init()
3083 drm_connector_attach_encoder(&sor->output.connector, in tegra_sor_init()
3084 &sor->output.encoder); in tegra_sor_init()
3085 drm_connector_register(&sor->output.connector); in tegra_sor_init()
3087 err = tegra_output_init(drm, &sor->output); in tegra_sor_init()
3093 tegra_output_find_possible_crtcs(&sor->output, drm); in tegra_sor_init()
3095 if (sor->aux) { in tegra_sor_init()
3096 err = drm_dp_aux_attach(sor->aux, &sor->output); in tegra_sor_init()
3098 dev_err(sor->dev, "failed to attach DP: %d\n", err); in tegra_sor_init()
3107 if (sor->rst) { in tegra_sor_init()
3108 err = pm_runtime_resume_and_get(sor->dev); in tegra_sor_init()
3110 dev_err(sor->dev, "failed to get runtime PM: %d\n", err); in tegra_sor_init()
3114 err = reset_control_acquire(sor->rst); in tegra_sor_init()
3116 dev_err(sor->dev, "failed to acquire SOR reset: %d\n", in tegra_sor_init()
3121 err = reset_control_assert(sor->rst); in tegra_sor_init()
3123 dev_err(sor->dev, "failed to assert SOR reset: %d\n", in tegra_sor_init()
3129 err = clk_prepare_enable(sor->clk); in tegra_sor_init()
3131 dev_err(sor->dev, "failed to enable clock: %d\n", err); in tegra_sor_init()
3137 if (sor->rst) { in tegra_sor_init()
3138 err = reset_control_deassert(sor->rst); in tegra_sor_init()
3140 dev_err(sor->dev, "failed to deassert SOR reset: %d\n", in tegra_sor_init()
3142 clk_disable_unprepare(sor->clk); in tegra_sor_init()
3146 reset_control_release(sor->rst); in tegra_sor_init()
3147 pm_runtime_put(sor->dev); in tegra_sor_init()
3150 err = clk_prepare_enable(sor->clk_safe); in tegra_sor_init()
3152 clk_disable_unprepare(sor->clk); in tegra_sor_init()
3156 err = clk_prepare_enable(sor->clk_dp); in tegra_sor_init()
3158 clk_disable_unprepare(sor->clk_safe); in tegra_sor_init()
3159 clk_disable_unprepare(sor->clk); in tegra_sor_init()
3166 if (sor->rst) in tegra_sor_init()
3167 pm_runtime_put(sor->dev); in tegra_sor_init()
3174 struct tegra_sor *sor = host1x_client_to_sor(client); in tegra_sor_exit() local
3177 tegra_output_exit(&sor->output); in tegra_sor_exit()
3179 if (sor->aux) { in tegra_sor_exit()
3180 err = drm_dp_aux_detach(sor->aux); in tegra_sor_exit()
3182 dev_err(sor->dev, "failed to detach DP: %d\n", err); in tegra_sor_exit()
3187 clk_disable_unprepare(sor->clk_safe); in tegra_sor_exit()
3188 clk_disable_unprepare(sor->clk_dp); in tegra_sor_exit()
3189 clk_disable_unprepare(sor->clk); in tegra_sor_exit()
3196 struct tegra_sor *sor = host1x_client_to_sor(client); in tegra_sor_runtime_suspend() local
3200 if (sor->rst) { in tegra_sor_runtime_suspend()
3201 err = reset_control_assert(sor->rst); in tegra_sor_runtime_suspend()
3207 reset_control_release(sor->rst); in tegra_sor_runtime_suspend()
3212 clk_disable_unprepare(sor->clk); in tegra_sor_runtime_suspend()
3220 struct tegra_sor *sor = host1x_client_to_sor(client); in tegra_sor_runtime_resume() local
3230 err = clk_prepare_enable(sor->clk); in tegra_sor_runtime_resume()
3238 if (sor->rst) { in tegra_sor_runtime_resume()
3239 err = reset_control_acquire(sor->rst); in tegra_sor_runtime_resume()
3245 err = reset_control_deassert(sor->rst); in tegra_sor_runtime_resume()
3255 reset_control_release(sor->rst); in tegra_sor_runtime_resume()
3257 clk_disable_unprepare(sor->clk); in tegra_sor_runtime_resume()
3637 static int tegra_sor_parse_dt(struct tegra_sor *sor) in tegra_sor_parse_dt() argument
3639 struct device_node *np = sor->dev->of_node; in tegra_sor_parse_dt()
3645 if (sor->soc->has_nvdisplay) { in tegra_sor_parse_dt()
3650 sor->index = value; in tegra_sor_parse_dt()
3656 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index; in tegra_sor_parse_dt()
3658 if (!sor->soc->supports_audio) in tegra_sor_parse_dt()
3659 sor->index = 0; in tegra_sor_parse_dt()
3661 sor->index = 1; in tegra_sor_parse_dt()
3668 sor->xbar_cfg[i] = sor->soc->xbar_cfg[i]; in tegra_sor_parse_dt()
3672 sor->xbar_cfg[i] = xbar_cfg[i]; in tegra_sor_parse_dt()
3680 struct tegra_sor *sor = data; in tegra_sor_irq() local
3683 value = tegra_sor_readl(sor, SOR_INT_STATUS); in tegra_sor_irq()
3684 tegra_sor_writel(sor, value, SOR_INT_STATUS); in tegra_sor_irq()
3687 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0); in tegra_sor_irq()
3694 tegra_hda_parse_format(format, &sor->format); in tegra_sor_irq()
3696 if (sor->ops->audio_enable) in tegra_sor_irq()
3697 sor->ops->audio_enable(sor); in tegra_sor_irq()
3699 if (sor->ops->audio_disable) in tegra_sor_irq()
3700 sor->ops->audio_disable(sor); in tegra_sor_irq()
3710 struct tegra_sor *sor; in tegra_sor_probe() local
3713 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); in tegra_sor_probe()
3714 if (!sor) in tegra_sor_probe()
3717 sor->soc = of_device_get_match_data(&pdev->dev); in tegra_sor_probe()
3718 sor->output.dev = sor->dev = &pdev->dev; in tegra_sor_probe()
3720 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings, in tegra_sor_probe()
3721 sor->soc->num_settings * in tegra_sor_probe()
3722 sizeof(*sor->settings), in tegra_sor_probe()
3724 if (!sor->settings) in tegra_sor_probe()
3727 sor->num_settings = sor->soc->num_settings; in tegra_sor_probe()
3731 sor->aux = drm_dp_aux_find_by_of_node(np); in tegra_sor_probe()
3734 if (!sor->aux) in tegra_sor_probe()
3737 if (get_device(sor->aux->dev)) in tegra_sor_probe()
3738 sor->output.ddc = &sor->aux->ddc; in tegra_sor_probe()
3741 if (!sor->aux) { in tegra_sor_probe()
3742 if (sor->soc->supports_hdmi) { in tegra_sor_probe()
3743 sor->ops = &tegra_sor_hdmi_ops; in tegra_sor_probe()
3744 sor->pad = TEGRA_IO_PAD_HDMI; in tegra_sor_probe()
3745 } else if (sor->soc->supports_lvds) { in tegra_sor_probe()
3760 sor->ops = &tegra_sor_dp_ops; in tegra_sor_probe()
3761 sor->pad = TEGRA_IO_PAD_LVDS; in tegra_sor_probe()
3764 err = tegra_sor_parse_dt(sor); in tegra_sor_probe()
3768 err = tegra_output_probe(&sor->output); in tegra_sor_probe()
3774 if (sor->ops && sor->ops->probe) { in tegra_sor_probe()
3775 err = sor->ops->probe(sor); in tegra_sor_probe()
3778 sor->ops->name, err); in tegra_sor_probe()
3783 sor->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_sor_probe()
3784 if (IS_ERR(sor->regs)) { in tegra_sor_probe()
3785 err = PTR_ERR(sor->regs); in tegra_sor_probe()
3793 sor->irq = err; in tegra_sor_probe()
3795 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0, in tegra_sor_probe()
3796 dev_name(sor->dev), sor); in tegra_sor_probe()
3802 sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor"); in tegra_sor_probe()
3803 if (IS_ERR(sor->rst)) { in tegra_sor_probe()
3804 err = PTR_ERR(sor->rst); in tegra_sor_probe()
3818 sor->rst = NULL; in tegra_sor_probe()
3821 sor->clk = devm_clk_get(&pdev->dev, NULL); in tegra_sor_probe()
3822 if (IS_ERR(sor->clk)) { in tegra_sor_probe()
3823 err = PTR_ERR(sor->clk); in tegra_sor_probe()
3828 if (sor->soc->supports_hdmi || sor->soc->supports_dp) { in tegra_sor_probe()
3842 sor->clk_out = devm_clk_get(&pdev->dev, name); in tegra_sor_probe()
3843 if (IS_ERR(sor->clk_out)) { in tegra_sor_probe()
3844 err = PTR_ERR(sor->clk_out); in tegra_sor_probe()
3845 dev_err(sor->dev, "failed to get %s clock: %d\n", in tegra_sor_probe()
3851 sor->clk_out = sor->clk; in tegra_sor_probe()
3854 sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); in tegra_sor_probe()
3855 if (IS_ERR(sor->clk_parent)) { in tegra_sor_probe()
3856 err = PTR_ERR(sor->clk_parent); in tegra_sor_probe()
3861 sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); in tegra_sor_probe()
3862 if (IS_ERR(sor->clk_safe)) { in tegra_sor_probe()
3863 err = PTR_ERR(sor->clk_safe); in tegra_sor_probe()
3868 sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); in tegra_sor_probe()
3869 if (IS_ERR(sor->clk_dp)) { in tegra_sor_probe()
3870 err = PTR_ERR(sor->clk_dp); in tegra_sor_probe()
3879 sor->clk_pad = devm_clk_get(&pdev->dev, "pad"); in tegra_sor_probe()
3880 if (IS_ERR(sor->clk_pad)) { in tegra_sor_probe()
3881 if (sor->clk_pad != ERR_PTR(-ENOENT)) { in tegra_sor_probe()
3882 err = PTR_ERR(sor->clk_pad); in tegra_sor_probe()
3891 sor->clk_pad = NULL; in tegra_sor_probe()
3899 err = clk_set_parent(sor->clk_out, sor->clk_safe); in tegra_sor_probe()
3905 platform_set_drvdata(pdev, sor); in tegra_sor_probe()
3908 host1x_client_init(&sor->client); in tegra_sor_probe()
3909 sor->client.ops = &sor_client_ops; in tegra_sor_probe()
3910 sor->client.dev = &pdev->dev; in tegra_sor_probe()
3916 if (!sor->clk_pad) { in tegra_sor_probe()
3919 name = devm_kasprintf(sor->dev, GFP_KERNEL, "sor%u_pad_clkout", in tegra_sor_probe()
3920 sor->index); in tegra_sor_probe()
3926 err = host1x_client_resume(&sor->client); in tegra_sor_probe()
3928 dev_err(sor->dev, "failed to resume: %d\n", err); in tegra_sor_probe()
3932 sor->clk_pad = tegra_clk_sor_pad_register(sor, name); in tegra_sor_probe()
3933 host1x_client_suspend(&sor->client); in tegra_sor_probe()
3936 if (IS_ERR(sor->clk_pad)) { in tegra_sor_probe()
3937 err = PTR_ERR(sor->clk_pad); in tegra_sor_probe()
3938 dev_err(sor->dev, "failed to register SOR pad clock: %d\n", in tegra_sor_probe()
3943 err = __host1x_client_register(&sor->client); in tegra_sor_probe()
3953 host1x_client_exit(&sor->client); in tegra_sor_probe()
3956 if (sor->aux) in tegra_sor_probe()
3957 sor->output.ddc = NULL; in tegra_sor_probe()
3959 tegra_output_remove(&sor->output); in tegra_sor_probe()
3961 if (sor->aux) in tegra_sor_probe()
3962 put_device(sor->aux->dev); in tegra_sor_probe()
3969 struct tegra_sor *sor = platform_get_drvdata(pdev); in tegra_sor_remove() local
3971 host1x_client_unregister(&sor->client); in tegra_sor_remove()
3975 if (sor->aux) { in tegra_sor_remove()
3976 put_device(sor->aux->dev); in tegra_sor_remove()
3977 sor->output.ddc = NULL; in tegra_sor_remove()
3980 tegra_output_remove(&sor->output); in tegra_sor_remove()
3985 struct tegra_sor *sor = dev_get_drvdata(dev); in tegra_sor_suspend() local
3988 err = tegra_output_suspend(&sor->output); in tegra_sor_suspend()
3994 if (sor->hdmi_supply) { in tegra_sor_suspend()
3995 err = regulator_disable(sor->hdmi_supply); in tegra_sor_suspend()
3997 tegra_output_resume(&sor->output); in tegra_sor_suspend()
4007 struct tegra_sor *sor = dev_get_drvdata(dev); in tegra_sor_resume() local
4010 if (sor->hdmi_supply) { in tegra_sor_resume()
4011 err = regulator_enable(sor->hdmi_supply); in tegra_sor_resume()
4016 err = tegra_output_resume(&sor->output); in tegra_sor_resume()
4020 if (sor->hdmi_supply) in tegra_sor_resume()
4021 regulator_disable(sor->hdmi_supply); in tegra_sor_resume()