Lines Matching refs:ams
277 struct ams { struct
291 static inline void ams_ps_update_reg(struct ams *ams, unsigned int offset, in ams_ps_update_reg() argument
296 val = readl(ams->ps_base + offset); in ams_ps_update_reg()
298 writel(regval, ams->ps_base + offset); in ams_ps_update_reg()
301 static inline void ams_pl_update_reg(struct ams *ams, unsigned int offset, in ams_pl_update_reg() argument
306 val = readl(ams->pl_base + offset); in ams_pl_update_reg()
308 writel(regval, ams->pl_base + offset); in ams_pl_update_reg()
311 static void ams_update_intrmask(struct ams *ams, u64 mask, u64 val) in ams_update_intrmask() argument
315 ams->intr_mask = (ams->intr_mask & ~mask) | (val & mask); in ams_update_intrmask()
317 regval = ~(ams->intr_mask | ams->current_masked_alarm); in ams_update_intrmask()
318 writel(regval, ams->base + AMS_IER_0); in ams_update_intrmask()
320 regval = ~(FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask)); in ams_update_intrmask()
321 writel(regval, ams->base + AMS_IER_1); in ams_update_intrmask()
323 regval = ams->intr_mask | ams->current_masked_alarm; in ams_update_intrmask()
324 writel(regval, ams->base + AMS_IDR_0); in ams_update_intrmask()
326 regval = FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask); in ams_update_intrmask()
327 writel(regval, ams->base + AMS_IDR_1); in ams_update_intrmask()
330 static void ams_disable_all_alarms(struct ams *ams) in ams_disable_all_alarms() argument
333 if (ams->ps_base) { in ams_disable_all_alarms()
334 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, in ams_disable_all_alarms()
336 ams_ps_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, in ams_disable_all_alarms()
341 if (ams->pl_base) { in ams_disable_all_alarms()
342 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, in ams_disable_all_alarms()
344 ams_pl_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, in ams_disable_all_alarms()
349 static void ams_update_ps_alarm(struct ams *ams, unsigned long alarm_mask) in ams_update_ps_alarm() argument
360 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, cfg); in ams_update_ps_alarm()
364 ams_ps_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, cfg); in ams_update_ps_alarm()
367 static void ams_update_pl_alarm(struct ams *ams, unsigned long alarm_mask) in ams_update_pl_alarm() argument
381 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, cfg); in ams_update_pl_alarm()
385 ams_pl_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, cfg); in ams_update_pl_alarm()
388 static void ams_update_alarm(struct ams *ams, unsigned long alarm_mask) in ams_update_alarm() argument
392 if (ams->ps_base) in ams_update_alarm()
393 ams_update_ps_alarm(ams, alarm_mask); in ams_update_alarm()
395 if (ams->pl_base) in ams_update_alarm()
396 ams_update_pl_alarm(ams, alarm_mask); in ams_update_alarm()
398 spin_lock_irqsave(&ams->intr_lock, flags); in ams_update_alarm()
399 ams_update_intrmask(ams, AMS_ISR0_ALARM_MASK, ~alarm_mask); in ams_update_alarm()
400 spin_unlock_irqrestore(&ams->intr_lock, flags); in ams_update_alarm()
405 struct ams *ams = iio_priv(indio_dev); in ams_enable_channel_sequence() local
424 if (ams->ps_base) { in ams_enable_channel_sequence()
426 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, in ams_enable_channel_sequence()
431 writel(regval, ams->ps_base + AMS_REG_SEQ_CH0); in ams_enable_channel_sequence()
434 writel(regval, ams->ps_base + AMS_REG_SEQ_CH2); in ams_enable_channel_sequence()
437 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, in ams_enable_channel_sequence()
441 if (ams->pl_base) { in ams_enable_channel_sequence()
443 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, in ams_enable_channel_sequence()
450 writel(regval, ams->pl_base + AMS_REG_SEQ_CH0); in ams_enable_channel_sequence()
453 writel(regval, ams->pl_base + AMS_REG_SEQ_CH1); in ams_enable_channel_sequence()
456 writel(regval, ams->pl_base + AMS_REG_SEQ_CH2); in ams_enable_channel_sequence()
459 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, in ams_enable_channel_sequence()
464 static int ams_init_device(struct ams *ams) in ams_init_device() argument
471 if (ams->ps_base) { in ams_init_device()
472 writel(AMS_PS_RESET_VALUE, ams->ps_base + AMS_VP_VN); in ams_init_device()
474 ret = readl_poll_timeout(ams->base + AMS_PS_CSTS, reg, (reg & expect), in ams_init_device()
480 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, in ams_init_device()
484 if (ams->pl_base) { in ams_init_device()
485 value = readl(ams->base + AMS_PL_CSTS); in ams_init_device()
489 writel(AMS_PL_RESET_VALUE, ams->pl_base + AMS_VP_VN); in ams_init_device()
492 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, in ams_init_device()
496 ams_disable_all_alarms(ams); in ams_init_device()
499 ams_update_intrmask(ams, AMS_ALARM_MASK, AMS_ALARM_MASK); in ams_init_device()
502 writel(AMS_ISR0_ALARM_MASK, ams->base + AMS_ISR_0); in ams_init_device()
503 writel(AMS_ISR1_ALARM_MASK, ams->base + AMS_ISR_1); in ams_init_device()
508 static int ams_enable_single_channel(struct ams *ams, unsigned int offset) in ams_enable_single_channel() argument
539 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, in ams_enable_single_channel()
543 ams_ps_update_reg(ams, AMS_REG_CONFIG0, AMS_CONF0_CHANNEL_NUM_MASK, in ams_enable_single_channel()
547 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, in ams_enable_single_channel()
553 static int ams_read_vcc_reg(struct ams *ams, unsigned int offset, u32 *data) in ams_read_vcc_reg() argument
559 ret = ams_enable_single_channel(ams, offset); in ams_read_vcc_reg()
564 writel(expect, ams->base + AMS_ISR_1); in ams_read_vcc_reg()
565 ret = readl_poll_timeout(ams->base + AMS_ISR_1, reg, (reg & expect), in ams_read_vcc_reg()
570 *data = readl(ams->base + offset); in ams_read_vcc_reg()
603 static int ams_get_pl_scale(struct ams *ams, int address) in ams_get_pl_scale() argument
620 regval = readl(ams->pl_base + AMS_REG_CONFIG4); in ams_get_pl_scale()
627 regval = readl(ams->pl_base + AMS_REG_CONFIG4); in ams_get_pl_scale()
634 regval = readl(ams->pl_base + AMS_REG_CONFIG4); in ams_get_pl_scale()
641 regval = readl(ams->pl_base + AMS_REG_CONFIG4); in ams_get_pl_scale()
685 struct ams *ams = iio_priv(indio_dev); in ams_read_raw() local
690 mutex_lock(&ams->lock); in ams_read_raw()
692 ret = ams_read_vcc_reg(ams, chan->address, val); in ams_read_raw()
697 *val = readl(ams->pl_base + chan->address); in ams_read_raw()
699 *val = readl(ams->ps_base + chan->address); in ams_read_raw()
703 mutex_unlock(&ams->lock); in ams_read_raw()
712 *val = ams_get_pl_scale(ams, chan->address); in ams_read_raw()
889 struct ams *ams = iio_priv(indio_dev); in ams_read_event_config() local
891 return !!(ams->alarm_mask & ams_get_alarm_mask(chan->scan_index)); in ams_read_event_config()
900 struct ams *ams = iio_priv(indio_dev); in ams_write_event_config() local
905 mutex_lock(&ams->lock); in ams_write_event_config()
908 ams->alarm_mask |= alarm; in ams_write_event_config()
910 ams->alarm_mask &= ~alarm; in ams_write_event_config()
912 ams_update_alarm(ams, ams->alarm_mask); in ams_write_event_config()
914 mutex_unlock(&ams->lock); in ams_write_event_config()
925 struct ams *ams = iio_priv(indio_dev); in ams_read_event_value() local
928 mutex_lock(&ams->lock); in ams_read_event_value()
931 *val = readl(ams->pl_base + offset); in ams_read_event_value()
933 *val = readl(ams->ps_base + offset); in ams_read_event_value()
935 mutex_unlock(&ams->lock); in ams_read_event_value()
946 struct ams *ams = iio_priv(indio_dev); in ams_write_event_value() local
949 mutex_lock(&ams->lock); in ams_write_event_value()
956 ams_pl_update_reg(ams, offset, in ams_write_event_value()
960 ams_ps_update_reg(ams, offset, in ams_write_event_value()
967 writel(val, ams->pl_base + offset); in ams_write_event_value()
969 writel(val, ams->ps_base + offset); in ams_write_event_value()
971 mutex_unlock(&ams->lock); in ams_write_event_value()
1027 struct ams *ams = container_of(work, struct ams, ams_unmask_work.work); in ams_unmask_worker() local
1030 spin_lock_irq(&ams->intr_lock); in ams_unmask_worker()
1032 status = readl(ams->base + AMS_ISR_0); in ams_unmask_worker()
1035 unmask = (ams->current_masked_alarm ^ status) & ams->current_masked_alarm; in ams_unmask_worker()
1038 unmask |= ams->intr_mask; in ams_unmask_worker()
1040 ams->current_masked_alarm &= status; in ams_unmask_worker()
1043 ams->current_masked_alarm &= ~ams->intr_mask; in ams_unmask_worker()
1046 writel(unmask, ams->base + AMS_ISR_0); in ams_unmask_worker()
1048 ams_update_intrmask(ams, ~AMS_ALARM_MASK, ~AMS_ALARM_MASK); in ams_unmask_worker()
1050 spin_unlock_irq(&ams->intr_lock); in ams_unmask_worker()
1053 if (ams->current_masked_alarm) in ams_unmask_worker()
1054 schedule_delayed_work(&ams->ams_unmask_work, in ams_unmask_worker()
1061 struct ams *ams = iio_priv(indio_dev); in ams_irq() local
1064 spin_lock(&ams->intr_lock); in ams_irq()
1066 isr0 = readl(ams->base + AMS_ISR_0); in ams_irq()
1069 isr0 &= ~((ams->intr_mask & AMS_ISR0_ALARM_MASK) | ams->current_masked_alarm); in ams_irq()
1071 spin_unlock(&ams->intr_lock); in ams_irq()
1076 writel(isr0, ams->base + AMS_ISR_0); in ams_irq()
1079 ams->current_masked_alarm |= isr0; in ams_irq()
1080 ams_update_intrmask(ams, ~AMS_ALARM_MASK, ~AMS_ALARM_MASK); in ams_irq()
1084 schedule_delayed_work(&ams->ams_unmask_work, in ams_irq()
1087 spin_unlock(&ams->intr_lock); in ams_irq()
1206 struct ams *ams = data; in ams_iounmap_ps() local
1208 iounmap(ams->ps_base); in ams_iounmap_ps()
1213 struct ams *ams = data; in ams_iounmap_pl() local
1215 iounmap(ams->pl_base); in ams_iounmap_pl()
1223 struct ams *ams = iio_priv(indio_dev); in ams_init_module() local
1228 ams->ps_base = fwnode_iomap(fwnode, 0); in ams_init_module()
1229 if (!ams->ps_base) in ams_init_module()
1231 ret = devm_add_action_or_reset(dev, ams_iounmap_ps, ams); in ams_init_module()
1239 ams->pl_base = fwnode_iomap(fwnode, 0); in ams_init_module()
1240 if (!ams->pl_base) in ams_init_module()
1243 ret = devm_add_action_or_reset(dev, ams_iounmap_pl, ams); in ams_init_module()
1265 struct ams *ams = iio_priv(indio_dev); in ams_parse_firmware() local
1315 ams->pl_base + falling_off); in ams_parse_firmware()
1317 ams->pl_base + rising_off); in ams_parse_firmware()
1320 ams->ps_base + falling_off); in ams_parse_firmware()
1322 ams->ps_base + rising_off); in ams_parse_firmware()
1355 struct ams *ams; in ams_probe() local
1359 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*ams)); in ams_probe()
1363 ams = iio_priv(indio_dev); in ams_probe()
1364 mutex_init(&ams->lock); in ams_probe()
1365 spin_lock_init(&ams->intr_lock); in ams_probe()
1372 ams->base = devm_platform_ioremap_resource(pdev, 0); in ams_probe()
1373 if (IS_ERR(ams->base)) in ams_probe()
1374 return PTR_ERR(ams->base); in ams_probe()
1376 ams->clk = devm_clk_get_enabled(&pdev->dev, NULL); in ams_probe()
1377 if (IS_ERR(ams->clk)) in ams_probe()
1378 return PTR_ERR(ams->clk); in ams_probe()
1380 ret = devm_delayed_work_autocancel(&pdev->dev, &ams->ams_unmask_work, in ams_probe()
1389 ret = ams_init_device(ams); in ams_probe()
1411 struct ams *ams = iio_priv(dev_get_drvdata(dev)); in ams_suspend() local
1413 clk_disable_unprepare(ams->clk); in ams_suspend()
1420 struct ams *ams = iio_priv(dev_get_drvdata(dev)); in ams_resume() local
1422 return clk_prepare_enable(ams->clk); in ams_resume()