Lines Matching refs:dib7000m_write_word
107 static int dib7000m_write_word(struct dib7000m_state *state, u16 reg, u16 val) in dib7000m_write_word() function
144 dib7000m_write_word(state, r, *n++); in dib7000m_write_tab()
195 ret |= dib7000m_write_word(state, 294 + state->reg_offs, smo_mode); in dib7000m_set_output_mode()
196 ret |= dib7000m_write_word(state, 295 + state->reg_offs, fifo_threshold); /* synchronous fread */ in dib7000m_set_output_mode()
197 ret |= dib7000m_write_word(state, 1795, outreg); in dib7000m_set_output_mode()
198 ret |= dib7000m_write_word(state, 1805, sram); in dib7000m_set_output_mode()
204 dib7000m_write_word(state, 909, clk_cfg1); in dib7000m_set_output_mode()
255 dib7000m_write_word(state, 903 + offset, reg_903); in dib7000m_set_power_mode()
256 dib7000m_write_word(state, 904 + offset, reg_904); in dib7000m_set_power_mode()
257 dib7000m_write_word(state, 905 + offset, reg_905); in dib7000m_set_power_mode()
258 dib7000m_write_word(state, 906 + offset, reg_906); in dib7000m_set_power_mode()
270 ret |= dib7000m_write_word(state, 914, reg_914); in dib7000m_set_adc_state()
281 dib7000m_write_word(state, 913, 0); in dib7000m_set_adc_state()
282 dib7000m_write_word(state, 914, reg_914 & 0x3); in dib7000m_set_adc_state()
284 dib7000m_write_word(state, 913, (1 << 15)); in dib7000m_set_adc_state()
285 dib7000m_write_word(state, 914, reg_914 & 0x3); in dib7000m_set_adc_state()
310 ret |= dib7000m_write_word(state, 913, reg_913); in dib7000m_set_adc_state()
311 ret |= dib7000m_write_word(state, 914, reg_914); in dib7000m_set_adc_state()
336 dib7000m_write_word(state, 23, (u16) ((timf >> 16) & 0xffff)); in dib7000m_set_bandwidth()
337 dib7000m_write_word(state, 24, (u16) ((timf ) & 0xffff)); in dib7000m_set_bandwidth()
353 dib7000m_write_word(state, 263 + state->reg_offs, 6); in dib7000m_set_diversity_in()
354 dib7000m_write_word(state, 264 + state->reg_offs, 6); in dib7000m_set_diversity_in()
355 …dib7000m_write_word(state, 266 + state->reg_offs, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0… in dib7000m_set_diversity_in()
357 dib7000m_write_word(state, 263 + state->reg_offs, 1); in dib7000m_set_diversity_in()
358 dib7000m_write_word(state, 264 + state->reg_offs, 0); in dib7000m_set_diversity_in()
359 dib7000m_write_word(state, 266 + state->reg_offs, 0); in dib7000m_set_diversity_in()
370 dib7000m_write_word(state, 929, (0 << 1) | (0 << 0)); in dib7000m_sad_calib()
371 dib7000m_write_word(state, 930, 776); // 0.625*3.3 / 4096 in dib7000m_sad_calib()
374 dib7000m_write_word(state, 929, (1 << 0)); in dib7000m_sad_calib()
375 dib7000m_write_word(state, 929, (0 << 0)); in dib7000m_sad_calib()
384 dib7000m_write_word(state, 18, (u16) (((bw->internal*1000) >> 16) & 0xffff)); in dib7000m_reset_pll_common()
385 dib7000m_write_word(state, 19, (u16) ( (bw->internal*1000) & 0xffff)); in dib7000m_reset_pll_common()
386 dib7000m_write_word(state, 21, (u16) ( (bw->ifreq >> 16) & 0xffff)); in dib7000m_reset_pll_common()
387 dib7000m_write_word(state, 22, (u16) ( bw->ifreq & 0xffff)); in dib7000m_reset_pll_common()
389 dib7000m_write_word(state, 928, bw->sad_cfg); in dib7000m_reset_pll_common()
418 dib7000m_write_word(state, 910, reg_910); // pll cfg in dib7000m_reset_pll()
419 dib7000m_write_word(state, 907, reg_907); // clk cfg0 in dib7000m_reset_pll()
420 dib7000m_write_word(state, 908, 0x0006); // clk_cfg1 in dib7000m_reset_pll()
431 dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0)); in dib7000mc_reset_pll()
438 dib7000m_write_word(state, 908, clk_cfg1); in dib7000mc_reset_pll()
440 dib7000m_write_word(state, 908, clk_cfg1); in dib7000mc_reset_pll()
443 dib7000m_write_word(state, 910, (1 << 12) | (2 << 10) | (bw->modulo << 8) | (bw->ADClkSrc << 7)); in dib7000mc_reset_pll()
451 dib7000m_write_word(st, 773, st->cfg.gpio_dir); in dib7000m_reset_gpio()
452 dib7000m_write_word(st, 774, st->cfg.gpio_val); in dib7000m_reset_gpio()
456 dib7000m_write_word(st, 775, st->cfg.gpio_pwm_pos); in dib7000m_reset_gpio()
458 dib7000m_write_word(st, 780, st->cfg.pwm_freq_div); in dib7000m_reset_gpio()
571 dib7000m_write_word(state, 898, 0xffff); in dib7000m_demod_reset()
572 dib7000m_write_word(state, 899, 0xffff); in dib7000m_demod_reset()
573 dib7000m_write_word(state, 900, 0xff0f); in dib7000m_demod_reset()
574 dib7000m_write_word(state, 901, 0xfffc); in dib7000m_demod_reset()
576 dib7000m_write_word(state, 898, 0); in dib7000m_demod_reset()
577 dib7000m_write_word(state, 899, 0); in dib7000m_demod_reset()
578 dib7000m_write_word(state, 900, 0); in dib7000m_demod_reset()
579 dib7000m_write_word(state, 901, 0); in dib7000m_demod_reset()
593 dib7000m_write_word(state, 1794, dib7000m_read_word(state, 1794) & ~(1 << 1) ); in dib7000m_demod_reset()
602 dib7000m_write_word(state, 1796, 0x0); // select DVB-T output in dib7000m_demod_reset()
605 dib7000m_write_word(state, 261 + state->reg_offs, 2); in dib7000m_demod_reset()
607 dib7000m_write_word(state, 224 + state->reg_offs, 1); in dib7000m_demod_reset()
611 dib7000m_write_word(state, 36, 0x0755); in dib7000m_demod_reset()
613 dib7000m_write_word(state, 36, 0x1f55); in dib7000m_demod_reset()
617 dib7000m_write_word(state, 909, (3 << 10) | (1 << 6)); in dib7000m_demod_reset()
619 dib7000m_write_word(state, 909, (3 << 4) | 1); in dib7000m_demod_reset()
634 dib7000m_write_word(state, 898, 0x0c00); in dib7000m_restart_agc()
635 dib7000m_write_word(state, 898, 0x0000); in dib7000m_restart_agc()
660 return dib7000m_write_word(state, 103, (dib7000m_read_word(state, 103) & 0xff00) | split_offset); in dib7000m_agc_soft_split()
701 dib7000m_write_word(state, 72 , agc->setup); in dib7000m_set_agc_config()
702 dib7000m_write_word(state, 73 , agc->inv_gain); in dib7000m_set_agc_config()
703 dib7000m_write_word(state, 74 , agc->time_stabiliz); in dib7000m_set_agc_config()
704 dib7000m_write_word(state, 97 , (agc->alpha_level << 12) | agc->thlock); in dib7000m_set_agc_config()
707 dib7000m_write_word(state, 98, (agc->alpha_mant << 5) | agc->alpha_exp); in dib7000m_set_agc_config()
708 dib7000m_write_word(state, 99, (agc->beta_mant << 6) | agc->beta_exp); in dib7000m_set_agc_config()
715 dib7000m_write_word(state, 102, state->wbd_ref); in dib7000m_set_agc_config()
717 dib7000m_write_word(state, 102, agc->wbd_ref); in dib7000m_set_agc_config()
719 dib7000m_write_word(state, 103, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8) ); in dib7000m_set_agc_config()
720 dib7000m_write_word(state, 104, agc->agc1_max); in dib7000m_set_agc_config()
721 dib7000m_write_word(state, 105, agc->agc1_min); in dib7000m_set_agc_config()
722 dib7000m_write_word(state, 106, agc->agc2_max); in dib7000m_set_agc_config()
723 dib7000m_write_word(state, 107, agc->agc2_min); in dib7000m_set_agc_config()
724 dib7000m_write_word(state, 108, (agc->agc1_pt1 << 8) | agc->agc1_pt2 ); in dib7000m_set_agc_config()
725 dib7000m_write_word(state, 109, (agc->agc1_slope1 << 8) | agc->agc1_slope2); in dib7000m_set_agc_config()
726 dib7000m_write_word(state, 110, (agc->agc2_pt1 << 8) | agc->agc2_pt2); in dib7000m_set_agc_config()
727 dib7000m_write_word(state, 111, (agc->agc2_slope1 << 8) | agc->agc2_slope2); in dib7000m_set_agc_config()
730 dib7000m_write_word(state, 71, agc->agc1_pt3); in dib7000m_set_agc_config()
733 …dib7000m_write_word(state, 929, (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | … in dib7000m_set_agc_config()
738 dib7000m_write_word(state, 88 + i, b[i]); in dib7000m_set_agc_config()
747 dib7000m_write_word(state, 23, (u16) (timf >> 16)); in dib7000m_update_timf()
748 dib7000m_write_word(state, 24, (u16) (timf & 0xffff)); in dib7000m_update_timf()
779 dib7000m_write_word(state, 75, 32768); in dib7000m_agc_startup()
782 dib7000m_write_word(state, 103, 1 << 8); /* force 0 split on WBD and restart AGC */ in dib7000m_agc_startup()
796 dib7000m_write_word(state, 72, cfg_72 | (1 << 4)); /* freeze AGC loop */ in dib7000m_agc_startup()
797 dib7000m_write_word(state, 103, 2 << 9); /* fast split search 0.25kHz */ in dib7000m_agc_startup()
804 dib7000m_write_word(state, 75, dib7000m_read_word(state, 390)); /* set AGC gain start value */ in dib7000m_agc_startup()
806 dib7000m_write_word(state, 72, cfg_72 & ~(1 << 4)); /* std AGC loop */ in dib7000m_agc_startup()
807 …dib7000m_write_word(state, 103, (state->current_agc->wbd_alpha << 9) | agc_split); /* standard spl… in dib7000m_agc_startup()
877 dib7000m_write_word(state, 0, value); in dib7000m_set_channel()
878 dib7000m_write_word(state, 5, (seq << 4)); in dib7000m_set_channel()
896 dib7000m_write_word(state, 267 + state->reg_offs, value); in dib7000m_set_channel()
901 dib7000m_write_word(state, 26, (6 << 12) | (6 << 8) | 0x80); in dib7000m_set_channel()
904 dib7000m_write_word(state, 29, (0 << 14) | (4 << 10) | (1 << 9) | (3 << 5) | (1 << 4) | (0x3)); in dib7000m_set_channel()
907 dib7000m_write_word(state, 32, (0 << 4) | 0x3); in dib7000m_set_channel()
910 dib7000m_write_word(state, 33, (0 << 4) | 0x5); in dib7000m_set_channel()
958 dib7000m_write_word(state, 214 + value + state->reg_offs, est[value]); in dib7000m_set_channel()
991 ret |= dib7000m_write_word(state, 6, (u16) ((value >> 16) & 0xffff)); // lock0 wait time in dib7000m_autosearch_start()
992 ret |= dib7000m_write_word(state, 7, (u16) (value & 0xffff)); // lock0 wait time in dib7000m_autosearch_start()
994 ret |= dib7000m_write_word(state, 8, (u16) ((value >> 16) & 0xffff)); // lock1 wait time in dib7000m_autosearch_start()
995 ret |= dib7000m_write_word(state, 9, (u16) (value & 0xffff)); // lock1 wait time in dib7000m_autosearch_start()
997 ret |= dib7000m_write_word(state, 10, (u16) ((value >> 16) & 0xffff)); // lock2 wait time in dib7000m_autosearch_start()
998 ret |= dib7000m_write_word(state, 11, (u16) (value & 0xffff)); // lock2 wait time in dib7000m_autosearch_start()
1002 ret |= dib7000m_write_word(state, 0, (u16) (value | (1 << 9))); in dib7000m_autosearch_start()
1006 dib7000m_write_word(state, 1793, 0); in dib7000m_autosearch_start()
1010 ret |= dib7000m_write_word(state, 0, (u16) value); in dib7000m_autosearch_start()
1051 ret |= dib7000m_write_word(state, 898, 0x4000); in dib7000m_tune()
1052 ret |= dib7000m_write_word(state, 898, 0x0000); in dib7000m_tune()
1057 …ret |= dib7000m_write_word(state, 29, (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x… in dib7000m_tune()
1072 ret |= dib7000m_write_word(state, 26, value); in dib7000m_tune()
1082 ret |= dib7000m_write_word(state, 32, value); in dib7000m_tune()
1092 ret |= dib7000m_write_word(state, 33, value); in dib7000m_tune()
1338 return dib7000m_write_word(state, 294 + state->reg_offs, val); in dib7000m_pid_filter_ctrl()
1346 return dib7000m_write_word(state, 300 + state->reg_offs + id, in dib7000m_pid_filter()
1377 dib7000m_write_word(&st, 1796, 0x0); // select DVB-T output
1380 dib7000m_write_word(&st, 1794, (new_addr << 2) | 0x2);
1390 dib7000m_write_word(&st,1794, st.i2c_addr << 2);