Lines Matching refs:last
119 struct tegra210_emc_timing *last = emc->last; in update_clock_tree_delay() local
121 u32 last_timing_rate_mhz = last->rate / 1000; in update_clock_tree_delay()
155 cval = tegra210_emc_actual_osc_clocks(last->run_clocks); in update_clock_tree_delay()
180 cval = tegra210_emc_actual_osc_clocks(last->run_clocks); in update_clock_tree_delay()
208 cval = tegra210_emc_actual_osc_clocks(last->run_clocks); in update_clock_tree_delay()
235 cval = tegra210_emc_actual_osc_clocks(last->run_clocks); in update_clock_tree_delay()
290 cval = tegra210_emc_actual_osc_clocks(last->run_clocks); in update_clock_tree_delay()
317 cval = tegra210_emc_actual_osc_clocks(last->run_clocks); in update_clock_tree_delay()
345 cval = tegra210_emc_actual_osc_clocks(last->run_clocks); in update_clock_tree_delay()
372 cval = tegra210_emc_actual_osc_clocks(last->run_clocks); in update_clock_tree_delay()
404 struct tegra210_emc_timing *last, in periodic_compensation_handler() argument
414 delay = tegra210_emc_actual_osc_clocks(last->run_clocks); in periodic_compensation_handler()
416 delay = 2 + (delay / last->rate); in periodic_compensation_handler()
422 if (last->periodic_training && in periodic_compensation_handler()
430 __COPY_EMA(next, last, C0D0U0); in periodic_compensation_handler()
431 __COPY_EMA(next, last, C0D0U1); in periodic_compensation_handler()
432 __COPY_EMA(next, last, C1D0U0); in periodic_compensation_handler()
433 __COPY_EMA(next, last, C1D0U1); in periodic_compensation_handler()
434 __COPY_EMA(next, last, C0D1U0); in periodic_compensation_handler()
435 __COPY_EMA(next, last, C0D1U1); in periodic_compensation_handler()
436 __COPY_EMA(next, last, C1D1U0); in periodic_compensation_handler()
437 __COPY_EMA(next, last, C1D1U1); in periodic_compensation_handler()
493 struct tegra210_emc_timing *last = emc->last; in tegra210_emc_r21021_periodic_compensation() local
497 if (last->periodic_training) { in tegra210_emc_r21021_periodic_compensation()
539 delay = tegra210_emc_actual_osc_clocks(last->run_clocks); in tegra210_emc_r21021_periodic_compensation()
541 delay /= last->rate + 1; in tegra210_emc_r21021_periodic_compensation()
550 last, last); in tegra210_emc_r21021_periodic_compensation()
556 if (last->tree_margin < ((del * 128 * (last->rate / 1000)) / 1000000)) { in tegra210_emc_r21021_periodic_compensation()
558 value = tegra210_emc_compensate(last, list[i]); in tegra210_emc_r21021_periodic_compensation()
607 struct tegra210_emc_timing *fake, *last = emc->last, *next = emc->next; in tegra210_emc_r21021_set_clock() local
627 fake = tegra210_emc_find_timing(emc, last->rate * 1000UL); in tegra210_emc_r21021_set_clock()
633 if (last->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX] & BIT(31)) in tegra210_emc_r21021_set_clock()
637 last->burst_regs[EMC_ZCAL_INTERVAL_INDEX] == 0) || in tegra210_emc_r21021_set_clock()
651 src_clk_period = 1000000000 / last->rate; in tegra210_emc_r21021_set_clock()
681 emc_dbg(emc, INFO, "last rate: %u, next rate %u\n", last->rate, in tegra210_emc_r21021_set_clock()
739 delay = 1000 * tegra210_emc_actual_osc_clocks(last->run_clocks); in tegra210_emc_r21021_set_clock()
740 udelay((delay / last->rate) + 2); in tegra210_emc_r21021_set_clock()
763 (last->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
767 (last->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
778 emc_writel(emc, last->burst_regs in tegra210_emc_r21021_set_clock()
784 emc_writel(emc, last->burst_regs in tegra210_emc_r21021_set_clock()
791 if ((((last->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] & in tegra210_emc_r21021_set_clock()
795 (((last->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] & in tegra210_emc_r21021_set_clock()
802 last->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX]; in tegra210_emc_r21021_set_clock()
924 tRPST = (last->emc_mrw & 0x80) >> 7; in tegra210_emc_r21021_set_clock()
932 if (last->burst_regs[EMC_RP_INDEX] < tRTM) { in tegra210_emc_r21021_set_clock()
933 if (tRTM > (last->burst_regs[EMC_R2P_INDEX] + in tegra210_emc_r21021_set_clock()
934 last->burst_regs[EMC_RP_INDEX])) { in tegra210_emc_r21021_set_clock()
935 R2P_war = tRTM - last->burst_regs[EMC_RP_INDEX]; in tegra210_emc_r21021_set_clock()
936 RP_war = last->burst_regs[EMC_RP_INDEX]; in tegra210_emc_r21021_set_clock()
937 TRPab_war = last->burst_regs[EMC_TRPAB_INDEX]; in tegra210_emc_r21021_set_clock()
941 last->burst_regs[EMC_RP_INDEX] - 63; in tegra210_emc_r21021_set_clock()
949 R2P_war = last->burst_regs[EMC_R2P_INDEX]; in tegra210_emc_r21021_set_clock()
950 RP_war = last->burst_regs[EMC_RP_INDEX]; in tegra210_emc_r21021_set_clock()
951 TRPab_war = last->burst_regs[EMC_TRPAB_INDEX]; in tegra210_emc_r21021_set_clock()
955 W2P_war = last->burst_regs[EMC_W2P_INDEX] in tegra210_emc_r21021_set_clock()
964 W2P_war = last->burst_regs[ in tegra210_emc_r21021_set_clock()
968 if ((last->burst_regs[EMC_W2P_INDEX] ^ W2P_war) || in tegra210_emc_r21021_set_clock()
969 (last->burst_regs[EMC_R2P_INDEX] ^ R2P_war) || in tegra210_emc_r21021_set_clock()
970 (last->burst_regs[EMC_RP_INDEX] ^ RP_war) || in tegra210_emc_r21021_set_clock()
971 (last->burst_regs[EMC_TRPAB_INDEX] ^ TRPab_war)) { in tegra210_emc_r21021_set_clock()
1220 if (next->rate < last->rate) { in tegra210_emc_r21021_set_clock()
1273 (last->burst_regs[EMC_MRW6_INDEX] & in tegra210_emc_r21021_set_clock()
1277 (last->burst_regs[EMC_MRW14_INDEX] & in tegra210_emc_r21021_set_clock()
1284 (last->burst_regs[EMC_MRW7_INDEX] & in tegra210_emc_r21021_set_clock()
1289 (last->burst_regs[EMC_MRW15_INDEX] & in tegra210_emc_r21021_set_clock()
1664 if (next->rate > last->rate) { in tegra210_emc_r21021_set_clock()