Lines Matching refs:BNX2_RD
270 val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW); in bnx2_reg_rd_ind()
312 val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL); in bnx2_ctx_wr()
492 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); in bnx2_read_phy()
496 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); in bnx2_read_phy()
509 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM); in bnx2_read_phy()
513 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM); in bnx2_read_phy()
530 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); in bnx2_read_phy()
534 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); in bnx2_read_phy()
549 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); in bnx2_write_phy()
553 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); in bnx2_write_phy()
566 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM); in bnx2_write_phy()
579 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); in bnx2_write_phy()
583 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); in bnx2_write_phy()
602 BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD); in bnx2_disable_int()
1326 val = BNX2_RD(bp, BNX2_EMAC_MODE); in bnx2_set_mac_link()
1368 val = BNX2_RD(bp, BNX2_EMAC_TX_MODE); in bnx2_set_mac_link()
1579 val = BNX2_RD(bp, BNX2_EMAC_STATUS); in bnx2_set_link()
2435 mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE); in bnx2_set_mac_loopback()
2464 mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE); in bnx2_set_phy_loopback()
2575 val = BNX2_RD(bp, BNX2_CTX_COMMAND); in bnx2_init_5709_context()
2600 val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL); in bnx2_init_5709_context()
3358 (BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS) & in bnx2_interrupt()
3369 BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD); in bnx2_interrupt()
3425 msi_ctrl = BNX2_RD(bp, BNX2_PCICFG_MSI_CONTROL); in bnx2_chk_missed_msi()
3473 BNX2_RD(bp, BNX2_HC_COMMAND); in bnx2_poll_link()
3959 val = BNX2_RD(bp, BNX2_EMAC_MODE); in bnx2_setup_wol()
3994 val = BNX2_RD(bp, BNX2_RPM_CONFIG); in bnx2_setup_wol()
4033 val = BNX2_RD(bp, BNX2_EMAC_MODE); in bnx2_set_power_state()
4038 val = BNX2_RD(bp, BNX2_RPM_CONFIG); in bnx2_set_power_state()
4088 val = BNX2_RD(bp, BNX2_NVM_SW_ARB); in bnx2_acquire_nvram_lock()
4111 val = BNX2_RD(bp, BNX2_NVM_SW_ARB); in bnx2_release_nvram_lock()
4130 val = BNX2_RD(bp, BNX2_MISC_CFG); in bnx2_enable_nvram_write()
4143 val = BNX2_RD(bp, BNX2_NVM_COMMAND); in bnx2_enable_nvram_write()
4159 val = BNX2_RD(bp, BNX2_MISC_CFG); in bnx2_disable_nvram_write()
4169 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE); in bnx2_enable_nvram_access()
4180 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE); in bnx2_disable_nvram_access()
4216 val = BNX2_RD(bp, BNX2_NVM_COMMAND); in bnx2_nvram_erase_page()
4258 val = BNX2_RD(bp, BNX2_NVM_COMMAND); in bnx2_nvram_read_dword()
4260 __be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ)); in bnx2_nvram_read_dword()
4307 if (BNX2_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE) in bnx2_nvram_write_dword()
4329 val = BNX2_RD(bp, BNX2_NVM_CFG1); in bnx2_init_nvram()
4755 val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS); in bnx2_wait_dma_complete()
4758 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL); in bnx2_wait_dma_complete()
4761 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL); in bnx2_wait_dma_complete()
4765 val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL); in bnx2_wait_dma_complete()
4796 val = BNX2_RD(bp, BNX2_MISC_ID); in bnx2_reset_chip()
4800 BNX2_RD(bp, BNX2_MISC_COMMAND); in bnx2_reset_chip()
4826 val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG); in bnx2_reset_chip()
4841 val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0); in bnx2_reset_chip()
4910 val = BNX2_RD(bp, BNX2_TDMA_CONFIG); in bnx2_init_chip()
4944 val = BNX2_RD(bp, BNX2_MQ_CONFIG); in bnx2_init_chip()
4963 val = BNX2_RD(bp, BNX2_TBDR_CONFIG); in bnx2_init_chip()
5090 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL); in bnx2_init_chip()
5098 BNX2_RD(bp, BNX2_MISC_ENABLE_SET_BITS); in bnx2_init_chip()
5102 bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND); in bnx2_init_chip()
5238 val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5); in bnx2_init_rx_ring()
5839 BNX2_RD(bp, BNX2_HC_COMMAND); in bnx2_run_loopback()
5865 BNX2_RD(bp, BNX2_HC_COMMAND); in bnx2_run_loopback()
6014 status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff; in bnx2_test_intr()
6018 BNX2_RD(bp, BNX2_HC_COMMAND); in bnx2_test_intr()
6021 if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) != in bnx2_test_intr()
6263 BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL); in bnx2_enable_msix()
6508 BNX2_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT); in bnx2_dump_ftq()
6517 while ((BNX2_RD(bp, BNX2_TBDC_COMMAND) & in bnx2_dump_ftq()
6521 cid = BNX2_RD(bp, BNX2_TBDC_CID); in bnx2_dump_ftq()
6522 bdidx = BNX2_RD(bp, BNX2_TBDC_BIDX); in bnx2_dump_ftq()
6523 valid = BNX2_RD(bp, BNX2_TBDC_CAM_OPCODE); in bnx2_dump_ftq()
6544 BNX2_RD(bp, BNX2_EMAC_TX_STATUS), in bnx2_dump_state()
6545 BNX2_RD(bp, BNX2_EMAC_RX_STATUS)); in bnx2_dump_state()
6547 BNX2_RD(bp, BNX2_RPM_MGMT_PKT_CTRL)); in bnx2_dump_state()
6549 BNX2_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS)); in bnx2_dump_state()
6552 BNX2_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE)); in bnx2_dump_state()
7084 *p++ = BNX2_RD(bp, offset); in bnx2_get_regs()
7708 bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG); in bnx2_set_phys_id()
7939 u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL); in bnx2_get_5709_media()
7979 reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS); in bnx2_get_pci_speed()
7985 clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS); in bnx2_get_pci_speed()
8150 bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID); in bnx2_init_board()
8209 reg = BNX2_RD(bp, PCI_COMMAND); in bnx2_init_board()
8373 !(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) { in bnx2_init_board()