273 static inline u32 rdl(struct pxa168_eth_private *pep, int offset)  in rdl()  function
293 		while ((rdl(pep, SDMA_CMD) & (SDMA_CMD_AR | SDMA_CMD_AT))  in abort_dma()
567 	val = rdl(pep, PORT_CONFIG);  in pxa168_eth_set_rx_mode()
589 	unsigned int mac_h = rdl(pep, MAC_ADDR_HIGH);  in pxa168_eth_get_mac_address()
590 	unsigned int mac_l = rdl(pep, MAC_ADDR_LOW);  in pxa168_eth_get_mac_address()
654 	val = rdl(pep, PORT_CONFIG);  in eth_port_start()
659 	val = rdl(pep, SDMA_CMD);  in eth_port_start()
676 	val = rdl(pep, SDMA_CMD);  in eth_port_reset()
685 	val = rdl(pep, PORT_CONFIG);  in eth_port_reset()
846 	icr = rdl(pep, INT_CAUSE);  in pxa168_eth_collect_events()
933 	u32 cfg, cfg_o = rdl(pep, PORT_CONFIG);  in pxa168_eth_adjust_link()
934 	u32 cfgext, cfgext_o = rdl(pep, PORT_CONFIG_EXT);  in pxa168_eth_adjust_link()
1291 	for (i = 0; rdl(pep, SMI) & SMI_BUSY; i++) {  in smi_wait_ready()
1312 	for (i = 0; !((val = rdl(pep, SMI)) & SMI_R_VALID); i++) {  in pxa168_smi_read()