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Lines Matching refs:pdma

48 	.pdma = {
96 .pdma = {
112 .pdma = {
160 .pdma = {
915 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); in mtk_rx_irq_disable()
916 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask); in mtk_rx_irq_disable()
926 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); in mtk_rx_irq_enable()
927 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask); in mtk_rx_irq_enable()
2421 reg_map->pdma.irq_status); in mtk_napi_rx()
2428 mtk_r32(eth, reg_map->pdma.irq_status), in mtk_napi_rx()
2429 mtk_r32(eth, reg_map->pdma.irq_mask)); in mtk_napi_rx()
2435 } while (mtk_r32(eth, reg_map->pdma.irq_status) & in mtk_napi_rx()
2548 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx); in mtk_tx_alloc()
2704 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr + in mtk_rx_alloc()
2720 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET); in mtk_rx_alloc()
2722 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); in mtk_rx_alloc()
2724 reg_map->pdma.rst_idx); in mtk_rx_alloc()
3048 reg = eth->soc->reg_map->pdma.glo_cfg; in mtk_dma_busy_wait()
3198 if (mtk_r32(eth, reg_map->pdma.irq_mask) & in mtk_handle_irq()
3200 if (mtk_r32(eth, reg_map->pdma.irq_status) & in mtk_handle_irq()
3255 reg_map->pdma.glo_cfg); in mtk_start_dma()
3259 reg_map->pdma.glo_cfg); in mtk_start_dma()
3479 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg); in mtk_stop()
3583 val = mtk_r32(eth, reg_map->pdma.delay_irq); in mtk_dim_rx()
3593 mtk_w32(eth, val, reg_map->pdma.delay_irq); in mtk_dim_rx()
3614 val = mtk_r32(eth, reg_map->pdma.delay_irq); in mtk_dim_tx()
3624 mtk_w32(eth, val, reg_map->pdma.delay_irq); in mtk_dim_tx()
3806 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) && in mtk_hw_check_dma_hang()
3807 !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & BIT(6)); in mtk_hw_check_dma_hang()
3945 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp); in mtk_hw_init()
3946 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4); in mtk_hw_init()