223 	int idx, jdx;  in sparx5_create_targets()  local
225 	for (idx = 0, jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) {  in sparx5_create_targets()
228 		if (idx == iomap->range) {  in sparx5_create_targets()
229 			range_id[idx] = jdx;  in sparx5_create_targets()
230 			idx++;  in sparx5_create_targets()
233 	for (idx = 0; idx < IO_RANGES; idx++) {  in sparx5_create_targets()
234 		iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM,  in sparx5_create_targets()
235 						   idx);  in sparx5_create_targets()
236 		if (!iores[idx]) {  in sparx5_create_targets()
240 		iomem[idx] = devm_ioremap(sparx5->dev,  in sparx5_create_targets()
241 					  iores[idx]->start,  in sparx5_create_targets()
242 					  resource_size(iores[idx]));  in sparx5_create_targets()
243 		if (!iomem[idx]) {  in sparx5_create_targets()
245 				iores[idx]->name);  in sparx5_create_targets()
248 		begin[idx] = iomem[idx] - sparx5_main_iomap[range_id[idx]].offset;  in sparx5_create_targets()
357 	u32 value, pending, jdx, idx;  in sparx5_init_ram()  local
361 		for (idx = 0; idx < ARRAY_SIZE(spx5_ram_cfg); idx++) {  in sparx5_init_ram()
362 			cfg = &spx5_ram_cfg[idx];  in sparx5_init_ram()
422 	u32 clk_div, clk_period, pol_upd_int, idx;  in sparx5_init_coreclock()  local
528 	for (idx = 0; idx < 3; idx++)  in sparx5_init_coreclock()
532 			 GCB_SIO_CLOCK(idx));  in sparx5_init_coreclock()
576 	int idx;  in sparx5_board_init()  local
588 	for (idx = 0; idx < SPX5_PORTS; idx++)  in sparx5_board_init()
589 		if (sparx5->ports[idx])  in sparx5_board_init()
590 			if (sparx5->ports[idx]->conf.sd_sgpio != ~0)  in sparx5_board_init()
591 				spx5_wr(sparx5->ports[idx]->conf.sd_sgpio,  in sparx5_board_init()
593 					GCB_HW_SGPIO_TO_SD_MAP_CFG(idx));  in sparx5_board_init()
600 	u32 idx;  in sparx5_start()  local
604 	for (idx = 0; idx < 3; idx++) {  in sparx5_start()
605 		spx5_wr(idx, sparx5, ANA_AC_OWN_UPSID(idx));  in sparx5_start()
606 		spx5_wr(idx, sparx5, ANA_CL_OWN_UPSID(idx));  in sparx5_start()
607 		spx5_wr(idx, sparx5, ANA_L2_OWN_UPSID(idx));  in sparx5_start()
608 		spx5_wr(idx, sparx5, REW_OWN_UPSID(idx));  in sparx5_start()
612 	for (idx = SPX5_PORTS; idx < SPX5_PORTS_ALL; idx++)  in sparx5_start()
616 			 QFWD_SWITCH_PORT_MODE(idx));  in sparx5_start()
628 	for (idx = SPX5_PORT_CPU_0; idx <= SPX5_PORT_CPU_1; idx++)  in sparx5_start()
631 			 sparx5, ANA_CL_FILTER_CTRL(idx));  in sparx5_start()
748 	int idx = 0, err = 0;  in mchp_sparx5_probe()  local
798 		config = &configs[idx];  in mchp_sparx5_probe()
836 		idx++;  in mchp_sparx5_probe()
873 	for (idx = 0; idx < sparx5->port_count; ++idx) {  in mchp_sparx5_probe()
874 		config = &configs[idx];  in mchp_sparx5_probe()