509 		regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));  in xlgmac_enable_tx()
512 		writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));  in xlgmac_enable_tx()
566 		regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));  in xlgmac_disable_tx()
569 		writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));  in xlgmac_disable_tx()
613 		regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR));  in xlgmac_enable_rx()
616 		writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));  in xlgmac_enable_rx()
669 		regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR));  in xlgmac_disable_rx()
672 		writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));  in xlgmac_disable_rx()
690 	       XLGMAC_DMA_REG(channel, DMA_CH_TDTR_LO));  in xlgmac_tx_start_xmit()
1072 	writel(ring->dma_desc_count - 1, XLGMAC_DMA_REG(channel, DMA_CH_TDRLR));  in xlgmac_tx_desc_init()
1077 	       XLGMAC_DMA_REG(channel, DMA_CH_TDLR_HI));  in xlgmac_tx_desc_init()
1079 	       XLGMAC_DMA_REG(channel, DMA_CH_TDLR_LO));  in xlgmac_tx_desc_init()
1156 	writel(ring->dma_desc_count - 1, XLGMAC_DMA_REG(channel, DMA_CH_RDRLR));  in xlgmac_rx_desc_init()
1161 	       XLGMAC_DMA_REG(channel, DMA_CH_RDLR_HI));  in xlgmac_rx_desc_init()
1163 	       XLGMAC_DMA_REG(channel, DMA_CH_RDLR_LO));  in xlgmac_rx_desc_init()
1169 	       XLGMAC_DMA_REG(channel, DMA_CH_RDTR_LO));  in xlgmac_rx_desc_init()
1311 		regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RIWT));  in xlgmac_config_rx_coalesce()
1315 		writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RIWT));  in xlgmac_config_rx_coalesce()
1369 		regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR));  in xlgmac_config_rx_buffer_size()
1373 		writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));  in xlgmac_config_rx_buffer_size()
1389 			regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));  in xlgmac_config_tso_mode()
1392 			writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));  in xlgmac_config_tso_mode()
1408 		regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_CR));  in xlgmac_config_sph_mode()
1411 		writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_CR));  in xlgmac_config_sph_mode()
1750 		regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));  in xlgmac_config_osp_mode()
1754 		writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));  in xlgmac_config_osp_mode()
1768 		regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_CR));  in xlgmac_config_pblx8()
1772 		writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_CR));  in xlgmac_config_pblx8()
1782 	regval = readl(XLGMAC_DMA_REG(pdata->channel_head, DMA_CH_TCR));  in xlgmac_get_tx_pbl_val()
1799 		regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));  in xlgmac_config_tx_pbl_val()
1803 		writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));  in xlgmac_config_tx_pbl_val()
1813 	regval = readl(XLGMAC_DMA_REG(pdata->channel_head, DMA_CH_RCR));  in xlgmac_get_rx_pbl_val()
1830 		regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR));  in xlgmac_config_rx_pbl_val()
1834 		writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));  in xlgmac_config_rx_pbl_val()
2455 		dma_ch_isr = readl(XLGMAC_DMA_REG(channel, DMA_CH_SR));  in xlgmac_enable_dma_interrupts()
2456 		writel(dma_ch_isr, XLGMAC_DMA_REG(channel, DMA_CH_SR));  in xlgmac_enable_dma_interrupts()
2507 		writel(dma_ch_isr, XLGMAC_DMA_REG(channel, DMA_CH_IER));  in xlgmac_enable_dma_interrupts()
2821 	dma_ch_ier = readl(XLGMAC_DMA_REG(channel, DMA_CH_IER));  in xlgmac_enable_int()
2874 	writel(dma_ch_ier, XLGMAC_DMA_REG(channel, DMA_CH_IER));  in xlgmac_enable_int()
2884 	dma_ch_ier = readl(XLGMAC_DMA_REG(channel, DMA_CH_IER));  in xlgmac_disable_int()
2938 	writel(dma_ch_ier, XLGMAC_DMA_REG(channel, DMA_CH_IER));  in xlgmac_disable_int()