Lines Matching refs:XLGMAC_MTL_REG
517 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_enable_tx()
521 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_enable_tx()
554 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_disable_tx()
557 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_disable_tx()
585 rx_status = readl(XLGMAC_MTL_REG(pdata, queue, MTL_Q_RQDR)); in xlgmac_prepare_rx_stop()
1196 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_disable_tx_flow_control()
1199 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_disable_tx_flow_control()
1228 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_enable_tx_flow_control()
1231 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_enable_tx_flow_control()
1333 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rx_fep_enable()
1336 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rx_fep_enable()
1346 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rx_fup_enable()
1349 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rx_fup_enable()
1464 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rx_threshold()
1467 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rx_threshold()
1486 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_TC_ETSCR)); in xlgmac_config_mtl_mode()
1489 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_TC_ETSCR)); in xlgmac_config_mtl_mode()
1491 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_TC_QWR)); in xlgmac_config_mtl_mode()
1494 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_TC_QWR)); in xlgmac_config_mtl_mode()
1522 regval = readl(XLGMAC_MTL_REG(pdata, queue, in xlgmac_config_queue_mapping()
1528 writel(regval, XLGMAC_MTL_REG(pdata, queue, in xlgmac_config_queue_mapping()
1536 regval = readl(XLGMAC_MTL_REG(pdata, queue, in xlgmac_config_queue_mapping()
1542 writel(regval, XLGMAC_MTL_REG(pdata, queue, in xlgmac_config_queue_mapping()
1641 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_config_tx_fifo_size()
1644 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_config_tx_fifo_size()
1663 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rx_fifo_size()
1666 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rx_fifo_size()
1680 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQFCR)); in xlgmac_config_flow_control_threshold()
1687 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQFCR)); in xlgmac_config_flow_control_threshold()
1698 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_config_tx_threshold()
1701 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_config_tx_threshold()
1714 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rsf_mode()
1717 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rsf_mode()
1730 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_config_tsf_mode()
1733 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_config_tsf_mode()
2519 mtl_q_isr = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_ISR)); in xlgmac_enable_mtl_interrupts()
2520 writel(mtl_q_isr, XLGMAC_MTL_REG(pdata, i, MTL_Q_ISR)); in xlgmac_enable_mtl_interrupts()
2523 writel(0, XLGMAC_MTL_REG(pdata, i, MTL_Q_IER)); in xlgmac_enable_mtl_interrupts()
2949 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_flush_tx_queues()
2952 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_flush_tx_queues()
2958 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_flush_tx_queues()