93 	struct hw_pmu_info *inf;  member
142 	struct hw_pmu_info inf;  member
734 	return readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));  in xgene_pmu_read_counter32()
759 	writel(val, pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));  in xgene_pmu_write_counter32()
778 	writel(val, pmu_dev->inf->csr + PMU_PMEVTYPER0 + (4 * idx));  in xgene_pmu_write_evttype()
784 	writel(val, pmu_dev->inf->csr + PMU_PMAMR0);  in xgene_pmu_write_agentmsk()
793 	writel(val, pmu_dev->inf->csr + PMU_PMAMR1);  in xgene_pmu_write_agent1msk()
804 	val = readl(pmu_dev->inf->csr + PMU_PMCNTENSET);  in xgene_pmu_enable_counter()
806 	writel(val, pmu_dev->inf->csr + PMU_PMCNTENSET);  in xgene_pmu_enable_counter()
814 	val = readl(pmu_dev->inf->csr + PMU_PMCNTENCLR);  in xgene_pmu_disable_counter()
816 	writel(val, pmu_dev->inf->csr + PMU_PMCNTENCLR);  in xgene_pmu_disable_counter()
824 	val = readl(pmu_dev->inf->csr + PMU_PMINTENSET);  in xgene_pmu_enable_counter_int()
826 	writel(val, pmu_dev->inf->csr + PMU_PMINTENSET);  in xgene_pmu_enable_counter_int()
834 	val = readl(pmu_dev->inf->csr + PMU_PMINTENCLR);  in xgene_pmu_disable_counter_int()
836 	writel(val, pmu_dev->inf->csr + PMU_PMINTENCLR);  in xgene_pmu_disable_counter_int()
843 	val = readl(pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_reset_counters()
845 	writel(val, pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_reset_counters()
852 	val = readl(pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_start_counters()
854 	writel(val, pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_start_counters()
861 	val = readl(pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_stop_counters()
863 	writel(val, pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_stop_counters()
952 	if (pmu_dev->inf->type == PMU_TYPE_IOB)  in xgene_perf_enable_event()
1137 	pmu->inf = &ctx->inf;  in xgene_pmu_dev_add()
1140 	switch (pmu->inf->type) {  in xgene_pmu_dev_add()
1142 		if (!(xgene_pmu->l3c_active_mask & pmu->inf->enable_mask))  in xgene_pmu_dev_add()
1160 		if (!(xgene_pmu->mcb_active_mask & pmu->inf->enable_mask))  in xgene_pmu_dev_add()
1168 		if (!(xgene_pmu->mc_active_mask & pmu->inf->enable_mask))  in xgene_pmu_dev_add()
1192 	void __iomem *csr = pmu_dev->inf->csr;  in _xgene_pmu_isr()
1460 	struct hw_pmu_info *inf;  in acpi_get_pmu_hw_inf()  local
1511 	inf = &ctx->inf;  in acpi_get_pmu_hw_inf()
1512 	inf->type = type;  in acpi_get_pmu_hw_inf()
1513 	inf->csr = dev_csr;  in acpi_get_pmu_hw_inf()
1514 	inf->enable_mask = 1 << enable_bit;  in acpi_get_pmu_hw_inf()
1574 	switch (ctx->inf.type) {  in acpi_pmu_dev_add()
1628 	struct hw_pmu_info *inf;  in fdt_get_pmu_hw_inf()  local
1658 	inf = &ctx->inf;  in fdt_get_pmu_hw_inf()
1659 	inf->type = type;  in fdt_get_pmu_hw_inf()
1660 	inf->csr = dev_csr;  in fdt_get_pmu_hw_inf()
1661 	inf->enable_mask = 1 << enable_bit;  in fdt_get_pmu_hw_inf()
1696 		switch (ctx->inf.type) {  in fdt_pmu_probe_pmu_dev()