Lines Matching defs:n
21 #define SUN6I_DPHY_GCTL_LANE_NUM(n) ((((n) - 1) & 3) << 4) argument
36 #define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n) (((n) & 0xff) << 24) argument
37 #define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n) (((n) & 0xff) << 16) argument
38 #define SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(n) ((n) & 0xff) argument
41 #define SUN6I_DPHY_TX_TIME1_CLK_POST(n) (((n) & 0xff) << 24) argument
42 #define SUN6I_DPHY_TX_TIME1_CLK_PRE(n) (((n) & 0xff) << 16) argument
43 #define SUN6I_DPHY_TX_TIME1_CLK_ZERO(n) (((n) & 0xff) << 8) argument
44 #define SUN6I_DPHY_TX_TIME1_CLK_PREPARE(n) ((n) & 0xff) argument
47 #define SUN6I_DPHY_TX_TIME2_CLK_TRAIL(n) ((n) & 0xff) argument
52 #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n) (((n) & 0xff) << 8) argument
53 #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n) ((n) & 0xff) argument
56 #define SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(n) (((n) & 0xff) << 24) argument
57 #define SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(n) (((n) & 0xff) << 16) argument
58 #define SUN6I_DPHY_RX_TIME0_LP_RX(n) (((n) & 0xff) << 8) argument
61 #define SUN6I_DPHY_RX_TIME1_RX_DLY(n) (((n) & 0xfff) << 20) argument
62 #define SUN6I_DPHY_RX_TIME1_LP_RX_ULPS_WP(n) ((n) & 0xfffff) argument
65 #define SUN6I_DPHY_RX_TIME2_HS_RX_ANA1(n) (((n) & 0xff) << 8) argument
66 #define SUN6I_DPHY_RX_TIME2_HS_RX_ANA0(n) ((n) & 0xff) argument
69 #define SUN6I_DPHY_RX_TIME3_LPRST_DLY(n) (((n) & 0xffff) << 16) argument
76 #define SUN6I_DPHY_ANA0_REG_DMPD(n) (((n) & 0xf) << 24) argument
77 #define SUN6I_DPHY_ANA0_REG_SRXDT(n) (((n) & 0xf) << 20) argument
78 #define SUN6I_DPHY_ANA0_REG_SRXCK(n) (((n) & 0xf) << 16) argument
80 #define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12) argument
81 #define SUN6I_DPHY_ANA0_REG_DEN(n) (((n) & 0xf) << 8) argument
82 #define SUN6I_DPHY_ANA0_REG_PLR(n) (((n) & 0xf) << 4) argument
83 #define SUN6I_DPHY_ANA0_REG_SFB(n) (((n) & 3) << 2) argument
89 #define SUN6I_DPHY_ANA1_REG_CSMPS(n) (((n) & 3) << 28) argument
90 #define SUN6I_DPHY_ANA1_REG_SVTT(n) (((n) & 0xf) << 24) argument
93 #define SUN6I_DPHY_ANA2_EN_P2S_CPU(n) (((n) & 0xf) << 24) argument
99 #define SUN6I_DPHY_ANA3_EN_VTTD(n) (((n) & 0xf) << 28) argument
110 #define SUN6I_DPHY_ANA4_REG_COMTEST(n) (((n) & 3) << 28) argument
111 #define SUN6I_DPHY_ANA4_REG_IB(n) (((n) & 3) << 25) argument
113 #define SUN6I_DPHY_ANA4_REG_DMPLVD(n) (((n) & 0xf) << 20) argument
114 #define SUN6I_DPHY_ANA4_REG_VTT_SET(n) (((n) & 0x7) << 17) argument
115 #define SUN6I_DPHY_ANA4_REG_CKDV(n) (((n) & 0x1f) << 12) argument
116 #define SUN6I_DPHY_ANA4_REG_TMSC(n) (((n) & 3) << 10) argument
117 #define SUN6I_DPHY_ANA4_REG_TMSD(n) (((n) & 3) << 8) argument
118 #define SUN6I_DPHY_ANA4_REG_TXDNSC(n) (((n) & 3) << 6) argument
119 #define SUN6I_DPHY_ANA4_REG_TXDNSD(n) (((n) & 3) << 4) argument
120 #define SUN6I_DPHY_ANA4_REG_TXPUSC(n) (((n) & 3) << 2) argument
121 #define SUN6I_DPHY_ANA4_REG_TXPUSD(n) ((n) & 3) argument
134 #define SUN50I_DPHY_PLL_REG0_P(n) (((n) & 0xf) << 16) argument
135 #define SUN50I_DPHY_PLL_REG0_N(n) (((n) & 0xff) << 8) argument
138 #define SUN50I_DPHY_PLL_REG0_M0(n) (((n) & 3) << 4) argument
139 #define SUN50I_DPHY_PLL_REG0_M1(n) ((n) & 0xf) argument
142 #define SUN50I_DPHY_PLL_REG1_UNLOCK_MDSEL(n) (((n) & 3) << 14) argument
145 #define SUN50I_DPHY_PLL_REG1_VSETA(n) (((n) & 0x7) << 9) argument
146 #define SUN50I_DPHY_PLL_REG1_VSETD(n) (((n) & 0x7) << 6) argument
148 #define SUN50I_DPHY_PLL_REG1_ICP_SEL(n) (((n) & 3) << 3) argument
149 #define SUN50I_DPHY_PLL_REG1_ATEST_SEL(n) (((n) & 3) << 1) argument
156 #define SUN50I_DPHY_PLL_REG2_SS_FRAC(n) (((n) & 0x1ff) << 20) argument
157 #define SUN50I_DPHY_PLL_REG2_SS_INT(n) (((n) & 0xff) << 12) argument
158 #define SUN50I_DPHY_PLL_REG2_FRAC(n) ((n) & 0xfff) argument
169 #define SUN50I_COMBO_PHY_REG2_REG_VREF1P6(n) (((n) & 0x7) << 4) argument
170 #define SUN50I_COMBO_PHY_REG2_REG_VREF0P8(n) ((n) & 0x7) argument
173 #define SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(n) ((n) & 0xff) argument
265 unsigned int div, n; in sun50i_a100_mipi_dphy_tx_power_on() local