Lines Matching refs:regs
23 mtk_phy_set_bits(hdmi_phy->regs + HDMI_ANA_CTL, REG_ANA_HDMI20_FIFO_EN); in mtk_hdmi_ana_fifo_en()
29 void __iomem *regs = hdmi_phy->regs; in mtk_phy_tmds_clk_ratio() local
37 mtk_phy_update_field(regs + HDMI20_CLK_CFG, REG_TXC_DIV, 3); in mtk_phy_tmds_clk_ratio()
39 mtk_phy_clear_bits(regs + HDMI20_CLK_CFG, REG_TXC_DIV); in mtk_phy_tmds_clk_ratio()
45 void __iomem *regs = hdmi_phy->regs; in mtk_hdmi_pll_sel_src() local
47 mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_REF_XTAL_SEL); in mtk_hdmi_pll_sel_src()
48 mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_REF_RESPLL_SEL); in mtk_hdmi_pll_sel_src()
51 mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITXPLL_REF_CK_SEL); in mtk_hdmi_pll_sel_src()
57 void __iomem *regs = hdmi_phy->regs; in mtk_hdmi_pll_perf() local
59 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_BP2); in mtk_hdmi_pll_perf()
60 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BC); in mtk_hdmi_pll_perf()
61 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_IC, 0x1); in mtk_hdmi_pll_perf()
62 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BR, 0x2); in mtk_hdmi_pll_perf()
63 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_IR, 0x2); in mtk_hdmi_pll_perf()
64 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BP); in mtk_hdmi_pll_perf()
65 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_IBAND_FIX_EN); in mtk_hdmi_pll_perf()
66 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT14); in mtk_hdmi_pll_perf()
67 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_HIKVCO); in mtk_hdmi_pll_perf()
68 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_HREN, 0x1); in mtk_hdmi_pll_perf()
69 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_LVR_SEL, 0x1); in mtk_hdmi_pll_perf()
70 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT12_11); in mtk_hdmi_pll_perf()
71 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_TCL_EN); in mtk_hdmi_pll_perf()
90 void __iomem *regs = hdmi_phy->regs; in mtk_hdmi_pll_set_hw() local
96 mtk_phy_update_field(regs + HDMI_1_CFG_10, RG_HDMITX21_BIAS_PE_BG_VREF_SEL, 0x2); in mtk_hdmi_pll_set_hw()
97 mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_VREF_SEL); in mtk_hdmi_pll_set_hw()
98 mtk_phy_update_field(regs + HDMI_1_CFG_9, RG_HDMITX21_SLDO_VREF_SEL, 0x2); in mtk_hdmi_pll_set_hw()
99 mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BIAS_PE_VREF_SELB); in mtk_hdmi_pll_set_hw()
100 mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDOLPF_EN); in mtk_hdmi_pll_set_hw()
101 mtk_phy_update_field(regs + HDMI_1_CFG_6, RG_HDMITX21_INTR_CAL, 0x11); in mtk_hdmi_pll_set_hw()
102 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD); in mtk_hdmi_pll_set_hw()
107 mtk_phy_update_field(regs + HDMI_1_CFG_6, RG_HDMITX21_TX_POSDIV, txposdiv_value); in mtk_hdmi_pll_set_hw()
108 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_TX_POSDIV_EN); in mtk_hdmi_pll_set_hw()
109 mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_EN); in mtk_hdmi_pll_set_hw()
133 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_POSDIV_DIV3_CTRL, div3_ctrl_value); in mtk_hdmi_pll_set_hw()
134 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_POSDIV, posdiv_vallue); in mtk_hdmi_pll_set_hw()
154 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_DIV_CTRL, div_ctrl_value); in mtk_hdmi_pll_set_hw()
157 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT14); in mtk_hdmi_pll_set_hw()
177 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT3_2, reserve_3_2_value); in mtk_hdmi_pll_set_hw()
180 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT1_0, 0x2); in mtk_hdmi_pll_set_hw()
185 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_PREDIV, prediv_value); in mtk_hdmi_pll_set_hw()
190 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT13, reserve13_value); in mtk_hdmi_pll_set_hw()
193 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_FBKDIV_HIGH, fbkdiv_high); in mtk_hdmi_pll_set_hw()
194 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_3, RG_HDMITXPLL_FBKDIV_LOW, fbkdiv_low); in mtk_hdmi_pll_set_hw()
197 mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_PIXEL_CLOCK_SEL); in mtk_hdmi_pll_set_hw()
200 mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_PIXEL_CLOCK); in mtk_hdmi_pll_set_hw()
202 mtk_phy_set_bits(regs + HDMI_CTL_3, REG_HDMITX_PIXEL_CLOCK); in mtk_hdmi_pll_set_hw()
203 mtk_phy_update_field(regs + HDMI_CTL_3, REG_HDMITXPLL_DIV, digital_div - 1); in mtk_hdmi_pll_set_hw()
303 void __iomem *regs = hdmi_phy->regs; in mtk_hdmi_pll_drv_setting() local
342 mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D0, data_channel_bias); in mtk_hdmi_pll_drv_setting()
343 mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D1, data_channel_bias); in mtk_hdmi_pll_drv_setting()
344 mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D2, data_channel_bias); in mtk_hdmi_pll_drv_setting()
345 mtk_phy_update_field(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_IBIAS_CLK, clk_channel_bias); in mtk_hdmi_pll_drv_setting()
348 mtk_phy_update_field(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_IMP_EN, impedance_en); in mtk_hdmi_pll_drv_setting()
349 mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D0_EN1, impedance); in mtk_hdmi_pll_drv_setting()
350 mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D1_EN1, impedance); in mtk_hdmi_pll_drv_setting()
351 mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D2_EN1, impedance); in mtk_hdmi_pll_drv_setting()
352 mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_CLK_EN1, impedance); in mtk_hdmi_pll_drv_setting()
360 void __iomem *regs = hdmi_phy->regs; in mtk_hdmi_pll_prepare() local
362 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_TX_POSDIV_EN); in mtk_hdmi_pll_prepare()
364 mtk_phy_set_bits(regs + HDMI_1_CFG_0, RG_HDMITX21_SER_EN); in mtk_hdmi_pll_prepare()
365 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_D0_DRV_OP_EN); in mtk_hdmi_pll_prepare()
366 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_D1_DRV_OP_EN); in mtk_hdmi_pll_prepare()
367 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_D2_DRV_OP_EN); in mtk_hdmi_pll_prepare()
368 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_CK_DRV_OP_EN); in mtk_hdmi_pll_prepare()
370 mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_D0_EN); in mtk_hdmi_pll_prepare()
371 mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_D1_EN); in mtk_hdmi_pll_prepare()
372 mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_D2_EN); in mtk_hdmi_pll_prepare()
373 mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_CK_EN); in mtk_hdmi_pll_prepare()
377 mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BG_PWD); in mtk_hdmi_pll_prepare()
378 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_BIAS_EN); in mtk_hdmi_pll_prepare()
379 mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_CKLDO_EN); in mtk_hdmi_pll_prepare()
380 mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDO_EN); in mtk_hdmi_pll_prepare()
382 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_PWR_ON); in mtk_hdmi_pll_prepare()
384 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_ISO_EN); in mtk_hdmi_pll_prepare()
386 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD); in mtk_hdmi_pll_prepare()
394 void __iomem *regs = hdmi_phy->regs; in mtk_hdmi_pll_unprepare() local
396 mtk_phy_set_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BG_PWD); in mtk_hdmi_pll_unprepare()
397 mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_BIAS_EN); in mtk_hdmi_pll_unprepare()
398 mtk_phy_clear_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_CKLDO_EN); in mtk_hdmi_pll_unprepare()
399 mtk_phy_clear_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDO_EN); in mtk_hdmi_pll_unprepare()
401 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD); in mtk_hdmi_pll_unprepare()
403 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_ISO_EN); in mtk_hdmi_pll_unprepare()
405 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_PWR_ON); in mtk_hdmi_pll_unprepare()
446 void __iomem *regs = hdmi_phy->regs; in vtx_signal_en() local
449 mtk_phy_set_bits(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_EN); in vtx_signal_en()
451 mtk_phy_clear_bits(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_EN); in vtx_signal_en()