Lines Matching refs:BIT1
192 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
350 #define MASK_PARITY BIT1
1781 status = *(p + 1) & (BIT1 + BIT0); in rx_async()
1783 if (status & BIT1) in rx_async()
1790 if (status & BIT1) in rx_async()
1968 if (status & BIT1) { in dcd_change()
3774 wr_reg32(info, RDCSR, BIT1); in rdma_reset()
3787 wr_reg32(info, TDCSR, BIT1); in tdma_reset()
3851 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ in rx_stop()
3876 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ in rx_start()
3909 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1)); in rx_start()
3919 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); in tx_start()
3962 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */ in tx_stop()
4308 val |= BIT1 + BIT0; in sync_mode()
4418 if (status & BIT1) in get_gtsignals()
4460 val |= BIT1; in msc_set_vcr()
4576 status &= ~BIT1; in rx_get_frame()
4587 } else if (status & BIT1) { in rx_get_frame()
4631 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK; in rx_get_frame()
4874 (unsigned short)(rd_reg16(info, TCR) | BIT1)); in irq_test()