Lines Matching refs:PFB
391 cfg1 = NV_RD32(par->PFB, 0x00000204); in nv4UpdateArbitrationSettings()
630 cfg1 = NV_RD32(par->PFB, 0x0204); in nv10UpdateArbitrationSettings()
634 sim_data.memory_type = (NV_RD32(par->PFB, 0x0200) & 0x01) ? 1 : 0; in nv10UpdateArbitrationSettings()
933 state->config = NV_RD32(par->PFB, 0x00000200); in NVCalcStateExt()
961 NV_WR32(par->PFB, 0x0200, state->config); in NVLoadStateExt()
965 NV_WR32(par->PFB, 0x0240 + (i * 0x10), 0); in NVLoadStateExt()
966 NV_WR32(par->PFB, 0x0244 + (i * 0x10), in NVLoadStateExt()
979 NV_WR32(par->PFB, 0x0600 + (i * 0x10), 0); in NVLoadStateExt()
980 NV_WR32(par->PFB, 0x0604 + (i * 0x10), in NVLoadStateExt()
1205 NV_RD32(&par->PFB[(0x0240 / 4) + i], in NVLoadStateExt()
1251 NV_WR32(par->PFB, 0x033C, in NVLoadStateExt()
1252 NV_RD32(par->PFB, 0x33C) & in NVLoadStateExt()
1267 NV_RD32(par->PFB, 0x020C)); in NVLoadStateExt()
1271 NV_RD32(par->PFB, 0x020C)); in NVLoadStateExt()
1363 NV_RD32(par->PFB, 0x0240 +i*4)); in NVLoadStateExt()
1365 NV_RD32(par->PFB, 0x0240 +i*4)); in NVLoadStateExt()
1376 NV_RD32(par->PFB, in NVLoadStateExt()
1380 NV_RD32(par->PFB, in NVLoadStateExt()
1387 NV_RD32(par->PFB, in NVLoadStateExt()
1397 NV_RD32(par->PFB, in NVLoadStateExt()
1406 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1408 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1410 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1412 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1426 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1428 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1431 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1433 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1436 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1438 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1449 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1451 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1454 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1457 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1654 state->config = NV_RD32(par->PFB, 0x0200); in NVUnloadStateExt()