1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 31 32 enum smu_event_type { 33 SMU_EVENT_RESET_COMPLETE = 0, 34 }; 35 36 struct amd_vce_state { 37 /* vce clocks */ 38 u32 evclk; 39 u32 ecclk; 40 /* gpu clocks */ 41 u32 sclk; 42 u32 mclk; 43 u8 clk_idx; 44 u8 pstate; 45 }; 46 47 48 enum amd_dpm_forced_level { 49 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 50 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 51 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 52 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 53 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 54 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 55 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 56 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 57 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 58 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 59 }; 60 61 enum amd_pm_state_type { 62 /* not used for dpm */ 63 POWER_STATE_TYPE_DEFAULT, 64 POWER_STATE_TYPE_POWERSAVE, 65 /* user selectable states */ 66 POWER_STATE_TYPE_BATTERY, 67 POWER_STATE_TYPE_BALANCED, 68 POWER_STATE_TYPE_PERFORMANCE, 69 /* internal states */ 70 POWER_STATE_TYPE_INTERNAL_UVD, 71 POWER_STATE_TYPE_INTERNAL_UVD_SD, 72 POWER_STATE_TYPE_INTERNAL_UVD_HD, 73 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 74 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 75 POWER_STATE_TYPE_INTERNAL_BOOT, 76 POWER_STATE_TYPE_INTERNAL_THERMAL, 77 POWER_STATE_TYPE_INTERNAL_ACPI, 78 POWER_STATE_TYPE_INTERNAL_ULV, 79 POWER_STATE_TYPE_INTERNAL_3DPERF, 80 }; 81 82 #define AMD_MAX_VCE_LEVELS 6 83 84 enum amd_vce_level { 85 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 86 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 87 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 88 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 89 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 90 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 91 }; 92 93 enum amd_fan_ctrl_mode { 94 AMD_FAN_CTRL_NONE = 0, 95 AMD_FAN_CTRL_MANUAL = 1, 96 AMD_FAN_CTRL_AUTO = 2, 97 }; 98 99 enum pp_clock_type { 100 PP_SCLK, 101 PP_MCLK, 102 PP_PCIE, 103 PP_SOCCLK, 104 PP_FCLK, 105 PP_DCEFCLK, 106 PP_VCLK, 107 PP_VCLK1, 108 PP_DCLK, 109 PP_DCLK1, 110 OD_SCLK, 111 OD_MCLK, 112 OD_VDDC_CURVE, 113 OD_RANGE, 114 OD_VDDGFX_OFFSET, 115 OD_CCLK, 116 }; 117 118 enum amd_pp_sensors { 119 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 120 AMDGPU_PP_SENSOR_CPU_CLK, 121 AMDGPU_PP_SENSOR_VDDNB, 122 AMDGPU_PP_SENSOR_VDDGFX, 123 AMDGPU_PP_SENSOR_UVD_VCLK, 124 AMDGPU_PP_SENSOR_UVD_DCLK, 125 AMDGPU_PP_SENSOR_VCE_ECCLK, 126 AMDGPU_PP_SENSOR_GPU_LOAD, 127 AMDGPU_PP_SENSOR_MEM_LOAD, 128 AMDGPU_PP_SENSOR_GFX_MCLK, 129 AMDGPU_PP_SENSOR_GPU_TEMP, 130 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 131 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 132 AMDGPU_PP_SENSOR_MEM_TEMP, 133 AMDGPU_PP_SENSOR_VCE_POWER, 134 AMDGPU_PP_SENSOR_UVD_POWER, 135 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 136 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 137 AMDGPU_PP_SENSOR_SS_APU_SHARE, 138 AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 139 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 140 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 141 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 142 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 143 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 144 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 145 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 146 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 147 }; 148 149 enum amd_pp_task { 150 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 151 AMD_PP_TASK_ENABLE_USER_STATE, 152 AMD_PP_TASK_READJUST_POWER_STATE, 153 AMD_PP_TASK_COMPLETE_INIT, 154 AMD_PP_TASK_MAX 155 }; 156 157 enum PP_SMC_POWER_PROFILE { 158 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 159 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 160 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 161 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 162 PP_SMC_POWER_PROFILE_VR = 0x4, 163 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 164 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 165 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7, 166 PP_SMC_POWER_PROFILE_CAPPED = 0x8, 167 PP_SMC_POWER_PROFILE_UNCAPPED = 0x9, 168 PP_SMC_POWER_PROFILE_COUNT, 169 }; 170 171 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; 172 173 174 175 enum { 176 PP_GROUP_UNKNOWN = 0, 177 PP_GROUP_GFX = 1, 178 PP_GROUP_SYS, 179 PP_GROUP_MAX 180 }; 181 182 enum PP_OD_DPM_TABLE_COMMAND { 183 PP_OD_EDIT_SCLK_VDDC_TABLE, 184 PP_OD_EDIT_MCLK_VDDC_TABLE, 185 PP_OD_EDIT_CCLK_VDDC_TABLE, 186 PP_OD_EDIT_VDDC_CURVE, 187 PP_OD_RESTORE_DEFAULT_TABLE, 188 PP_OD_COMMIT_DPM_TABLE, 189 PP_OD_EDIT_VDDGFX_OFFSET 190 }; 191 192 struct pp_states_info { 193 uint32_t nums; 194 uint32_t states[16]; 195 }; 196 197 enum PP_HWMON_TEMP { 198 PP_TEMP_EDGE = 0, 199 PP_TEMP_JUNCTION, 200 PP_TEMP_MEM, 201 PP_TEMP_MAX 202 }; 203 204 enum pp_mp1_state { 205 PP_MP1_STATE_NONE, 206 PP_MP1_STATE_SHUTDOWN, 207 PP_MP1_STATE_UNLOAD, 208 PP_MP1_STATE_RESET, 209 }; 210 211 enum pp_df_cstate { 212 DF_CSTATE_DISALLOW = 0, 213 DF_CSTATE_ALLOW, 214 }; 215 216 /** 217 * DOC: amdgpu_pp_power 218 * 219 * APU power is managed to system-level requirements through the PPT 220 * (package power tracking) feature. PPT is intended to limit power to the 221 * requirements of the power source and could be dynamically updated to 222 * maximize APU performance within the system power budget. 223 * 224 * Two types of power measurement can be requested, where supported, with 225 * :c:type:`enum pp_power_type <pp_power_type>`. 226 */ 227 228 /** 229 * enum pp_power_limit_level - Used to query the power limits 230 * 231 * @PP_PWR_LIMIT_MIN: Minimum Power Limit 232 * @PP_PWR_LIMIT_CURRENT: Current Power Limit 233 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit 234 * @PP_PWR_LIMIT_MAX: Maximum Power Limit 235 */ 236 enum pp_power_limit_level 237 { 238 PP_PWR_LIMIT_MIN = -1, 239 PP_PWR_LIMIT_CURRENT, 240 PP_PWR_LIMIT_DEFAULT, 241 PP_PWR_LIMIT_MAX, 242 }; 243 244 /** 245 * enum pp_power_type - Used to specify the type of the requested power 246 * 247 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant 248 * moving average of APU power (default ~5000 ms). 249 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, 250 * where supported. 251 */ 252 enum pp_power_type 253 { 254 PP_PWR_TYPE_SUSTAINED, 255 PP_PWR_TYPE_FAST, 256 }; 257 258 #define PP_GROUP_MASK 0xF0000000 259 #define PP_GROUP_SHIFT 28 260 261 #define PP_BLOCK_MASK 0x0FFFFF00 262 #define PP_BLOCK_SHIFT 8 263 264 #define PP_BLOCK_GFX_CG 0x01 265 #define PP_BLOCK_GFX_MG 0x02 266 #define PP_BLOCK_GFX_3D 0x04 267 #define PP_BLOCK_GFX_RLC 0x08 268 #define PP_BLOCK_GFX_CP 0x10 269 #define PP_BLOCK_SYS_BIF 0x01 270 #define PP_BLOCK_SYS_MC 0x02 271 #define PP_BLOCK_SYS_ROM 0x04 272 #define PP_BLOCK_SYS_DRM 0x08 273 #define PP_BLOCK_SYS_HDP 0x10 274 #define PP_BLOCK_SYS_SDMA 0x20 275 276 #define PP_STATE_MASK 0x0000000F 277 #define PP_STATE_SHIFT 0 278 #define PP_STATE_SUPPORT_MASK 0x000000F0 279 #define PP_STATE_SUPPORT_SHIFT 0 280 281 #define PP_STATE_CG 0x01 282 #define PP_STATE_LS 0x02 283 #define PP_STATE_DS 0x04 284 #define PP_STATE_SD 0x08 285 #define PP_STATE_SUPPORT_CG 0x10 286 #define PP_STATE_SUPPORT_LS 0x20 287 #define PP_STATE_SUPPORT_DS 0x40 288 #define PP_STATE_SUPPORT_SD 0x80 289 290 #define PP_CG_MSG_ID(group, block, support, state) \ 291 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 292 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 293 294 #define XGMI_MODE_PSTATE_D3 0 295 #define XGMI_MODE_PSTATE_D0 1 296 297 #define NUM_HBM_INSTANCES 4 298 299 struct seq_file; 300 enum amd_pp_clock_type; 301 struct amd_pp_simple_clock_info; 302 struct amd_pp_display_configuration; 303 struct amd_pp_clock_info; 304 struct pp_display_clock_request; 305 struct pp_clock_levels_with_voltage; 306 struct pp_clock_levels_with_latency; 307 struct amd_pp_clocks; 308 struct pp_smu_wm_range_sets; 309 struct pp_smu_nv_clock_table; 310 struct dpm_clocks; 311 312 struct amd_pm_funcs { 313 /* export for dpm on ci and si */ 314 int (*pre_set_power_state)(void *handle); 315 int (*set_power_state)(void *handle); 316 void (*post_set_power_state)(void *handle); 317 void (*display_configuration_changed)(void *handle); 318 void (*print_power_state)(void *handle, void *ps); 319 bool (*vblank_too_short)(void *handle); 320 void (*enable_bapm)(void *handle, bool enable); 321 int (*check_state_equal)(void *handle, 322 void *cps, 323 void *rps, 324 bool *equal); 325 /* export for sysfs */ 326 int (*set_fan_control_mode)(void *handle, u32 mode); 327 int (*get_fan_control_mode)(void *handle, u32 *fan_mode); 328 int (*set_fan_speed_pwm)(void *handle, u32 speed); 329 int (*get_fan_speed_pwm)(void *handle, u32 *speed); 330 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 331 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 332 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset); 333 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 334 int (*get_sclk_od)(void *handle); 335 int (*set_sclk_od)(void *handle, uint32_t value); 336 int (*get_mclk_od)(void *handle); 337 int (*set_mclk_od)(void *handle, uint32_t value); 338 int (*read_sensor)(void *handle, int idx, void *value, int *size); 339 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit); 340 int (*set_apu_thermal_limit)(void *handle, uint32_t limit); 341 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 342 enum amd_pm_state_type (*get_current_power_state)(void *handle); 343 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 344 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 345 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 346 int (*get_pp_table)(void *handle, char **table); 347 int (*set_pp_table)(void *handle, const char *buf, size_t size); 348 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 349 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 350 /* export to amdgpu */ 351 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 352 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 353 enum amd_pm_state_type *user_state); 354 int (*load_firmware)(void *handle); 355 int (*wait_for_fw_loading_complete)(void *handle); 356 int (*set_powergating_by_smu)(void *handle, 357 uint32_t block_type, bool gate); 358 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 359 int (*set_power_limit)(void *handle, uint32_t n); 360 int (*get_power_limit)(void *handle, uint32_t *limit, 361 enum pp_power_limit_level pp_limit_level, 362 enum pp_power_type power_type); 363 int (*get_power_profile_mode)(void *handle, char *buf); 364 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 365 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 366 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 367 long *input, uint32_t size); 368 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 369 int (*smu_i2c_bus_access)(void *handle, bool acquire); 370 int (*gfx_state_change_set)(void *handle, uint32_t state); 371 /* export to DC */ 372 u32 (*get_sclk)(void *handle, bool low); 373 u32 (*get_mclk)(void *handle, bool low); 374 int (*display_configuration_change)(void *handle, 375 const struct amd_pp_display_configuration *input); 376 int (*get_display_power_level)(void *handle, 377 struct amd_pp_simple_clock_info *output); 378 int (*get_current_clocks)(void *handle, 379 struct amd_pp_clock_info *clocks); 380 int (*get_clock_by_type)(void *handle, 381 enum amd_pp_clock_type type, 382 struct amd_pp_clocks *clocks); 383 int (*get_clock_by_type_with_latency)(void *handle, 384 enum amd_pp_clock_type type, 385 struct pp_clock_levels_with_latency *clocks); 386 int (*get_clock_by_type_with_voltage)(void *handle, 387 enum amd_pp_clock_type type, 388 struct pp_clock_levels_with_voltage *clocks); 389 int (*set_watermarks_for_clocks_ranges)(void *handle, 390 void *clock_ranges); 391 int (*display_clock_voltage_request)(void *handle, 392 struct pp_display_clock_request *clock); 393 int (*get_display_mode_validation_clocks)(void *handle, 394 struct amd_pp_simple_clock_info *clocks); 395 int (*notify_smu_enable_pwe)(void *handle); 396 int (*enable_mgpu_fan_boost)(void *handle); 397 int (*set_active_display_count)(void *handle, uint32_t count); 398 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 399 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 400 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 401 int (*get_asic_baco_capability)(void *handle, bool *cap); 402 int (*get_asic_baco_state)(void *handle, int *state); 403 int (*set_asic_baco_state)(void *handle, int state); 404 int (*get_ppfeature_status)(void *handle, char *buf); 405 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 406 int (*asic_reset_mode_2)(void *handle); 407 int (*asic_reset_enable_gfx_features)(void *handle); 408 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 409 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 410 ssize_t (*get_gpu_metrics)(void *handle, void **table); 411 int (*set_watermarks_for_clock_ranges)(void *handle, 412 struct pp_smu_wm_range_sets *ranges); 413 int (*display_disable_memory_clock_switch)(void *handle, 414 bool disable_memory_clock_switch); 415 int (*get_max_sustainable_clocks_by_dc)(void *handle, 416 struct pp_smu_nv_clock_table *max_clocks); 417 int (*get_uclk_dpm_states)(void *handle, 418 unsigned int *clock_values_in_khz, 419 unsigned int *num_states); 420 int (*get_dpm_clock_table)(void *handle, 421 struct dpm_clocks *clock_table); 422 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); 423 void (*pm_compute_clocks)(void *handle); 424 }; 425 426 struct metrics_table_header { 427 uint16_t structure_size; 428 uint8_t format_revision; 429 uint8_t content_revision; 430 }; 431 432 /* 433 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 434 * Use gpu_metrics_v1_1 or later instead. 435 */ 436 struct gpu_metrics_v1_0 { 437 struct metrics_table_header common_header; 438 439 /* Driver attached timestamp (in ns) */ 440 uint64_t system_clock_counter; 441 442 /* Temperature */ 443 uint16_t temperature_edge; 444 uint16_t temperature_hotspot; 445 uint16_t temperature_mem; 446 uint16_t temperature_vrgfx; 447 uint16_t temperature_vrsoc; 448 uint16_t temperature_vrmem; 449 450 /* Utilization */ 451 uint16_t average_gfx_activity; 452 uint16_t average_umc_activity; // memory controller 453 uint16_t average_mm_activity; // UVD or VCN 454 455 /* Power/Energy */ 456 uint16_t average_socket_power; 457 uint32_t energy_accumulator; 458 459 /* Average clocks */ 460 uint16_t average_gfxclk_frequency; 461 uint16_t average_socclk_frequency; 462 uint16_t average_uclk_frequency; 463 uint16_t average_vclk0_frequency; 464 uint16_t average_dclk0_frequency; 465 uint16_t average_vclk1_frequency; 466 uint16_t average_dclk1_frequency; 467 468 /* Current clocks */ 469 uint16_t current_gfxclk; 470 uint16_t current_socclk; 471 uint16_t current_uclk; 472 uint16_t current_vclk0; 473 uint16_t current_dclk0; 474 uint16_t current_vclk1; 475 uint16_t current_dclk1; 476 477 /* Throttle status */ 478 uint32_t throttle_status; 479 480 /* Fans */ 481 uint16_t current_fan_speed; 482 483 /* Link width/speed */ 484 uint8_t pcie_link_width; 485 uint8_t pcie_link_speed; // in 0.1 GT/s 486 }; 487 488 struct gpu_metrics_v1_1 { 489 struct metrics_table_header common_header; 490 491 /* Temperature */ 492 uint16_t temperature_edge; 493 uint16_t temperature_hotspot; 494 uint16_t temperature_mem; 495 uint16_t temperature_vrgfx; 496 uint16_t temperature_vrsoc; 497 uint16_t temperature_vrmem; 498 499 /* Utilization */ 500 uint16_t average_gfx_activity; 501 uint16_t average_umc_activity; // memory controller 502 uint16_t average_mm_activity; // UVD or VCN 503 504 /* Power/Energy */ 505 uint16_t average_socket_power; 506 uint64_t energy_accumulator; 507 508 /* Driver attached timestamp (in ns) */ 509 uint64_t system_clock_counter; 510 511 /* Average clocks */ 512 uint16_t average_gfxclk_frequency; 513 uint16_t average_socclk_frequency; 514 uint16_t average_uclk_frequency; 515 uint16_t average_vclk0_frequency; 516 uint16_t average_dclk0_frequency; 517 uint16_t average_vclk1_frequency; 518 uint16_t average_dclk1_frequency; 519 520 /* Current clocks */ 521 uint16_t current_gfxclk; 522 uint16_t current_socclk; 523 uint16_t current_uclk; 524 uint16_t current_vclk0; 525 uint16_t current_dclk0; 526 uint16_t current_vclk1; 527 uint16_t current_dclk1; 528 529 /* Throttle status */ 530 uint32_t throttle_status; 531 532 /* Fans */ 533 uint16_t current_fan_speed; 534 535 /* Link width/speed */ 536 uint16_t pcie_link_width; 537 uint16_t pcie_link_speed; // in 0.1 GT/s 538 539 uint16_t padding; 540 541 uint32_t gfx_activity_acc; 542 uint32_t mem_activity_acc; 543 544 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 545 }; 546 547 struct gpu_metrics_v1_2 { 548 struct metrics_table_header common_header; 549 550 /* Temperature */ 551 uint16_t temperature_edge; 552 uint16_t temperature_hotspot; 553 uint16_t temperature_mem; 554 uint16_t temperature_vrgfx; 555 uint16_t temperature_vrsoc; 556 uint16_t temperature_vrmem; 557 558 /* Utilization */ 559 uint16_t average_gfx_activity; 560 uint16_t average_umc_activity; // memory controller 561 uint16_t average_mm_activity; // UVD or VCN 562 563 /* Power/Energy */ 564 uint16_t average_socket_power; 565 uint64_t energy_accumulator; 566 567 /* Driver attached timestamp (in ns) */ 568 uint64_t system_clock_counter; 569 570 /* Average clocks */ 571 uint16_t average_gfxclk_frequency; 572 uint16_t average_socclk_frequency; 573 uint16_t average_uclk_frequency; 574 uint16_t average_vclk0_frequency; 575 uint16_t average_dclk0_frequency; 576 uint16_t average_vclk1_frequency; 577 uint16_t average_dclk1_frequency; 578 579 /* Current clocks */ 580 uint16_t current_gfxclk; 581 uint16_t current_socclk; 582 uint16_t current_uclk; 583 uint16_t current_vclk0; 584 uint16_t current_dclk0; 585 uint16_t current_vclk1; 586 uint16_t current_dclk1; 587 588 /* Throttle status (ASIC dependent) */ 589 uint32_t throttle_status; 590 591 /* Fans */ 592 uint16_t current_fan_speed; 593 594 /* Link width/speed */ 595 uint16_t pcie_link_width; 596 uint16_t pcie_link_speed; // in 0.1 GT/s 597 598 uint16_t padding; 599 600 uint32_t gfx_activity_acc; 601 uint32_t mem_activity_acc; 602 603 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 604 605 /* PMFW attached timestamp (10ns resolution) */ 606 uint64_t firmware_timestamp; 607 }; 608 609 struct gpu_metrics_v1_3 { 610 struct metrics_table_header common_header; 611 612 /* Temperature */ 613 uint16_t temperature_edge; 614 uint16_t temperature_hotspot; 615 uint16_t temperature_mem; 616 uint16_t temperature_vrgfx; 617 uint16_t temperature_vrsoc; 618 uint16_t temperature_vrmem; 619 620 /* Utilization */ 621 uint16_t average_gfx_activity; 622 uint16_t average_umc_activity; // memory controller 623 uint16_t average_mm_activity; // UVD or VCN 624 625 /* Power/Energy */ 626 uint16_t average_socket_power; 627 uint64_t energy_accumulator; 628 629 /* Driver attached timestamp (in ns) */ 630 uint64_t system_clock_counter; 631 632 /* Average clocks */ 633 uint16_t average_gfxclk_frequency; 634 uint16_t average_socclk_frequency; 635 uint16_t average_uclk_frequency; 636 uint16_t average_vclk0_frequency; 637 uint16_t average_dclk0_frequency; 638 uint16_t average_vclk1_frequency; 639 uint16_t average_dclk1_frequency; 640 641 /* Current clocks */ 642 uint16_t current_gfxclk; 643 uint16_t current_socclk; 644 uint16_t current_uclk; 645 uint16_t current_vclk0; 646 uint16_t current_dclk0; 647 uint16_t current_vclk1; 648 uint16_t current_dclk1; 649 650 /* Throttle status */ 651 uint32_t throttle_status; 652 653 /* Fans */ 654 uint16_t current_fan_speed; 655 656 /* Link width/speed */ 657 uint16_t pcie_link_width; 658 uint16_t pcie_link_speed; // in 0.1 GT/s 659 660 uint16_t padding; 661 662 uint32_t gfx_activity_acc; 663 uint32_t mem_activity_acc; 664 665 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 666 667 /* PMFW attached timestamp (10ns resolution) */ 668 uint64_t firmware_timestamp; 669 670 /* Voltage (mV) */ 671 uint16_t voltage_soc; 672 uint16_t voltage_gfx; 673 uint16_t voltage_mem; 674 675 uint16_t padding1; 676 677 /* Throttle status (ASIC independent) */ 678 uint64_t indep_throttle_status; 679 }; 680 681 /* 682 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 683 * Use gpu_metrics_v2_1 or later instead. 684 */ 685 struct gpu_metrics_v2_0 { 686 struct metrics_table_header common_header; 687 688 /* Driver attached timestamp (in ns) */ 689 uint64_t system_clock_counter; 690 691 /* Temperature */ 692 uint16_t temperature_gfx; // gfx temperature on APUs 693 uint16_t temperature_soc; // soc temperature on APUs 694 uint16_t temperature_core[8]; // CPU core temperature on APUs 695 uint16_t temperature_l3[2]; 696 697 /* Utilization */ 698 uint16_t average_gfx_activity; 699 uint16_t average_mm_activity; // UVD or VCN 700 701 /* Power/Energy */ 702 uint16_t average_socket_power; // dGPU + APU power on A + A platform 703 uint16_t average_cpu_power; 704 uint16_t average_soc_power; 705 uint16_t average_gfx_power; 706 uint16_t average_core_power[8]; // CPU core power on APUs 707 708 /* Average clocks */ 709 uint16_t average_gfxclk_frequency; 710 uint16_t average_socclk_frequency; 711 uint16_t average_uclk_frequency; 712 uint16_t average_fclk_frequency; 713 uint16_t average_vclk_frequency; 714 uint16_t average_dclk_frequency; 715 716 /* Current clocks */ 717 uint16_t current_gfxclk; 718 uint16_t current_socclk; 719 uint16_t current_uclk; 720 uint16_t current_fclk; 721 uint16_t current_vclk; 722 uint16_t current_dclk; 723 uint16_t current_coreclk[8]; // CPU core clocks 724 uint16_t current_l3clk[2]; 725 726 /* Throttle status */ 727 uint32_t throttle_status; 728 729 /* Fans */ 730 uint16_t fan_pwm; 731 732 uint16_t padding; 733 }; 734 735 struct gpu_metrics_v2_1 { 736 struct metrics_table_header common_header; 737 738 /* Temperature */ 739 uint16_t temperature_gfx; // gfx temperature on APUs 740 uint16_t temperature_soc; // soc temperature on APUs 741 uint16_t temperature_core[8]; // CPU core temperature on APUs 742 uint16_t temperature_l3[2]; 743 744 /* Utilization */ 745 uint16_t average_gfx_activity; 746 uint16_t average_mm_activity; // UVD or VCN 747 748 /* Driver attached timestamp (in ns) */ 749 uint64_t system_clock_counter; 750 751 /* Power/Energy */ 752 uint16_t average_socket_power; // dGPU + APU power on A + A platform 753 uint16_t average_cpu_power; 754 uint16_t average_soc_power; 755 uint16_t average_gfx_power; 756 uint16_t average_core_power[8]; // CPU core power on APUs 757 758 /* Average clocks */ 759 uint16_t average_gfxclk_frequency; 760 uint16_t average_socclk_frequency; 761 uint16_t average_uclk_frequency; 762 uint16_t average_fclk_frequency; 763 uint16_t average_vclk_frequency; 764 uint16_t average_dclk_frequency; 765 766 /* Current clocks */ 767 uint16_t current_gfxclk; 768 uint16_t current_socclk; 769 uint16_t current_uclk; 770 uint16_t current_fclk; 771 uint16_t current_vclk; 772 uint16_t current_dclk; 773 uint16_t current_coreclk[8]; // CPU core clocks 774 uint16_t current_l3clk[2]; 775 776 /* Throttle status */ 777 uint32_t throttle_status; 778 779 /* Fans */ 780 uint16_t fan_pwm; 781 782 uint16_t padding[3]; 783 }; 784 785 struct gpu_metrics_v2_2 { 786 struct metrics_table_header common_header; 787 788 /* Temperature */ 789 uint16_t temperature_gfx; // gfx temperature on APUs 790 uint16_t temperature_soc; // soc temperature on APUs 791 uint16_t temperature_core[8]; // CPU core temperature on APUs 792 uint16_t temperature_l3[2]; 793 794 /* Utilization */ 795 uint16_t average_gfx_activity; 796 uint16_t average_mm_activity; // UVD or VCN 797 798 /* Driver attached timestamp (in ns) */ 799 uint64_t system_clock_counter; 800 801 /* Power/Energy */ 802 uint16_t average_socket_power; // dGPU + APU power on A + A platform 803 uint16_t average_cpu_power; 804 uint16_t average_soc_power; 805 uint16_t average_gfx_power; 806 uint16_t average_core_power[8]; // CPU core power on APUs 807 808 /* Average clocks */ 809 uint16_t average_gfxclk_frequency; 810 uint16_t average_socclk_frequency; 811 uint16_t average_uclk_frequency; 812 uint16_t average_fclk_frequency; 813 uint16_t average_vclk_frequency; 814 uint16_t average_dclk_frequency; 815 816 /* Current clocks */ 817 uint16_t current_gfxclk; 818 uint16_t current_socclk; 819 uint16_t current_uclk; 820 uint16_t current_fclk; 821 uint16_t current_vclk; 822 uint16_t current_dclk; 823 uint16_t current_coreclk[8]; // CPU core clocks 824 uint16_t current_l3clk[2]; 825 826 /* Throttle status (ASIC dependent) */ 827 uint32_t throttle_status; 828 829 /* Fans */ 830 uint16_t fan_pwm; 831 832 uint16_t padding[3]; 833 834 /* Throttle status (ASIC independent) */ 835 uint64_t indep_throttle_status; 836 }; 837 838 struct gpu_metrics_v2_3 { 839 struct metrics_table_header common_header; 840 841 /* Temperature */ 842 uint16_t temperature_gfx; // gfx temperature on APUs 843 uint16_t temperature_soc; // soc temperature on APUs 844 uint16_t temperature_core[8]; // CPU core temperature on APUs 845 uint16_t temperature_l3[2]; 846 847 /* Utilization */ 848 uint16_t average_gfx_activity; 849 uint16_t average_mm_activity; // UVD or VCN 850 851 /* Driver attached timestamp (in ns) */ 852 uint64_t system_clock_counter; 853 854 /* Power/Energy */ 855 uint16_t average_socket_power; // dGPU + APU power on A + A platform 856 uint16_t average_cpu_power; 857 uint16_t average_soc_power; 858 uint16_t average_gfx_power; 859 uint16_t average_core_power[8]; // CPU core power on APUs 860 861 /* Average clocks */ 862 uint16_t average_gfxclk_frequency; 863 uint16_t average_socclk_frequency; 864 uint16_t average_uclk_frequency; 865 uint16_t average_fclk_frequency; 866 uint16_t average_vclk_frequency; 867 uint16_t average_dclk_frequency; 868 869 /* Current clocks */ 870 uint16_t current_gfxclk; 871 uint16_t current_socclk; 872 uint16_t current_uclk; 873 uint16_t current_fclk; 874 uint16_t current_vclk; 875 uint16_t current_dclk; 876 uint16_t current_coreclk[8]; // CPU core clocks 877 uint16_t current_l3clk[2]; 878 879 /* Throttle status (ASIC dependent) */ 880 uint32_t throttle_status; 881 882 /* Fans */ 883 uint16_t fan_pwm; 884 885 uint16_t padding[3]; 886 887 /* Throttle status (ASIC independent) */ 888 uint64_t indep_throttle_status; 889 890 /* Average Temperature */ 891 uint16_t average_temperature_gfx; // average gfx temperature on APUs 892 uint16_t average_temperature_soc; // average soc temperature on APUs 893 uint16_t average_temperature_core[8]; // average CPU core temperature on APUs 894 uint16_t average_temperature_l3[2]; 895 }; 896 897 struct gpu_metrics_v2_4 { 898 struct metrics_table_header common_header; 899 900 /* Temperature (unit: centi-Celsius) */ 901 uint16_t temperature_gfx; 902 uint16_t temperature_soc; 903 uint16_t temperature_core[8]; 904 uint16_t temperature_l3[2]; 905 906 /* Utilization (unit: centi) */ 907 uint16_t average_gfx_activity; 908 uint16_t average_mm_activity; 909 910 /* Driver attached timestamp (in ns) */ 911 uint64_t system_clock_counter; 912 913 /* Power/Energy (unit: mW) */ 914 uint16_t average_socket_power; 915 uint16_t average_cpu_power; 916 uint16_t average_soc_power; 917 uint16_t average_gfx_power; 918 uint16_t average_core_power[8]; 919 920 /* Average clocks (unit: MHz) */ 921 uint16_t average_gfxclk_frequency; 922 uint16_t average_socclk_frequency; 923 uint16_t average_uclk_frequency; 924 uint16_t average_fclk_frequency; 925 uint16_t average_vclk_frequency; 926 uint16_t average_dclk_frequency; 927 928 /* Current clocks (unit: MHz) */ 929 uint16_t current_gfxclk; 930 uint16_t current_socclk; 931 uint16_t current_uclk; 932 uint16_t current_fclk; 933 uint16_t current_vclk; 934 uint16_t current_dclk; 935 uint16_t current_coreclk[8]; 936 uint16_t current_l3clk[2]; 937 938 /* Throttle status (ASIC dependent) */ 939 uint32_t throttle_status; 940 941 /* Fans */ 942 uint16_t fan_pwm; 943 944 uint16_t padding[3]; 945 946 /* Throttle status (ASIC independent) */ 947 uint64_t indep_throttle_status; 948 949 /* Average Temperature (unit: centi-Celsius) */ 950 uint16_t average_temperature_gfx; 951 uint16_t average_temperature_soc; 952 uint16_t average_temperature_core[8]; 953 uint16_t average_temperature_l3[2]; 954 955 /* Power/Voltage (unit: mV) */ 956 uint16_t average_cpu_voltage; 957 uint16_t average_soc_voltage; 958 uint16_t average_gfx_voltage; 959 960 /* Power/Current (unit: mA) */ 961 uint16_t average_cpu_current; 962 uint16_t average_soc_current; 963 uint16_t average_gfx_current; 964 }; 965 #endif 966