1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_IORT if ACPI 9 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 10 select ACPI_MCFG if (ACPI && PCI) 11 select ACPI_SPCR_TABLE if ACPI 12 select ACPI_PPTT if ACPI 13 select ARCH_HAS_DEBUG_WX 14 select ARCH_BINFMT_ELF_EXTRA_PHDRS 15 select ARCH_BINFMT_ELF_STATE 16 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE 17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 18 select ARCH_ENABLE_MEMORY_HOTPLUG 19 select ARCH_ENABLE_MEMORY_HOTREMOVE 20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 22 select ARCH_HAS_CACHE_LINE_SIZE 23 select ARCH_HAS_CURRENT_STACK_POINTER 24 select ARCH_HAS_DEBUG_VIRTUAL 25 select ARCH_HAS_DEBUG_VM_PGTABLE 26 select ARCH_HAS_DMA_PREP_COHERENT 27 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 28 select ARCH_HAS_FAST_MULTIPLIER 29 select ARCH_HAS_FORTIFY_SOURCE 30 select ARCH_HAS_GCOV_PROFILE_ALL 31 select ARCH_HAS_GIGANTIC_PAGE 32 select ARCH_HAS_IOREMAP_PHYS_HOOKS 33 select ARCH_HAS_KCOV 34 select ARCH_HAS_KEEPINITRD 35 select ARCH_HAS_MEMBARRIER_SYNC_CORE 36 select ARCH_HAS_MEM_ENCRYPT 37 select ARCH_HAS_MEM_RELINQUISH 38 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 39 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 40 select ARCH_HAS_PTE_DEVMAP 41 select ARCH_HAS_PTE_SPECIAL 42 select ARCH_HAS_SETUP_DMA_OPS 43 select ARCH_HAS_SET_DIRECT_MAP 44 select ARCH_HAS_SET_MEMORY 45 select ARCH_STACKWALK 46 select ARCH_HAS_STRICT_KERNEL_RWX 47 select ARCH_HAS_STRICT_MODULE_RWX 48 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 49 select ARCH_HAS_SYNC_DMA_FOR_CPU 50 select ARCH_HAS_SYSCALL_WRAPPER 51 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT 52 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 53 select ARCH_HAS_ZONE_DMA_SET if EXPERT 54 select ARCH_HAVE_ELF_PROT 55 select ARCH_HAVE_NMI_SAFE_CMPXCHG 56 select ARCH_HAVE_TRACE_MMIO_ACCESS 57 select ARCH_INLINE_READ_LOCK if !PREEMPTION 58 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 59 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 60 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 61 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 62 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 63 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 64 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 65 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 66 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 67 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 68 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 69 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 70 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 71 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 72 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 73 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 74 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 75 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 76 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 77 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 78 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 79 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 80 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 81 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 82 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 83 select ARCH_KEEP_MEMBLOCK 84 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 85 select ARCH_USE_CMPXCHG_LOCKREF 86 select ARCH_USE_GNU_PROPERTY 87 select ARCH_USE_MEMTEST 88 select ARCH_USE_QUEUED_RWLOCKS 89 select ARCH_USE_QUEUED_SPINLOCKS 90 select ARCH_USE_SYM_ANNOTATIONS 91 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 92 select ARCH_SUPPORTS_HUGETLBFS 93 select ARCH_SUPPORTS_MEMORY_FAILURE 94 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 95 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 96 select ARCH_SUPPORTS_LTO_CLANG_THIN 97 select ARCH_SUPPORTS_CFI_CLANG 98 select ARCH_SUPPORTS_ATOMIC_RMW 99 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 100 select ARCH_SUPPORTS_NUMA_BALANCING 101 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 102 select ARCH_SUPPORTS_PER_VMA_LOCK 103 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 104 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 105 select ARCH_WANT_DEFAULT_BPF_JIT 106 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 107 select ARCH_WANT_FRAME_POINTERS 108 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 109 select ARCH_WANT_LD_ORPHAN_WARN 110 select ARCH_WANTS_NO_INSTR 111 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 112 select ARCH_HAS_UBSAN_SANITIZE_ALL 113 select ARM_AMBA 114 select ARM_ARCH_TIMER 115 select ARM_GIC 116 select AUDIT_ARCH_COMPAT_GENERIC 117 select ARM_GIC_V2M if PCI 118 select ARM_GIC_V3 119 select ARM_GIC_V3_ITS if PCI 120 select ARM_PSCI_FW 121 select BUILDTIME_TABLE_SORT 122 select CLONE_BACKWARDS 123 select COMMON_CLK 124 select CPU_PM if (SUSPEND || CPU_IDLE) 125 select CRC32 126 select DCACHE_WORD_ACCESS 127 select DYNAMIC_FTRACE if FUNCTION_TRACER 128 select DMA_BOUNCE_UNALIGNED_KMALLOC 129 select DMA_DIRECT_REMAP 130 select EDAC_SUPPORT 131 select FRAME_POINTER 132 select FUNCTION_ALIGNMENT_4B 133 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 134 select GENERIC_ALLOCATOR 135 select GENERIC_ARCH_TOPOLOGY 136 select GENERIC_CLOCKEVENTS_BROADCAST 137 select GENERIC_CPU_AUTOPROBE 138 select GENERIC_CPU_VULNERABILITIES 139 select GENERIC_EARLY_IOREMAP 140 select GENERIC_IDLE_POLL_SETUP 141 select GENERIC_IOREMAP 142 select GENERIC_IRQ_IPI 143 select GENERIC_IRQ_PROBE 144 select GENERIC_IRQ_SHOW 145 select GENERIC_IRQ_SHOW_LEVEL 146 select GENERIC_LIB_DEVMEM_IS_ALLOWED 147 select GENERIC_PCI_IOMAP 148 select GENERIC_PTDUMP 149 select GENERIC_SCHED_CLOCK 150 select GENERIC_SMP_IDLE_THREAD 151 select GENERIC_TIME_VSYSCALL 152 select GENERIC_GETTIMEOFDAY 153 select GENERIC_VDSO_TIME_NS 154 select HARDIRQS_SW_RESEND 155 select HAS_IOPORT 156 select HAVE_MOVE_PMD 157 select HAVE_MOVE_PUD 158 select HAVE_PCI 159 select HAVE_ACPI_APEI if (ACPI && EFI) 160 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 161 select HAVE_ARCH_AUDITSYSCALL 162 select HAVE_ARCH_BITREVERSE 163 select HAVE_ARCH_COMPILER_H 164 select HAVE_ARCH_HUGE_VMALLOC 165 select HAVE_ARCH_HUGE_VMAP 166 select HAVE_ARCH_JUMP_LABEL 167 select HAVE_ARCH_JUMP_LABEL_RELATIVE 168 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 169 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 170 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN 171 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE) 172 # Some instrumentation may be unsound, hence EXPERT 173 select HAVE_ARCH_KCSAN if EXPERT 174 select HAVE_ARCH_KFENCE 175 select HAVE_ARCH_KGDB 176 select HAVE_ARCH_MMAP_RND_BITS 177 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 178 select HAVE_ARCH_PREL32_RELOCATIONS 179 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 180 select HAVE_ARCH_SECCOMP_FILTER 181 select HAVE_ARCH_STACKLEAK 182 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 183 select HAVE_ARCH_TRACEHOOK 184 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 185 select HAVE_ARCH_VMAP_STACK 186 select HAVE_ARM_SMCCC 187 select HAVE_ASM_MODVERSIONS 188 select HAVE_EBPF_JIT 189 select HAVE_C_RECORDMCOUNT 190 select HAVE_CMPXCHG_DOUBLE 191 select HAVE_CMPXCHG_LOCAL 192 select HAVE_CONTEXT_TRACKING_USER 193 select HAVE_DEBUG_KMEMLEAK 194 select HAVE_DMA_CONTIGUOUS 195 select HAVE_DYNAMIC_FTRACE 196 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 197 if $(cc-option,-fpatchable-function-entry=2) 198 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 199 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 200 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 201 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \ 202 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 203 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 204 if DYNAMIC_FTRACE_WITH_ARGS 205 select HAVE_SAMPLE_FTRACE_DIRECT 206 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 207 select HAVE_EFFICIENT_UNALIGNED_ACCESS 208 select HAVE_FAST_GUP 209 select HAVE_FTRACE_MCOUNT_RECORD 210 select HAVE_FUNCTION_TRACER 211 select HAVE_FUNCTION_ERROR_INJECTION 212 select HAVE_FUNCTION_GRAPH_RETVAL if HAVE_FUNCTION_GRAPH_TRACER 213 select HAVE_FUNCTION_GRAPH_TRACER 214 select HAVE_GCC_PLUGINS 215 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 216 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 217 select HAVE_HW_BREAKPOINT if PERF_EVENTS 218 select HAVE_IOREMAP_PROT 219 select HAVE_IRQ_TIME_ACCOUNTING 220 select HAVE_KVM 221 select HAVE_MOD_ARCH_SPECIFIC 222 select HAVE_NMI 223 select HAVE_PERF_EVENTS 224 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 225 select HAVE_PERF_REGS 226 select HAVE_PERF_USER_STACK_DUMP 227 select HAVE_PREEMPT_DYNAMIC_KEY 228 select HAVE_REGS_AND_STACK_ACCESS_API 229 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 230 select HAVE_FUNCTION_ARG_ACCESS_API 231 select MMU_GATHER_RCU_TABLE_FREE 232 select HAVE_RSEQ 233 select HAVE_STACKPROTECTOR 234 select HAVE_SYSCALL_TRACEPOINTS 235 select HAVE_KPROBES 236 select HAVE_KRETPROBES 237 select HAVE_GENERIC_VDSO 238 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 239 select IRQ_DOMAIN 240 select IRQ_FORCED_THREADING 241 select KASAN_VMALLOC if KASAN 242 select LOCK_MM_AND_FIND_VMA 243 select MODULES_USE_ELF_RELA 244 select NEED_DMA_MAP_STATE 245 select NEED_SG_DMA_LENGTH 246 select OF 247 select OF_EARLY_FLATTREE 248 select PCI_DOMAINS_GENERIC if PCI 249 select PCI_ECAM if (ACPI && PCI) 250 select PCI_SYSCALL if PCI 251 select POWER_RESET 252 select POWER_SUPPLY 253 select SPARSE_IRQ 254 select SWIOTLB 255 select SYSCTL_EXCEPTION_TRACE 256 select THREAD_INFO_IN_TASK 257 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 258 select TRACE_IRQFLAGS_SUPPORT 259 select TRACE_IRQFLAGS_NMI_SUPPORT 260 select HAVE_SOFTIRQ_ON_OWN_STACK 261 select USER_STACKTRACE_SUPPORT 262 help 263 ARM 64-bit (AArch64) Linux support. 264 265config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 266 def_bool CC_IS_CLANG 267 # https://github.com/ClangBuiltLinux/linux/issues/1507 268 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 269 select HAVE_DYNAMIC_FTRACE_WITH_ARGS 270 271config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 272 def_bool CC_IS_GCC 273 depends on $(cc-option,-fpatchable-function-entry=2) 274 select HAVE_DYNAMIC_FTRACE_WITH_ARGS 275 276config 64BIT 277 def_bool y 278 279config MMU 280 def_bool y 281 282config ARM64_PAGE_SHIFT 283 int 284 default 16 if ARM64_64K_PAGES 285 default 14 if ARM64_16K_PAGES 286 default 12 287 288config ARM64_CONT_PTE_SHIFT 289 int 290 default 5 if ARM64_64K_PAGES 291 default 7 if ARM64_16K_PAGES 292 default 4 293 294config ARM64_CONT_PMD_SHIFT 295 int 296 default 5 if ARM64_64K_PAGES 297 default 5 if ARM64_16K_PAGES 298 default 4 299 300config ARCH_MMAP_RND_BITS_MIN 301 default 14 if ARM64_64K_PAGES 302 default 16 if ARM64_16K_PAGES 303 default 18 304 305# max bits determined by the following formula: 306# VA_BITS - PAGE_SHIFT - 3 307config ARCH_MMAP_RND_BITS_MAX 308 default 19 if ARM64_VA_BITS=36 309 default 24 if ARM64_VA_BITS=39 310 default 27 if ARM64_VA_BITS=42 311 default 30 if ARM64_VA_BITS=47 312 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 313 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 314 default 33 if ARM64_VA_BITS=48 315 default 14 if ARM64_64K_PAGES 316 default 16 if ARM64_16K_PAGES 317 default 18 318 319config ARCH_MMAP_RND_COMPAT_BITS_MIN 320 default 7 if ARM64_64K_PAGES 321 default 9 if ARM64_16K_PAGES 322 default 11 323 324config ARCH_MMAP_RND_COMPAT_BITS_MAX 325 default 16 326 327config NO_IOPORT_MAP 328 def_bool y if !PCI 329 330config STACKTRACE_SUPPORT 331 def_bool y 332 333config ILLEGAL_POINTER_VALUE 334 hex 335 default 0xdead000000000000 336 337config LOCKDEP_SUPPORT 338 def_bool y 339 340config GENERIC_BUG 341 def_bool y 342 depends on BUG 343 344config GENERIC_BUG_RELATIVE_POINTERS 345 def_bool y 346 depends on GENERIC_BUG 347 348config GENERIC_HWEIGHT 349 def_bool y 350 351config GENERIC_CSUM 352 def_bool y 353 354config GENERIC_CALIBRATE_DELAY 355 def_bool y 356 357config SMP 358 def_bool y 359 360config KERNEL_MODE_NEON 361 def_bool y 362 363config FIX_EARLYCON_MEM 364 def_bool y 365 366config PGTABLE_LEVELS 367 int 368 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 369 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 370 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 371 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 372 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 373 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 374 375config ARCH_SUPPORTS_UPROBES 376 def_bool y 377 378config ARCH_PROC_KCORE_TEXT 379 def_bool y 380 381config BROKEN_GAS_INST 382 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 383 384config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 385 bool 386 # Clang's __builtin_return_adddress() strips the PAC since 12.0.0 387 # https://reviews.llvm.org/D75044 388 default y if CC_IS_CLANG && (CLANG_VERSION >= 120000) 389 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 390 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 391 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 392 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 393 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 394 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 395 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 396 default n 397 398config KASAN_SHADOW_OFFSET 399 hex 400 depends on KASAN_GENERIC || KASAN_SW_TAGS 401 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS 402 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS 403 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 404 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 405 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 406 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS 407 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS 408 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 409 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 410 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 411 default 0xffffffffffffffff 412 413config UNWIND_TABLES 414 bool 415 416source "arch/arm64/Kconfig.platforms" 417 418menu "Kernel Features" 419 420menu "ARM errata workarounds via the alternatives framework" 421 422config AMPERE_ERRATUM_AC03_CPU_38 423 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 424 default y 425 help 426 This option adds an alternative code sequence to work around Ampere 427 erratum AC03_CPU_38 on AmpereOne. 428 429 The affected design reports FEAT_HAFDBS as not implemented in 430 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 431 as required by the architecture. The unadvertised HAFDBS 432 implementation suffers from an additional erratum where hardware 433 A/D updates can occur after a PTE has been marked invalid. 434 435 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 436 which avoids enabling unadvertised hardware Access Flag management 437 at stage-2. 438 439 If unsure, say Y. 440 441config ARM64_WORKAROUND_CLEAN_CACHE 442 bool 443 444config ARM64_ERRATUM_826319 445 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 446 default y 447 select ARM64_WORKAROUND_CLEAN_CACHE 448 help 449 This option adds an alternative code sequence to work around ARM 450 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 451 AXI master interface and an L2 cache. 452 453 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 454 and is unable to accept a certain write via this interface, it will 455 not progress on read data presented on the read data channel and the 456 system can deadlock. 457 458 The workaround promotes data cache clean instructions to 459 data cache clean-and-invalidate. 460 Please note that this does not necessarily enable the workaround, 461 as it depends on the alternative framework, which will only patch 462 the kernel if an affected CPU is detected. 463 464 If unsure, say Y. 465 466config ARM64_ERRATUM_827319 467 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 468 default y 469 select ARM64_WORKAROUND_CLEAN_CACHE 470 help 471 This option adds an alternative code sequence to work around ARM 472 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 473 master interface and an L2 cache. 474 475 Under certain conditions this erratum can cause a clean line eviction 476 to occur at the same time as another transaction to the same address 477 on the AMBA 5 CHI interface, which can cause data corruption if the 478 interconnect reorders the two transactions. 479 480 The workaround promotes data cache clean instructions to 481 data cache clean-and-invalidate. 482 Please note that this does not necessarily enable the workaround, 483 as it depends on the alternative framework, which will only patch 484 the kernel if an affected CPU is detected. 485 486 If unsure, say Y. 487 488config ARM64_ERRATUM_824069 489 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 490 default y 491 select ARM64_WORKAROUND_CLEAN_CACHE 492 help 493 This option adds an alternative code sequence to work around ARM 494 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 495 to a coherent interconnect. 496 497 If a Cortex-A53 processor is executing a store or prefetch for 498 write instruction at the same time as a processor in another 499 cluster is executing a cache maintenance operation to the same 500 address, then this erratum might cause a clean cache line to be 501 incorrectly marked as dirty. 502 503 The workaround promotes data cache clean instructions to 504 data cache clean-and-invalidate. 505 Please note that this option does not necessarily enable the 506 workaround, as it depends on the alternative framework, which will 507 only patch the kernel if an affected CPU is detected. 508 509 If unsure, say Y. 510 511config ARM64_ERRATUM_819472 512 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 513 default y 514 select ARM64_WORKAROUND_CLEAN_CACHE 515 help 516 This option adds an alternative code sequence to work around ARM 517 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 518 present when it is connected to a coherent interconnect. 519 520 If the processor is executing a load and store exclusive sequence at 521 the same time as a processor in another cluster is executing a cache 522 maintenance operation to the same address, then this erratum might 523 cause data corruption. 524 525 The workaround promotes data cache clean instructions to 526 data cache clean-and-invalidate. 527 Please note that this does not necessarily enable the workaround, 528 as it depends on the alternative framework, which will only patch 529 the kernel if an affected CPU is detected. 530 531 If unsure, say Y. 532 533config ARM64_ERRATUM_832075 534 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 535 default y 536 help 537 This option adds an alternative code sequence to work around ARM 538 erratum 832075 on Cortex-A57 parts up to r1p2. 539 540 Affected Cortex-A57 parts might deadlock when exclusive load/store 541 instructions to Write-Back memory are mixed with Device loads. 542 543 The workaround is to promote device loads to use Load-Acquire 544 semantics. 545 Please note that this does not necessarily enable the workaround, 546 as it depends on the alternative framework, which will only patch 547 the kernel if an affected CPU is detected. 548 549 If unsure, say Y. 550 551config ARM64_ERRATUM_834220 552 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 553 depends on KVM 554 default y 555 help 556 This option adds an alternative code sequence to work around ARM 557 erratum 834220 on Cortex-A57 parts up to r1p2. 558 559 Affected Cortex-A57 parts might report a Stage 2 translation 560 fault as the result of a Stage 1 fault for load crossing a 561 page boundary when there is a permission or device memory 562 alignment fault at Stage 1 and a translation fault at Stage 2. 563 564 The workaround is to verify that the Stage 1 translation 565 doesn't generate a fault before handling the Stage 2 fault. 566 Please note that this does not necessarily enable the workaround, 567 as it depends on the alternative framework, which will only patch 568 the kernel if an affected CPU is detected. 569 570 If unsure, say Y. 571 572config ARM64_ERRATUM_1742098 573 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 574 depends on COMPAT 575 default y 576 help 577 This option removes the AES hwcap for aarch32 user-space to 578 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 579 580 Affected parts may corrupt the AES state if an interrupt is 581 taken between a pair of AES instructions. These instructions 582 are only present if the cryptography extensions are present. 583 All software should have a fallback implementation for CPUs 584 that don't implement the cryptography extensions. 585 586 If unsure, say Y. 587 588config ARM64_ERRATUM_845719 589 bool "Cortex-A53: 845719: a load might read incorrect data" 590 depends on COMPAT 591 default y 592 help 593 This option adds an alternative code sequence to work around ARM 594 erratum 845719 on Cortex-A53 parts up to r0p4. 595 596 When running a compat (AArch32) userspace on an affected Cortex-A53 597 part, a load at EL0 from a virtual address that matches the bottom 32 598 bits of the virtual address used by a recent load at (AArch64) EL1 599 might return incorrect data. 600 601 The workaround is to write the contextidr_el1 register on exception 602 return to a 32-bit task. 603 Please note that this does not necessarily enable the workaround, 604 as it depends on the alternative framework, which will only patch 605 the kernel if an affected CPU is detected. 606 607 If unsure, say Y. 608 609config ARM64_ERRATUM_843419 610 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 611 default y 612 help 613 This option links the kernel with '--fix-cortex-a53-843419' and 614 enables PLT support to replace certain ADRP instructions, which can 615 cause subsequent memory accesses to use an incorrect address on 616 Cortex-A53 parts up to r0p4. 617 618 If unsure, say Y. 619 620config ARM64_LD_HAS_FIX_ERRATUM_843419 621 def_bool $(ld-option,--fix-cortex-a53-843419) 622 623config ARM64_ERRATUM_1024718 624 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 625 default y 626 help 627 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 628 629 Affected Cortex-A55 cores (all revisions) could cause incorrect 630 update of the hardware dirty bit when the DBM/AP bits are updated 631 without a break-before-make. The workaround is to disable the usage 632 of hardware DBM locally on the affected cores. CPUs not affected by 633 this erratum will continue to use the feature. 634 635 If unsure, say Y. 636 637config ARM64_ERRATUM_1418040 638 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 639 default y 640 depends on COMPAT 641 help 642 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 643 errata 1188873 and 1418040. 644 645 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 646 cause register corruption when accessing the timer registers 647 from AArch32 userspace. 648 649 If unsure, say Y. 650 651config ARM64_WORKAROUND_SPECULATIVE_AT 652 bool 653 654config ARM64_ERRATUM_1165522 655 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 656 default y 657 select ARM64_WORKAROUND_SPECULATIVE_AT 658 help 659 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 660 661 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 662 corrupted TLBs by speculating an AT instruction during a guest 663 context switch. 664 665 If unsure, say Y. 666 667config ARM64_ERRATUM_1319367 668 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 669 default y 670 select ARM64_WORKAROUND_SPECULATIVE_AT 671 help 672 This option adds work arounds for ARM Cortex-A57 erratum 1319537 673 and A72 erratum 1319367 674 675 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 676 speculating an AT instruction during a guest context switch. 677 678 If unsure, say Y. 679 680config ARM64_ERRATUM_1530923 681 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 682 default y 683 select ARM64_WORKAROUND_SPECULATIVE_AT 684 help 685 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 686 687 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 688 corrupted TLBs by speculating an AT instruction during a guest 689 context switch. 690 691 If unsure, say Y. 692 693config ARM64_WORKAROUND_REPEAT_TLBI 694 bool 695 696config ARM64_ERRATUM_2441007 697 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" 698 default y 699 select ARM64_WORKAROUND_REPEAT_TLBI 700 help 701 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 702 703 Under very rare circumstances, affected Cortex-A55 CPUs 704 may not handle a race between a break-before-make sequence on one 705 CPU, and another CPU accessing the same page. This could allow a 706 store to a page that has been unmapped. 707 708 Work around this by adding the affected CPUs to the list that needs 709 TLB sequences to be done twice. 710 711 If unsure, say Y. 712 713config ARM64_ERRATUM_1286807 714 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" 715 default y 716 select ARM64_WORKAROUND_REPEAT_TLBI 717 help 718 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 719 720 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 721 address for a cacheable mapping of a location is being 722 accessed by a core while another core is remapping the virtual 723 address to a new physical page using the recommended 724 break-before-make sequence, then under very rare circumstances 725 TLBI+DSB completes before a read using the translation being 726 invalidated has been observed by other observers. The 727 workaround repeats the TLBI+DSB operation. 728 729config ARM64_ERRATUM_1463225 730 bool "Cortex-A76: Software Step might prevent interrupt recognition" 731 default y 732 help 733 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 734 735 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 736 of a system call instruction (SVC) can prevent recognition of 737 subsequent interrupts when software stepping is disabled in the 738 exception handler of the system call and either kernel debugging 739 is enabled or VHE is in use. 740 741 Work around the erratum by triggering a dummy step exception 742 when handling a system call from a task that is being stepped 743 in a VHE configuration of the kernel. 744 745 If unsure, say Y. 746 747config ARM64_ERRATUM_1542419 748 bool "Neoverse-N1: workaround mis-ordering of instruction fetches" 749 default y 750 help 751 This option adds a workaround for ARM Neoverse-N1 erratum 752 1542419. 753 754 Affected Neoverse-N1 cores could execute a stale instruction when 755 modified by another CPU. The workaround depends on a firmware 756 counterpart. 757 758 Workaround the issue by hiding the DIC feature from EL0. This 759 forces user-space to perform cache maintenance. 760 761 If unsure, say Y. 762 763config ARM64_ERRATUM_1508412 764 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 765 default y 766 help 767 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 768 769 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 770 of a store-exclusive or read of PAR_EL1 and a load with device or 771 non-cacheable memory attributes. The workaround depends on a firmware 772 counterpart. 773 774 KVM guests must also have the workaround implemented or they can 775 deadlock the system. 776 777 Work around the issue by inserting DMB SY barriers around PAR_EL1 778 register reads and warning KVM users. The DMB barrier is sufficient 779 to prevent a speculative PAR_EL1 read. 780 781 If unsure, say Y. 782 783config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 784 bool 785 786config ARM64_ERRATUM_2051678 787 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 788 default y 789 help 790 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 791 Affected Cortex-A510 might not respect the ordering rules for 792 hardware update of the page table's dirty bit. The workaround 793 is to not enable the feature on affected CPUs. 794 795 If unsure, say Y. 796 797config ARM64_ERRATUM_2077057 798 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 799 default y 800 help 801 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 802 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 803 expected, but a Pointer Authentication trap is taken instead. The 804 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 805 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 806 807 This can only happen when EL2 is stepping EL1. 808 809 When these conditions occur, the SPSR_EL2 value is unchanged from the 810 previous guest entry, and can be restored from the in-memory copy. 811 812 If unsure, say Y. 813 814config ARM64_ERRATUM_2658417 815 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 816 default y 817 help 818 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 819 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 820 BFMMLA or VMMLA instructions in rare circumstances when a pair of 821 A510 CPUs are using shared neon hardware. As the sharing is not 822 discoverable by the kernel, hide the BF16 HWCAP to indicate that 823 user-space should not be using these instructions. 824 825 If unsure, say Y. 826 827config ARM64_ERRATUM_2119858 828 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 829 default y 830 depends on CORESIGHT_TRBE 831 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 832 help 833 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 834 835 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 836 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 837 the event of a WRAP event. 838 839 Work around the issue by always making sure we move the TRBPTR_EL1 by 840 256 bytes before enabling the buffer and filling the first 256 bytes of 841 the buffer with ETM ignore packets upon disabling. 842 843 If unsure, say Y. 844 845config ARM64_ERRATUM_2139208 846 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 847 default y 848 depends on CORESIGHT_TRBE 849 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 850 help 851 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 852 853 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 854 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 855 the event of a WRAP event. 856 857 Work around the issue by always making sure we move the TRBPTR_EL1 by 858 256 bytes before enabling the buffer and filling the first 256 bytes of 859 the buffer with ETM ignore packets upon disabling. 860 861 If unsure, say Y. 862 863config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 864 bool 865 866config ARM64_ERRATUM_2054223 867 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 868 default y 869 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 870 help 871 Enable workaround for ARM Cortex-A710 erratum 2054223 872 873 Affected cores may fail to flush the trace data on a TSB instruction, when 874 the PE is in trace prohibited state. This will cause losing a few bytes 875 of the trace cached. 876 877 Workaround is to issue two TSB consecutively on affected cores. 878 879 If unsure, say Y. 880 881config ARM64_ERRATUM_2067961 882 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 883 default y 884 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 885 help 886 Enable workaround for ARM Neoverse-N2 erratum 2067961 887 888 Affected cores may fail to flush the trace data on a TSB instruction, when 889 the PE is in trace prohibited state. This will cause losing a few bytes 890 of the trace cached. 891 892 Workaround is to issue two TSB consecutively on affected cores. 893 894 If unsure, say Y. 895 896config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 897 bool 898 899config ARM64_ERRATUM_2253138 900 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 901 depends on CORESIGHT_TRBE 902 default y 903 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 904 help 905 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 906 907 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 908 for TRBE. Under some conditions, the TRBE might generate a write to the next 909 virtually addressed page following the last page of the TRBE address space 910 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 911 912 Work around this in the driver by always making sure that there is a 913 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 914 915 If unsure, say Y. 916 917config ARM64_ERRATUM_2224489 918 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 919 depends on CORESIGHT_TRBE 920 default y 921 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 922 help 923 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 924 925 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 926 for TRBE. Under some conditions, the TRBE might generate a write to the next 927 virtually addressed page following the last page of the TRBE address space 928 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 929 930 Work around this in the driver by always making sure that there is a 931 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 932 933 If unsure, say Y. 934 935config ARM64_ERRATUM_2441009 936 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" 937 default y 938 select ARM64_WORKAROUND_REPEAT_TLBI 939 help 940 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 941 942 Under very rare circumstances, affected Cortex-A510 CPUs 943 may not handle a race between a break-before-make sequence on one 944 CPU, and another CPU accessing the same page. This could allow a 945 store to a page that has been unmapped. 946 947 Work around this by adding the affected CPUs to the list that needs 948 TLB sequences to be done twice. 949 950 If unsure, say Y. 951 952config ARM64_ERRATUM_2064142 953 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 954 depends on CORESIGHT_TRBE 955 default y 956 help 957 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 958 959 Affected Cortex-A510 core might fail to write into system registers after the 960 TRBE has been disabled. Under some conditions after the TRBE has been disabled 961 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 962 and TRBTRG_EL1 will be ignored and will not be effected. 963 964 Work around this in the driver by executing TSB CSYNC and DSB after collection 965 is stopped and before performing a system register write to one of the affected 966 registers. 967 968 If unsure, say Y. 969 970config ARM64_ERRATUM_2038923 971 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 972 depends on CORESIGHT_TRBE 973 default y 974 help 975 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 976 977 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 978 prohibited within the CPU. As a result, the trace buffer or trace buffer state 979 might be corrupted. This happens after TRBE buffer has been enabled by setting 980 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 981 execution changes from a context, in which trace is prohibited to one where it 982 isn't, or vice versa. In these mentioned conditions, the view of whether trace 983 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 984 the trace buffer state might be corrupted. 985 986 Work around this in the driver by preventing an inconsistent view of whether the 987 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 988 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 989 two ISB instructions if no ERET is to take place. 990 991 If unsure, say Y. 992 993config ARM64_ERRATUM_1902691 994 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 995 depends on CORESIGHT_TRBE 996 default y 997 help 998 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 999 1000 Affected Cortex-A510 core might cause trace data corruption, when being written 1001 into the memory. Effectively TRBE is broken and hence cannot be used to capture 1002 trace data. 1003 1004 Work around this problem in the driver by just preventing TRBE initialization on 1005 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1006 on such implementations. This will cover the kernel for any firmware that doesn't 1007 do this already. 1008 1009 If unsure, say Y. 1010 1011config ARM64_ERRATUM_2457168 1012 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1013 depends on ARM64_AMU_EXTN 1014 default y 1015 help 1016 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1017 1018 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1019 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1020 incorrectly giving a significantly higher output value. 1021 1022 Work around this problem by returning 0 when reading the affected counter in 1023 key locations that results in disabling all users of this counter. This effect 1024 is the same to firmware disabling affected counters. 1025 1026 If unsure, say Y. 1027 1028config ARM64_ERRATUM_2645198 1029 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1030 default y 1031 help 1032 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1033 1034 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1035 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1036 next instruction abort caused by permission fault. 1037 1038 Only user-space does executable to non-executable permission transition via 1039 mprotect() system call. Workaround the problem by doing a break-before-make 1040 TLB invalidation, for all changes to executable user space mappings. 1041 1042 If unsure, say Y. 1043 1044config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1045 bool 1046 1047config ARM64_ERRATUM_2966298 1048 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1049 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1050 default y 1051 help 1052 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1053 1054 On an affected Cortex-A520 core, a speculatively executed unprivileged 1055 load might leak data from a privileged level via a cache side channel. 1056 1057 Work around this problem by executing a TLBI before returning to EL0. 1058 1059 If unsure, say Y. 1060 1061config ARM64_ERRATUM_3117295 1062 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1063 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1064 default y 1065 help 1066 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1067 1068 On an affected Cortex-A510 core, a speculatively executed unprivileged 1069 load might leak data from a privileged level via a cache side channel. 1070 1071 Work around this problem by executing a TLBI before returning to EL0. 1072 1073 If unsure, say Y. 1074 1075config ARM64_ERRATUM_3194386 1076 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" 1077 default y 1078 help 1079 This option adds the workaround for the following errata: 1080 1081 * ARM Cortex-A76 erratum 3324349 1082 * ARM Cortex-A77 erratum 3324348 1083 * ARM Cortex-A78 erratum 3324344 1084 * ARM Cortex-A78C erratum 3324346 1085 * ARM Cortex-A78C erratum 3324347 1086 * ARM Cortex-A710 erratam 3324338 1087 * ARM Cortex-A720 erratum 3456091 1088 * ARM Cortex-A725 erratum 3456106 1089 * ARM Cortex-X1 erratum 3324344 1090 * ARM Cortex-X1C erratum 3324346 1091 * ARM Cortex-X2 erratum 3324338 1092 * ARM Cortex-X3 erratum 3324335 1093 * ARM Cortex-X4 erratum 3194386 1094 * ARM Cortex-X925 erratum 3324334 1095 * ARM Neoverse-N1 erratum 3324349 1096 * ARM Neoverse N2 erratum 3324339 1097 * ARM Neoverse-V1 erratum 3324341 1098 * ARM Neoverse V2 erratum 3324336 1099 * ARM Neoverse-V3 erratum 3312417 1100 1101 On affected cores "MSR SSBS, #0" instructions may not affect 1102 subsequent speculative instructions, which may permit unexepected 1103 speculative store bypassing. 1104 1105 Work around this problem by placing a Speculation Barrier (SB) or 1106 Instruction Synchronization Barrier (ISB) after kernel changes to 1107 SSBS. The presence of the SSBS special-purpose register is hidden 1108 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace 1109 will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. 1110 1111 If unsure, say Y. 1112 1113config CAVIUM_ERRATUM_22375 1114 bool "Cavium erratum 22375, 24313" 1115 default y 1116 help 1117 Enable workaround for errata 22375 and 24313. 1118 1119 This implements two gicv3-its errata workarounds for ThunderX. Both 1120 with a small impact affecting only ITS table allocation. 1121 1122 erratum 22375: only alloc 8MB table size 1123 erratum 24313: ignore memory access type 1124 1125 The fixes are in ITS initialization and basically ignore memory access 1126 type and table size provided by the TYPER and BASER registers. 1127 1128 If unsure, say Y. 1129 1130config CAVIUM_ERRATUM_23144 1131 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1132 depends on NUMA 1133 default y 1134 help 1135 ITS SYNC command hang for cross node io and collections/cpu mapping. 1136 1137 If unsure, say Y. 1138 1139config CAVIUM_ERRATUM_23154 1140 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1141 default y 1142 help 1143 The ThunderX GICv3 implementation requires a modified version for 1144 reading the IAR status to ensure data synchronization 1145 (access to icc_iar1_el1 is not sync'ed before and after). 1146 1147 It also suffers from erratum 38545 (also present on Marvell's 1148 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1149 spuriously presented to the CPU interface. 1150 1151 If unsure, say Y. 1152 1153config CAVIUM_ERRATUM_27456 1154 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1155 default y 1156 help 1157 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1158 instructions may cause the icache to become corrupted if it 1159 contains data for a non-current ASID. The fix is to 1160 invalidate the icache when changing the mm context. 1161 1162 If unsure, say Y. 1163 1164config CAVIUM_ERRATUM_30115 1165 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1166 default y 1167 help 1168 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1169 1.2, and T83 Pass 1.0, KVM guest execution may disable 1170 interrupts in host. Trapping both GICv3 group-0 and group-1 1171 accesses sidesteps the issue. 1172 1173 If unsure, say Y. 1174 1175config CAVIUM_TX2_ERRATUM_219 1176 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1177 default y 1178 help 1179 On Cavium ThunderX2, a load, store or prefetch instruction between a 1180 TTBR update and the corresponding context synchronizing operation can 1181 cause a spurious Data Abort to be delivered to any hardware thread in 1182 the CPU core. 1183 1184 Work around the issue by avoiding the problematic code sequence and 1185 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1186 trap handler performs the corresponding register access, skips the 1187 instruction and ensures context synchronization by virtue of the 1188 exception return. 1189 1190 If unsure, say Y. 1191 1192config FUJITSU_ERRATUM_010001 1193 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1194 default y 1195 help 1196 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1197 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1198 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1199 This fault occurs under a specific hardware condition when a 1200 load/store instruction performs an address translation using: 1201 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1202 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1203 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1204 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1205 1206 The workaround is to ensure these bits are clear in TCR_ELx. 1207 The workaround only affects the Fujitsu-A64FX. 1208 1209 If unsure, say Y. 1210 1211config HISILICON_ERRATUM_161600802 1212 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1213 default y 1214 help 1215 The HiSilicon Hip07 SoC uses the wrong redistributor base 1216 when issued ITS commands such as VMOVP and VMAPP, and requires 1217 a 128kB offset to be applied to the target address in this commands. 1218 1219 If unsure, say Y. 1220 1221config QCOM_FALKOR_ERRATUM_1003 1222 bool "Falkor E1003: Incorrect translation due to ASID change" 1223 default y 1224 help 1225 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1226 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1227 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1228 then only for entries in the walk cache, since the leaf translation 1229 is unchanged. Work around the erratum by invalidating the walk cache 1230 entries for the trampoline before entering the kernel proper. 1231 1232config QCOM_FALKOR_ERRATUM_1009 1233 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1234 default y 1235 select ARM64_WORKAROUND_REPEAT_TLBI 1236 help 1237 On Falkor v1, the CPU may prematurely complete a DSB following a 1238 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1239 one more time to fix the issue. 1240 1241 If unsure, say Y. 1242 1243config QCOM_QDF2400_ERRATUM_0065 1244 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1245 default y 1246 help 1247 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1248 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1249 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1250 1251 If unsure, say Y. 1252 1253config QCOM_FALKOR_ERRATUM_E1041 1254 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1255 default y 1256 help 1257 Falkor CPU may speculatively fetch instructions from an improper 1258 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1259 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1260 1261 If unsure, say Y. 1262 1263config NVIDIA_CARMEL_CNP_ERRATUM 1264 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1265 default y 1266 help 1267 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1268 invalidate shared TLB entries installed by a different core, as it would 1269 on standard ARM cores. 1270 1271 If unsure, say Y. 1272 1273config ROCKCHIP_ERRATUM_3588001 1274 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1275 default y 1276 help 1277 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1278 This means, that its sharability feature may not be used, even though it 1279 is supported by the IP itself. 1280 1281 If unsure, say Y. 1282 1283config SOCIONEXT_SYNQUACER_PREITS 1284 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1285 default y 1286 help 1287 Socionext Synquacer SoCs implement a separate h/w block to generate 1288 MSI doorbell writes with non-zero values for the device ID. 1289 1290 If unsure, say Y. 1291 1292endmenu # "ARM errata workarounds via the alternatives framework" 1293 1294choice 1295 prompt "Page size" 1296 default ARM64_4K_PAGES 1297 help 1298 Page size (translation granule) configuration. 1299 1300config ARM64_4K_PAGES 1301 bool "4KB" 1302 help 1303 This feature enables 4KB pages support. 1304 1305config ARM64_16K_PAGES 1306 bool "16KB" 1307 help 1308 The system will use 16KB pages support. AArch32 emulation 1309 requires applications compiled with 16K (or a multiple of 16K) 1310 aligned segments. 1311 1312config ARM64_64K_PAGES 1313 bool "64KB" 1314 help 1315 This feature enables 64KB pages support (4KB by default) 1316 allowing only two levels of page tables and faster TLB 1317 look-up. AArch32 emulation requires applications compiled 1318 with 64K aligned segments. 1319 1320endchoice 1321 1322choice 1323 prompt "Virtual address space size" 1324 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 1325 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 1326 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 1327 help 1328 Allows choosing one of multiple possible virtual address 1329 space sizes. The level of translation table is determined by 1330 a combination of page size and virtual address space size. 1331 1332config ARM64_VA_BITS_36 1333 bool "36-bit" if EXPERT 1334 depends on ARM64_16K_PAGES 1335 1336config ARM64_VA_BITS_39 1337 bool "39-bit" 1338 depends on ARM64_4K_PAGES 1339 1340config ARM64_VA_BITS_42 1341 bool "42-bit" 1342 depends on ARM64_64K_PAGES 1343 1344config ARM64_VA_BITS_47 1345 bool "47-bit" 1346 depends on ARM64_16K_PAGES 1347 1348config ARM64_VA_BITS_48 1349 bool "48-bit" 1350 1351config ARM64_VA_BITS_52 1352 bool "52-bit" 1353 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN) 1354 help 1355 Enable 52-bit virtual addressing for userspace when explicitly 1356 requested via a hint to mmap(). The kernel will also use 52-bit 1357 virtual addresses for its own mappings (provided HW support for 1358 this feature is available, otherwise it reverts to 48-bit). 1359 1360 NOTE: Enabling 52-bit virtual addressing in conjunction with 1361 ARMv8.3 Pointer Authentication will result in the PAC being 1362 reduced from 7 bits to 3 bits, which may have a significant 1363 impact on its susceptibility to brute-force attacks. 1364 1365 If unsure, select 48-bit virtual addressing instead. 1366 1367endchoice 1368 1369config ARM64_FORCE_52BIT 1370 bool "Force 52-bit virtual addresses for userspace" 1371 depends on ARM64_VA_BITS_52 && EXPERT 1372 help 1373 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1374 to maintain compatibility with older software by providing 48-bit VAs 1375 unless a hint is supplied to mmap. 1376 1377 This configuration option disables the 48-bit compatibility logic, and 1378 forces all userspace addresses to be 52-bit on HW that supports it. One 1379 should only enable this configuration option for stress testing userspace 1380 memory management code. If unsure say N here. 1381 1382config ARM64_VA_BITS 1383 int 1384 default 36 if ARM64_VA_BITS_36 1385 default 39 if ARM64_VA_BITS_39 1386 default 42 if ARM64_VA_BITS_42 1387 default 47 if ARM64_VA_BITS_47 1388 default 48 if ARM64_VA_BITS_48 1389 default 52 if ARM64_VA_BITS_52 1390 1391choice 1392 prompt "Physical address space size" 1393 default ARM64_PA_BITS_48 1394 help 1395 Choose the maximum physical address range that the kernel will 1396 support. 1397 1398config ARM64_PA_BITS_48 1399 bool "48-bit" 1400 1401config ARM64_PA_BITS_52 1402 bool "52-bit (ARMv8.2)" 1403 depends on ARM64_64K_PAGES 1404 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1405 help 1406 Enable support for a 52-bit physical address space, introduced as 1407 part of the ARMv8.2-LPA extension. 1408 1409 With this enabled, the kernel will also continue to work on CPUs that 1410 do not support ARMv8.2-LPA, but with some added memory overhead (and 1411 minor performance overhead). 1412 1413endchoice 1414 1415config ARM64_PA_BITS 1416 int 1417 default 48 if ARM64_PA_BITS_48 1418 default 52 if ARM64_PA_BITS_52 1419 1420choice 1421 prompt "Endianness" 1422 default CPU_LITTLE_ENDIAN 1423 help 1424 Select the endianness of data accesses performed by the CPU. Userspace 1425 applications will need to be compiled and linked for the endianness 1426 that is selected here. 1427 1428config CPU_BIG_ENDIAN 1429 bool "Build big-endian kernel" 1430 depends on !LD_IS_LLD || LLD_VERSION >= 130000 1431 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c 1432 depends on AS_IS_GNU || AS_VERSION >= 150000 1433 help 1434 Say Y if you plan on running a kernel with a big-endian userspace. 1435 1436config CPU_LITTLE_ENDIAN 1437 bool "Build little-endian kernel" 1438 help 1439 Say Y if you plan on running a kernel with a little-endian userspace. 1440 This is usually the case for distributions targeting arm64. 1441 1442endchoice 1443 1444config SCHED_MC 1445 bool "Multi-core scheduler support" 1446 help 1447 Multi-core scheduler support improves the CPU scheduler's decision 1448 making when dealing with multi-core CPU chips at a cost of slightly 1449 increased overhead in some places. If unsure say N here. 1450 1451config SCHED_CLUSTER 1452 bool "Cluster scheduler support" 1453 help 1454 Cluster scheduler support improves the CPU scheduler's decision 1455 making when dealing with machines that have clusters of CPUs. 1456 Cluster usually means a couple of CPUs which are placed closely 1457 by sharing mid-level caches, last-level cache tags or internal 1458 busses. 1459 1460config SCHED_SMT 1461 bool "SMT scheduler support" 1462 help 1463 Improves the CPU scheduler's decision making when dealing with 1464 MultiThreading at a cost of slightly increased overhead in some 1465 places. If unsure say N here. 1466 1467config NR_CPUS 1468 int "Maximum number of CPUs (2-4096)" 1469 range 2 4096 1470 default "256" 1471 1472config HOTPLUG_CPU 1473 bool "Support for hot-pluggable CPUs" 1474 select GENERIC_IRQ_MIGRATION 1475 help 1476 Say Y here to experiment with turning CPUs off and on. CPUs 1477 can be controlled through /sys/devices/system/cpu. 1478 1479# Common NUMA Features 1480config NUMA 1481 bool "NUMA Memory Allocation and Scheduler Support" 1482 select GENERIC_ARCH_NUMA 1483 select ACPI_NUMA if ACPI 1484 select OF_NUMA 1485 select HAVE_SETUP_PER_CPU_AREA 1486 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1487 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1488 select USE_PERCPU_NUMA_NODE_ID 1489 help 1490 Enable NUMA (Non-Uniform Memory Access) support. 1491 1492 The kernel will try to allocate memory used by a CPU on the 1493 local memory of the CPU and add some more 1494 NUMA awareness to the kernel. 1495 1496config NODES_SHIFT 1497 int "Maximum NUMA Nodes (as a power of 2)" 1498 range 1 10 1499 default "4" 1500 depends on NUMA 1501 help 1502 Specify the maximum number of NUMA Nodes available on the target 1503 system. Increases memory reserved to accommodate various tables. 1504 1505source "kernel/Kconfig.hz" 1506 1507config ARCH_SPARSEMEM_ENABLE 1508 def_bool y 1509 select SPARSEMEM_VMEMMAP_ENABLE 1510 select SPARSEMEM_VMEMMAP 1511 1512config HW_PERF_EVENTS 1513 def_bool y 1514 depends on ARM_PMU 1515 1516# Supported by clang >= 7.0 or GCC >= 12.0.0 1517config CC_HAVE_SHADOW_CALL_STACK 1518 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1519 1520config PARAVIRT 1521 bool "Enable paravirtualization code" 1522 help 1523 This changes the kernel so it can modify itself when it is run 1524 under a hypervisor, potentially improving performance significantly 1525 over full virtualization. 1526 1527config PARAVIRT_TIME_ACCOUNTING 1528 bool "Paravirtual steal time accounting" 1529 select PARAVIRT 1530 help 1531 Select this option to enable fine granularity task steal time 1532 accounting. Time spent executing other tasks in parallel with 1533 the current vCPU is discounted from the vCPU power. To account for 1534 that, there can be a small performance impact. 1535 1536 If in doubt, say N here. 1537 1538config ARCH_SUPPORTS_KEXEC 1539 def_bool PM_SLEEP_SMP 1540 1541config ARCH_SUPPORTS_KEXEC_FILE 1542 def_bool y 1543 1544config ARCH_SELECTS_KEXEC_FILE 1545 def_bool y 1546 depends on KEXEC_FILE 1547 select HAVE_IMA_KEXEC if IMA 1548 1549config ARCH_SUPPORTS_KEXEC_SIG 1550 def_bool y 1551 1552config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1553 def_bool y 1554 1555config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1556 def_bool y 1557 1558config ARCH_SUPPORTS_CRASH_DUMP 1559 def_bool y 1560 1561config TRANS_TABLE 1562 def_bool y 1563 depends on HIBERNATION || KEXEC_CORE 1564 1565config XEN_DOM0 1566 def_bool y 1567 depends on XEN 1568 1569config XEN 1570 bool "Xen guest support on ARM64" 1571 depends on ARM64 && OF 1572 select SWIOTLB_XEN 1573 select PARAVIRT 1574 help 1575 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1576 1577# include/linux/mmzone.h requires the following to be true: 1578# 1579# MAX_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1580# 1581# so the maximum value of MAX_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1582# 1583# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_ORDER | default MAX_ORDER | 1584# ----+-------------------+--------------+-----------------+--------------------+ 1585# 4K | 27 | 12 | 15 | 10 | 1586# 16K | 27 | 14 | 13 | 11 | 1587# 64K | 29 | 16 | 13 | 13 | 1588config ARCH_FORCE_MAX_ORDER 1589 int 1590 default "13" if ARM64_64K_PAGES 1591 default "11" if ARM64_16K_PAGES 1592 default "10" 1593 help 1594 The kernel page allocator limits the size of maximal physically 1595 contiguous allocations. The limit is called MAX_ORDER and it 1596 defines the maximal power of two of number of pages that can be 1597 allocated as a single contiguous block. This option allows 1598 overriding the default setting when ability to allocate very 1599 large blocks of physically contiguous memory is required. 1600 1601 The maximal size of allocation cannot exceed the size of the 1602 section, so the value of MAX_ORDER should satisfy 1603 1604 MAX_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1605 1606 Don't change if unsure. 1607 1608config UNMAP_KERNEL_AT_EL0 1609 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT 1610 default y 1611 help 1612 Speculation attacks against some high-performance processors can 1613 be used to bypass MMU permission checks and leak kernel data to 1614 userspace. This can be defended against by unmapping the kernel 1615 when running in userspace, mapping it back in on exception entry 1616 via a trampoline page in the vector table. 1617 1618 If unsure, say Y. 1619 1620config MITIGATE_SPECTRE_BRANCH_HISTORY 1621 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1622 default y 1623 help 1624 Speculation attacks against some high-performance processors can 1625 make use of branch history to influence future speculation. 1626 When taking an exception from user-space, a sequence of branches 1627 or a firmware call overwrites the branch history. 1628 1629config RODATA_FULL_DEFAULT_ENABLED 1630 bool "Apply r/o permissions of VM areas also to their linear aliases" 1631 default y 1632 help 1633 Apply read-only attributes of VM areas to the linear alias of 1634 the backing pages as well. This prevents code or read-only data 1635 from being modified (inadvertently or intentionally) via another 1636 mapping of the same memory page. This additional enhancement can 1637 be turned off at runtime by passing rodata=[off|on] (and turned on 1638 with rodata=full if this option is set to 'n') 1639 1640 This requires the linear region to be mapped down to pages, 1641 which may adversely affect performance in some cases. 1642 1643config ARM64_SW_TTBR0_PAN 1644 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1645 help 1646 Enabling this option prevents the kernel from accessing 1647 user-space memory directly by pointing TTBR0_EL1 to a reserved 1648 zeroed area and reserved ASID. The user access routines 1649 restore the valid TTBR0_EL1 temporarily. 1650 1651config ARM64_TAGGED_ADDR_ABI 1652 bool "Enable the tagged user addresses syscall ABI" 1653 default y 1654 help 1655 When this option is enabled, user applications can opt in to a 1656 relaxed ABI via prctl() allowing tagged addresses to be passed 1657 to system calls as pointer arguments. For details, see 1658 Documentation/arch/arm64/tagged-address-abi.rst. 1659 1660menuconfig COMPAT 1661 bool "Kernel support for 32-bit EL0" 1662 depends on ARM64_4K_PAGES || EXPERT 1663 select HAVE_UID16 1664 select OLD_SIGSUSPEND3 1665 select COMPAT_OLD_SIGACTION 1666 help 1667 This option enables support for a 32-bit EL0 running under a 64-bit 1668 kernel at EL1. AArch32-specific components such as system calls, 1669 the user helper functions, VFP support and the ptrace interface are 1670 handled appropriately by the kernel. 1671 1672 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1673 that you will only be able to execute AArch32 binaries that were compiled 1674 with page size aligned segments. 1675 1676 If you want to execute 32-bit userspace applications, say Y. 1677 1678if COMPAT 1679 1680config KUSER_HELPERS 1681 bool "Enable kuser helpers page for 32-bit applications" 1682 default y 1683 help 1684 Warning: disabling this option may break 32-bit user programs. 1685 1686 Provide kuser helpers to compat tasks. The kernel provides 1687 helper code to userspace in read only form at a fixed location 1688 to allow userspace to be independent of the CPU type fitted to 1689 the system. This permits binaries to be run on ARMv4 through 1690 to ARMv8 without modification. 1691 1692 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1693 1694 However, the fixed address nature of these helpers can be used 1695 by ROP (return orientated programming) authors when creating 1696 exploits. 1697 1698 If all of the binaries and libraries which run on your platform 1699 are built specifically for your platform, and make no use of 1700 these helpers, then you can turn this option off to hinder 1701 such exploits. However, in that case, if a binary or library 1702 relying on those helpers is run, it will not function correctly. 1703 1704 Say N here only if you are absolutely certain that you do not 1705 need these helpers; otherwise, the safe option is to say Y. 1706 1707config COMPAT_VDSO 1708 bool "Enable vDSO for 32-bit applications" 1709 depends on !CPU_BIG_ENDIAN 1710 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1711 select GENERIC_COMPAT_VDSO 1712 default y 1713 help 1714 Place in the process address space of 32-bit applications an 1715 ELF shared object providing fast implementations of gettimeofday 1716 and clock_gettime. 1717 1718 You must have a 32-bit build of glibc 2.22 or later for programs 1719 to seamlessly take advantage of this. 1720 1721config THUMB2_COMPAT_VDSO 1722 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1723 depends on COMPAT_VDSO 1724 default y 1725 help 1726 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1727 otherwise with '-marm'. 1728 1729config COMPAT_ALIGNMENT_FIXUPS 1730 bool "Fix up misaligned multi-word loads and stores in user space" 1731 1732menuconfig ARMV8_DEPRECATED 1733 bool "Emulate deprecated/obsolete ARMv8 instructions" 1734 depends on SYSCTL 1735 help 1736 Legacy software support may require certain instructions 1737 that have been deprecated or obsoleted in the architecture. 1738 1739 Enable this config to enable selective emulation of these 1740 features. 1741 1742 If unsure, say Y 1743 1744if ARMV8_DEPRECATED 1745 1746config SWP_EMULATION 1747 bool "Emulate SWP/SWPB instructions" 1748 help 1749 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1750 they are always undefined. Say Y here to enable software 1751 emulation of these instructions for userspace using LDXR/STXR. 1752 This feature can be controlled at runtime with the abi.swp 1753 sysctl which is disabled by default. 1754 1755 In some older versions of glibc [<=2.8] SWP is used during futex 1756 trylock() operations with the assumption that the code will not 1757 be preempted. This invalid assumption may be more likely to fail 1758 with SWP emulation enabled, leading to deadlock of the user 1759 application. 1760 1761 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1762 on an external transaction monitoring block called a global 1763 monitor to maintain update atomicity. If your system does not 1764 implement a global monitor, this option can cause programs that 1765 perform SWP operations to uncached memory to deadlock. 1766 1767 If unsure, say Y 1768 1769config CP15_BARRIER_EMULATION 1770 bool "Emulate CP15 Barrier instructions" 1771 help 1772 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1773 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1774 strongly recommended to use the ISB, DSB, and DMB 1775 instructions instead. 1776 1777 Say Y here to enable software emulation of these 1778 instructions for AArch32 userspace code. When this option is 1779 enabled, CP15 barrier usage is traced which can help 1780 identify software that needs updating. This feature can be 1781 controlled at runtime with the abi.cp15_barrier sysctl. 1782 1783 If unsure, say Y 1784 1785config SETEND_EMULATION 1786 bool "Emulate SETEND instruction" 1787 help 1788 The SETEND instruction alters the data-endianness of the 1789 AArch32 EL0, and is deprecated in ARMv8. 1790 1791 Say Y here to enable software emulation of the instruction 1792 for AArch32 userspace code. This feature can be controlled 1793 at runtime with the abi.setend sysctl. 1794 1795 Note: All the cpus on the system must have mixed endian support at EL0 1796 for this feature to be enabled. If a new CPU - which doesn't support mixed 1797 endian - is hotplugged in after this feature has been enabled, there could 1798 be unexpected results in the applications. 1799 1800 If unsure, say Y 1801endif # ARMV8_DEPRECATED 1802 1803endif # COMPAT 1804 1805menu "ARMv8.1 architectural features" 1806 1807config ARM64_HW_AFDBM 1808 bool "Support for hardware updates of the Access and Dirty page flags" 1809 default y 1810 help 1811 The ARMv8.1 architecture extensions introduce support for 1812 hardware updates of the access and dirty information in page 1813 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1814 capable processors, accesses to pages with PTE_AF cleared will 1815 set this bit instead of raising an access flag fault. 1816 Similarly, writes to read-only pages with the DBM bit set will 1817 clear the read-only bit (AP[2]) instead of raising a 1818 permission fault. 1819 1820 Kernels built with this configuration option enabled continue 1821 to work on pre-ARMv8.1 hardware and the performance impact is 1822 minimal. If unsure, say Y. 1823 1824config ARM64_PAN 1825 bool "Enable support for Privileged Access Never (PAN)" 1826 default y 1827 help 1828 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1829 prevents the kernel or hypervisor from accessing user-space (EL0) 1830 memory directly. 1831 1832 Choosing this option will cause any unprotected (not using 1833 copy_to_user et al) memory access to fail with a permission fault. 1834 1835 The feature is detected at runtime, and will remain as a 'nop' 1836 instruction if the cpu does not implement the feature. 1837 1838config AS_HAS_LSE_ATOMICS 1839 def_bool $(as-instr,.arch_extension lse) 1840 1841config ARM64_LSE_ATOMICS 1842 bool 1843 default ARM64_USE_LSE_ATOMICS 1844 depends on AS_HAS_LSE_ATOMICS 1845 1846config ARM64_USE_LSE_ATOMICS 1847 bool "Atomic instructions" 1848 default y 1849 help 1850 As part of the Large System Extensions, ARMv8.1 introduces new 1851 atomic instructions that are designed specifically to scale in 1852 very large systems. 1853 1854 Say Y here to make use of these instructions for the in-kernel 1855 atomic routines. This incurs a small overhead on CPUs that do 1856 not support these instructions and requires the kernel to be 1857 built with binutils >= 2.25 in order for the new instructions 1858 to be used. 1859 1860endmenu # "ARMv8.1 architectural features" 1861 1862menu "ARMv8.2 architectural features" 1863 1864config AS_HAS_ARMV8_2 1865 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1866 1867config AS_HAS_SHA3 1868 def_bool $(as-instr,.arch armv8.2-a+sha3) 1869 1870config ARM64_PMEM 1871 bool "Enable support for persistent memory" 1872 select ARCH_HAS_PMEM_API 1873 select ARCH_HAS_UACCESS_FLUSHCACHE 1874 help 1875 Say Y to enable support for the persistent memory API based on the 1876 ARMv8.2 DCPoP feature. 1877 1878 The feature is detected at runtime, and the kernel will use DC CVAC 1879 operations if DC CVAP is not supported (following the behaviour of 1880 DC CVAP itself if the system does not define a point of persistence). 1881 1882config ARM64_RAS_EXTN 1883 bool "Enable support for RAS CPU Extensions" 1884 default y 1885 help 1886 CPUs that support the Reliability, Availability and Serviceability 1887 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1888 errors, classify them and report them to software. 1889 1890 On CPUs with these extensions system software can use additional 1891 barriers to determine if faults are pending and read the 1892 classification from a new set of registers. 1893 1894 Selecting this feature will allow the kernel to use these barriers 1895 and access the new registers if the system supports the extension. 1896 Platform RAS features may additionally depend on firmware support. 1897 1898config ARM64_CNP 1899 bool "Enable support for Common Not Private (CNP) translations" 1900 default y 1901 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1902 help 1903 Common Not Private (CNP) allows translation table entries to 1904 be shared between different PEs in the same inner shareable 1905 domain, so the hardware can use this fact to optimise the 1906 caching of such entries in the TLB. 1907 1908 Selecting this option allows the CNP feature to be detected 1909 at runtime, and does not affect PEs that do not implement 1910 this feature. 1911 1912endmenu # "ARMv8.2 architectural features" 1913 1914menu "ARMv8.3 architectural features" 1915 1916config ARM64_PTR_AUTH 1917 bool "Enable support for pointer authentication" 1918 default y 1919 help 1920 Pointer authentication (part of the ARMv8.3 Extensions) provides 1921 instructions for signing and authenticating pointers against secret 1922 keys, which can be used to mitigate Return Oriented Programming (ROP) 1923 and other attacks. 1924 1925 This option enables these instructions at EL0 (i.e. for userspace). 1926 Choosing this option will cause the kernel to initialise secret keys 1927 for each process at exec() time, with these keys being 1928 context-switched along with the process. 1929 1930 The feature is detected at runtime. If the feature is not present in 1931 hardware it will not be advertised to userspace/KVM guest nor will it 1932 be enabled. 1933 1934 If the feature is present on the boot CPU but not on a late CPU, then 1935 the late CPU will be parked. Also, if the boot CPU does not have 1936 address auth and the late CPU has then the late CPU will still boot 1937 but with the feature disabled. On such a system, this option should 1938 not be selected. 1939 1940config ARM64_PTR_AUTH_KERNEL 1941 bool "Use pointer authentication for kernel" 1942 default y 1943 depends on ARM64_PTR_AUTH 1944 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3 1945 # Modern compilers insert a .note.gnu.property section note for PAC 1946 # which is only understood by binutils starting with version 2.33.1. 1947 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1948 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1949 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 1950 help 1951 If the compiler supports the -mbranch-protection or 1952 -msign-return-address flag (e.g. GCC 7 or later), then this option 1953 will cause the kernel itself to be compiled with return address 1954 protection. In this case, and if the target hardware is known to 1955 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1956 disabled with minimal loss of protection. 1957 1958 This feature works with FUNCTION_GRAPH_TRACER option only if 1959 DYNAMIC_FTRACE_WITH_ARGS is enabled. 1960 1961config CC_HAS_BRANCH_PROT_PAC_RET 1962 # GCC 9 or later, clang 8 or later 1963 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1964 1965config CC_HAS_SIGN_RETURN_ADDRESS 1966 # GCC 7, 8 1967 def_bool $(cc-option,-msign-return-address=all) 1968 1969config AS_HAS_ARMV8_3 1970 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1971 1972config AS_HAS_CFI_NEGATE_RA_STATE 1973 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1974 1975config AS_HAS_LDAPR 1976 def_bool $(as-instr,.arch_extension rcpc) 1977 1978endmenu # "ARMv8.3 architectural features" 1979 1980menu "ARMv8.4 architectural features" 1981 1982config ARM64_AMU_EXTN 1983 bool "Enable support for the Activity Monitors Unit CPU extension" 1984 default y 1985 help 1986 The activity monitors extension is an optional extension introduced 1987 by the ARMv8.4 CPU architecture. This enables support for version 1 1988 of the activity monitors architecture, AMUv1. 1989 1990 To enable the use of this extension on CPUs that implement it, say Y. 1991 1992 Note that for architectural reasons, firmware _must_ implement AMU 1993 support when running on CPUs that present the activity monitors 1994 extension. The required support is present in: 1995 * Version 1.5 and later of the ARM Trusted Firmware 1996 1997 For kernels that have this configuration enabled but boot with broken 1998 firmware, you may need to say N here until the firmware is fixed. 1999 Otherwise you may experience firmware panics or lockups when 2000 accessing the counter registers. Even if you are not observing these 2001 symptoms, the values returned by the register reads might not 2002 correctly reflect reality. Most commonly, the value read will be 0, 2003 indicating that the counter is not enabled. 2004 2005config AS_HAS_ARMV8_4 2006 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 2007 2008config ARM64_TLB_RANGE 2009 bool "Enable support for tlbi range feature" 2010 default y 2011 depends on AS_HAS_ARMV8_4 2012 help 2013 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 2014 range of input addresses. 2015 2016 The feature introduces new assembly instructions, and they were 2017 support when binutils >= 2.30. 2018 2019endmenu # "ARMv8.4 architectural features" 2020 2021menu "ARMv8.5 architectural features" 2022 2023config AS_HAS_ARMV8_5 2024 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 2025 2026config ARM64_BTI 2027 bool "Branch Target Identification support" 2028 default y 2029 help 2030 Branch Target Identification (part of the ARMv8.5 Extensions) 2031 provides a mechanism to limit the set of locations to which computed 2032 branch instructions such as BR or BLR can jump. 2033 2034 To make use of BTI on CPUs that support it, say Y. 2035 2036 BTI is intended to provide complementary protection to other control 2037 flow integrity protection mechanisms, such as the Pointer 2038 authentication mechanism provided as part of the ARMv8.3 Extensions. 2039 For this reason, it does not make sense to enable this option without 2040 also enabling support for pointer authentication. Thus, when 2041 enabling this option you should also select ARM64_PTR_AUTH=y. 2042 2043 Userspace binaries must also be specifically compiled to make use of 2044 this mechanism. If you say N here or the hardware does not support 2045 BTI, such binaries can still run, but you get no additional 2046 enforcement of branch destinations. 2047 2048config ARM64_BTI_KERNEL 2049 bool "Use Branch Target Identification for kernel" 2050 default y 2051 depends on ARM64_BTI 2052 depends on ARM64_PTR_AUTH_KERNEL 2053 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2054 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2055 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2056 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2057 depends on !CC_IS_GCC 2058 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9 2059 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000 2060 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2061 help 2062 Build the kernel with Branch Target Identification annotations 2063 and enable enforcement of this for kernel code. When this option 2064 is enabled and the system supports BTI all kernel code including 2065 modular code must have BTI enabled. 2066 2067config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2068 # GCC 9 or later, clang 8 or later 2069 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2070 2071config ARM64_E0PD 2072 bool "Enable support for E0PD" 2073 default y 2074 help 2075 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2076 that EL0 accesses made via TTBR1 always fault in constant time, 2077 providing similar benefits to KASLR as those provided by KPTI, but 2078 with lower overhead and without disrupting legitimate access to 2079 kernel memory such as SPE. 2080 2081 This option enables E0PD for TTBR1 where available. 2082 2083config ARM64_AS_HAS_MTE 2084 # Initial support for MTE went in binutils 2.32.0, checked with 2085 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2086 # as a late addition to the final architecture spec (LDGM/STGM) 2087 # is only supported in the newer 2.32.x and 2.33 binutils 2088 # versions, hence the extra "stgm" instruction check below. 2089 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2090 2091config ARM64_MTE 2092 bool "Memory Tagging Extension support" 2093 default y 2094 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2095 depends on AS_HAS_ARMV8_5 2096 depends on AS_HAS_LSE_ATOMICS 2097 # Required for tag checking in the uaccess routines 2098 depends on ARM64_PAN 2099 select ARCH_HAS_SUBPAGE_FAULTS 2100 select ARCH_USES_HIGH_VMA_FLAGS 2101 select ARCH_USES_PG_ARCH_X 2102 help 2103 Memory Tagging (part of the ARMv8.5 Extensions) provides 2104 architectural support for run-time, always-on detection of 2105 various classes of memory error to aid with software debugging 2106 to eliminate vulnerabilities arising from memory-unsafe 2107 languages. 2108 2109 This option enables the support for the Memory Tagging 2110 Extension at EL0 (i.e. for userspace). 2111 2112 Selecting this option allows the feature to be detected at 2113 runtime. Any secondary CPU not implementing this feature will 2114 not be allowed a late bring-up. 2115 2116 Userspace binaries that want to use this feature must 2117 explicitly opt in. The mechanism for the userspace is 2118 described in: 2119 2120 Documentation/arch/arm64/memory-tagging-extension.rst. 2121 2122endmenu # "ARMv8.5 architectural features" 2123 2124menu "ARMv8.7 architectural features" 2125 2126config ARM64_EPAN 2127 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2128 default y 2129 depends on ARM64_PAN 2130 help 2131 Enhanced Privileged Access Never (EPAN) allows Privileged 2132 Access Never to be used with Execute-only mappings. 2133 2134 The feature is detected at runtime, and will remain disabled 2135 if the cpu does not implement the feature. 2136endmenu # "ARMv8.7 architectural features" 2137 2138config ARM64_SVE 2139 bool "ARM Scalable Vector Extension support" 2140 default y 2141 help 2142 The Scalable Vector Extension (SVE) is an extension to the AArch64 2143 execution state which complements and extends the SIMD functionality 2144 of the base architecture to support much larger vectors and to enable 2145 additional vectorisation opportunities. 2146 2147 To enable use of this extension on CPUs that implement it, say Y. 2148 2149 On CPUs that support the SVE2 extensions, this option will enable 2150 those too. 2151 2152 Note that for architectural reasons, firmware _must_ implement SVE 2153 support when running on SVE capable hardware. The required support 2154 is present in: 2155 2156 * version 1.5 and later of the ARM Trusted Firmware 2157 * the AArch64 boot wrapper since commit 5e1261e08abf 2158 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2159 2160 For other firmware implementations, consult the firmware documentation 2161 or vendor. 2162 2163 If you need the kernel to boot on SVE-capable hardware with broken 2164 firmware, you may need to say N here until you get your firmware 2165 fixed. Otherwise, you may experience firmware panics or lockups when 2166 booting the kernel. If unsure and you are not observing these 2167 symptoms, you should assume that it is safe to say Y. 2168 2169config ARM64_SME 2170 bool "ARM Scalable Matrix Extension support" 2171 default y 2172 depends on ARM64_SVE 2173 help 2174 The Scalable Matrix Extension (SME) is an extension to the AArch64 2175 execution state which utilises a substantial subset of the SVE 2176 instruction set, together with the addition of new architectural 2177 register state capable of holding two dimensional matrix tiles to 2178 enable various matrix operations. 2179 2180config ARM64_PSEUDO_NMI 2181 bool "Support for NMI-like interrupts" 2182 select ARM_GIC_V3 2183 help 2184 Adds support for mimicking Non-Maskable Interrupts through the use of 2185 GIC interrupt priority. This support requires version 3 or later of 2186 ARM GIC. 2187 2188 This high priority configuration for interrupts needs to be 2189 explicitly enabled by setting the kernel parameter 2190 "irqchip.gicv3_pseudo_nmi" to 1. 2191 2192 If unsure, say N 2193 2194if ARM64_PSEUDO_NMI 2195config ARM64_DEBUG_PRIORITY_MASKING 2196 bool "Debug interrupt priority masking" 2197 help 2198 This adds runtime checks to functions enabling/disabling 2199 interrupts when using priority masking. The additional checks verify 2200 the validity of ICC_PMR_EL1 when calling concerned functions. 2201 2202 If unsure, say N 2203endif # ARM64_PSEUDO_NMI 2204 2205config RELOCATABLE 2206 bool "Build a relocatable kernel image" if EXPERT 2207 select ARCH_HAS_RELR 2208 default y 2209 help 2210 This builds the kernel as a Position Independent Executable (PIE), 2211 which retains all relocation metadata required to relocate the 2212 kernel binary at runtime to a different virtual address than the 2213 address it was linked at. 2214 Since AArch64 uses the RELA relocation format, this requires a 2215 relocation pass at runtime even if the kernel is loaded at the 2216 same address it was linked at. 2217 2218config RANDOMIZE_BASE 2219 bool "Randomize the address of the kernel image" 2220 select RELOCATABLE 2221 help 2222 Randomizes the virtual address at which the kernel image is 2223 loaded, as a security feature that deters exploit attempts 2224 relying on knowledge of the location of kernel internals. 2225 2226 It is the bootloader's job to provide entropy, by passing a 2227 random u64 value in /chosen/kaslr-seed at kernel entry. 2228 2229 When booting via the UEFI stub, it will invoke the firmware's 2230 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2231 to the kernel proper. In addition, it will randomise the physical 2232 location of the kernel Image as well. 2233 2234 If unsure, say N. 2235 2236config RANDOMIZE_MODULE_REGION_FULL 2237 bool "Randomize the module region over a 2 GB range" 2238 depends on RANDOMIZE_BASE 2239 default y 2240 help 2241 Randomizes the location of the module region inside a 2 GB window 2242 covering the core kernel. This way, it is less likely for modules 2243 to leak information about the location of core kernel data structures 2244 but it does imply that function calls between modules and the core 2245 kernel will need to be resolved via veneers in the module PLT. 2246 2247 When this option is not set, the module region will be randomized over 2248 a limited range that contains the [_stext, _etext] interval of the 2249 core kernel, so branch relocations are almost always in range unless 2250 the region is exhausted. In this particular case of region 2251 exhaustion, modules might be able to fall back to a larger 2GB area. 2252 2253config CC_HAVE_STACKPROTECTOR_SYSREG 2254 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2255 2256config STACKPROTECTOR_PER_TASK 2257 def_bool y 2258 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2259 2260config UNWIND_PATCH_PAC_INTO_SCS 2261 bool "Enable shadow call stack dynamically using code patching" 2262 # needs Clang with https://reviews.llvm.org/D111780 incorporated 2263 depends on CC_IS_CLANG && CLANG_VERSION >= 150000 2264 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2265 depends on SHADOW_CALL_STACK 2266 select UNWIND_TABLES 2267 select DYNAMIC_SCS 2268 2269config ARM64_CONTPTE 2270 bool "Contiguous PTE mappings for user memory" if EXPERT 2271 depends on TRANSPARENT_HUGEPAGE 2272 default y 2273 help 2274 When enabled, user mappings are configured using the PTE contiguous 2275 bit, for any mappings that meet the size and alignment requirements. 2276 This reduces TLB pressure and improves performance. 2277 2278endmenu # "Kernel Features" 2279 2280menu "Boot options" 2281 2282config ARM64_ACPI_PARKING_PROTOCOL 2283 bool "Enable support for the ARM64 ACPI parking protocol" 2284 depends on ACPI 2285 help 2286 Enable support for the ARM64 ACPI parking protocol. If disabled 2287 the kernel will not allow booting through the ARM64 ACPI parking 2288 protocol even if the corresponding data is present in the ACPI 2289 MADT table. 2290 2291config CMDLINE 2292 string "Default kernel command string" 2293 default "" 2294 help 2295 Provide a set of default command-line options at build time by 2296 entering them here. As a minimum, you should specify the the 2297 root device (e.g. root=/dev/nfs). 2298 2299choice 2300 prompt "Kernel command line type" if CMDLINE != "" 2301 default CMDLINE_FROM_BOOTLOADER 2302 help 2303 Choose how the kernel will handle the provided default kernel 2304 command line string. 2305 2306config CMDLINE_FROM_BOOTLOADER 2307 bool "Use bootloader kernel arguments if available" 2308 help 2309 Uses the command-line options passed by the boot loader. If 2310 the boot loader doesn't provide any, the default kernel command 2311 string provided in CMDLINE will be used. 2312 2313config CMDLINE_EXTEND 2314 bool "Extend bootloader kernel arguments" 2315 help 2316 The command-line arguments provided by the boot loader will be 2317 appended to the default kernel command string. 2318 2319config CMDLINE_FORCE 2320 bool "Always use the default kernel command string" 2321 help 2322 Always use the default kernel command string, even if the boot 2323 loader passes other arguments to the kernel. 2324 This is useful if you cannot or don't want to change the 2325 command-line options your boot loader passes to the kernel. 2326 2327endchoice 2328 2329config EFI_STUB 2330 bool 2331 2332config EFI 2333 bool "UEFI runtime support" 2334 depends on OF && !CPU_BIG_ENDIAN 2335 depends on KERNEL_MODE_NEON 2336 select ARCH_SUPPORTS_ACPI 2337 select LIBFDT 2338 select UCS2_STRING 2339 select EFI_PARAMS_FROM_FDT 2340 select EFI_RUNTIME_WRAPPERS 2341 select EFI_STUB 2342 select EFI_GENERIC_STUB 2343 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2344 default y 2345 help 2346 This option provides support for runtime services provided 2347 by UEFI firmware (such as non-volatile variables, realtime 2348 clock, and platform reset). A UEFI stub is also provided to 2349 allow the kernel to be booted as an EFI application. This 2350 is only useful on systems that have UEFI firmware. 2351 2352config DMI 2353 bool "Enable support for SMBIOS (DMI) tables" 2354 depends on EFI 2355 default y 2356 help 2357 This enables SMBIOS/DMI feature for systems. 2358 2359 This option is only useful on systems that have UEFI firmware. 2360 However, even with this option, the resultant kernel should 2361 continue to boot on existing non-UEFI platforms. 2362 2363endmenu # "Boot options" 2364 2365menu "Power management options" 2366 2367source "kernel/power/Kconfig" 2368 2369config ARCH_HIBERNATION_POSSIBLE 2370 def_bool y 2371 depends on CPU_PM 2372 2373config ARCH_HIBERNATION_HEADER 2374 def_bool y 2375 depends on HIBERNATION 2376 2377config ARCH_SUSPEND_POSSIBLE 2378 def_bool y 2379 2380endmenu # "Power management options" 2381 2382menu "CPU Power Management" 2383 2384source "drivers/cpuidle/Kconfig" 2385 2386source "drivers/cpufreq/Kconfig" 2387 2388endmenu # "CPU Power Management" 2389 2390source "drivers/acpi/Kconfig" 2391 2392source "arch/arm64/kvm/Kconfig" 2393