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1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Support for Intel Camera Imaging ISP subsystem.
4  * Copyright (c) 2015, Intel Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  */
15 
16 #ifndef _if_subsystem_defs_h__
17 #define _if_subsystem_defs_h__
18 
19 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0            0
20 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_1            1
21 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_2            2
22 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_3            3
23 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_4            4
24 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_5            5
25 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_6            6
26 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_7            7
27 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_FSYNC_LUT_REG        8
28 #define HIVE_IFMT_GP_REGS_SRST_IDX                          9
29 #define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IDX                 10
30 
31 #define HIVE_IFMT_GP_REGS_CH_ID_FMT_TYPE_IDX               11
32 
33 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_BASE         HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0
34 
35 /* order of the input bits for the ifmt irq controller */
36 #define HIVE_IFMT_IRQ_IFT_PRIM_BIT_ID                       0
37 #define HIVE_IFMT_IRQ_IFT_PRIM_B_BIT_ID                     1
38 #define HIVE_IFMT_IRQ_IFT_SEC_BIT_ID                        2
39 #define HIVE_IFMT_IRQ_MEM_CPY_BIT_ID                        3
40 #define HIVE_IFMT_IRQ_SIDEBAND_CHANGED_BIT_ID               4
41 
42 /* order of the input bits for the ifmt Soft reset register */
43 #define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_BIT_IDX             0
44 #define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_B_BIT_IDX           1
45 #define HIVE_IFMT_GP_REGS_SRST_IFT_SEC_BIT_IDX              2
46 #define HIVE_IFMT_GP_REGS_SRST_MEM_CPY_BIT_IDX              3
47 
48 /* order of the input bits for the ifmt Soft reset register */
49 #define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_BIT_IDX     0
50 #define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_B_BIT_IDX   1
51 #define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_SEC_BIT_IDX      2
52 #define HIVE_IFMT_GP_REGS_SLV_REG_SRST_MEM_CPY_BIT_IDX      3
53 
54 #endif /* _if_subsystem_defs_h__ */
55