1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef __MLX5_CORE_H__
34 #define __MLX5_CORE_H__
35
36 #include <linux/types.h>
37 #include <linux/kernel.h>
38 #include <linux/sched.h>
39 #include <linux/if_link.h>
40 #include <linux/firmware.h>
41 #include <linux/mlx5/cq.h>
42 #include <linux/mlx5/fs.h>
43 #include <linux/mlx5/driver.h>
44
45 extern uint mlx5_core_debug_mask;
46
47 #define mlx5_core_dbg(__dev, format, ...) \
48 dev_dbg((__dev)->device, "%s:%d:(pid %d): " format, \
49 __func__, __LINE__, current->pid, \
50 ##__VA_ARGS__)
51
52 #define mlx5_core_dbg_once(__dev, format, ...) \
53 dev_dbg_once((__dev)->device, \
54 "%s:%d:(pid %d): " format, \
55 __func__, __LINE__, current->pid, \
56 ##__VA_ARGS__)
57
58 #define mlx5_core_dbg_mask(__dev, mask, format, ...) \
59 do { \
60 if ((mask) & mlx5_core_debug_mask) \
61 mlx5_core_dbg(__dev, format, ##__VA_ARGS__); \
62 } while (0)
63
64 #define mlx5_core_err(__dev, format, ...) \
65 dev_err((__dev)->device, "%s:%d:(pid %d): " format, \
66 __func__, __LINE__, current->pid, \
67 ##__VA_ARGS__)
68
69 #define mlx5_core_err_rl(__dev, format, ...) \
70 dev_err_ratelimited((__dev)->device, \
71 "%s:%d:(pid %d): " format, \
72 __func__, __LINE__, current->pid, \
73 ##__VA_ARGS__)
74
75 #define mlx5_core_warn(__dev, format, ...) \
76 dev_warn((__dev)->device, "%s:%d:(pid %d): " format, \
77 __func__, __LINE__, current->pid, \
78 ##__VA_ARGS__)
79
80 #define mlx5_core_warn_once(__dev, format, ...) \
81 dev_warn_once((__dev)->device, "%s:%d:(pid %d): " format, \
82 __func__, __LINE__, current->pid, \
83 ##__VA_ARGS__)
84
85 #define mlx5_core_warn_rl(__dev, format, ...) \
86 dev_warn_ratelimited((__dev)->device, \
87 "%s:%d:(pid %d): " format, \
88 __func__, __LINE__, current->pid, \
89 ##__VA_ARGS__)
90
91 #define mlx5_core_info(__dev, format, ...) \
92 dev_info((__dev)->device, format, ##__VA_ARGS__)
93
94 #define mlx5_core_info_rl(__dev, format, ...) \
95 dev_info_ratelimited((__dev)->device, \
96 "%s:%d:(pid %d): " format, \
97 __func__, __LINE__, current->pid, \
98 ##__VA_ARGS__)
99
mlx5_printk(struct mlx5_core_dev * dev,int level,const char * format,...)100 static inline void mlx5_printk(struct mlx5_core_dev *dev, int level, const char *format, ...)
101 {
102 struct device *device = dev->device;
103 struct va_format vaf;
104 va_list args;
105
106 if (WARN_ONCE(level < LOGLEVEL_EMERG || level > LOGLEVEL_DEBUG,
107 "Level %d is out of range, set to default level\n", level))
108 level = LOGLEVEL_DEFAULT;
109
110 va_start(args, format);
111 vaf.fmt = format;
112 vaf.va = &args;
113
114 dev_printk_emit(level, device, "%s %s: %pV", dev_driver_string(device), dev_name(device),
115 &vaf);
116 va_end(args);
117 }
118
119 #define mlx5_log(__dev, level, format, ...) \
120 mlx5_printk(__dev, level, "%s:%d:(pid %d): " format, \
121 __func__, __LINE__, current->pid, \
122 ##__VA_ARGS__)
123
mlx5_core_dma_dev(struct mlx5_core_dev * dev)124 static inline struct device *mlx5_core_dma_dev(struct mlx5_core_dev *dev)
125 {
126 return &dev->pdev->dev;
127 }
128
129 enum {
130 MLX5_CMD_DATA, /* print command payload only */
131 MLX5_CMD_TIME, /* print command execution time */
132 };
133
134 enum {
135 MLX5_DRIVER_STATUS_ABORTED = 0xfe,
136 MLX5_DRIVER_SYND = 0xbadd00de,
137 };
138
139 enum mlx5_semaphore_space_address {
140 MLX5_SEMAPHORE_SPACE_DOMAIN = 0xA,
141 MLX5_SEMAPHORE_SW_RESET = 0x20,
142 };
143
144 #define MLX5_DEFAULT_PROF 2
145 #define MLX5_SF_PROF 3
146
mlx5_flexible_inlen(struct mlx5_core_dev * dev,size_t fixed,size_t item_size,size_t num_items,const char * func,int line)147 static inline int mlx5_flexible_inlen(struct mlx5_core_dev *dev, size_t fixed,
148 size_t item_size, size_t num_items,
149 const char *func, int line)
150 {
151 int inlen;
152
153 if (fixed > INT_MAX || item_size > INT_MAX || num_items > INT_MAX) {
154 mlx5_core_err(dev, "%s: %s:%d: input values too big: %zu + %zu * %zu\n",
155 __func__, func, line, fixed, item_size, num_items);
156 return -ENOMEM;
157 }
158
159 if (check_mul_overflow((int)item_size, (int)num_items, &inlen)) {
160 mlx5_core_err(dev, "%s: %s:%d: multiplication overflow: %zu + %zu * %zu\n",
161 __func__, func, line, fixed, item_size, num_items);
162 return -ENOMEM;
163 }
164
165 if (check_add_overflow((int)fixed, inlen, &inlen)) {
166 mlx5_core_err(dev, "%s: %s:%d: addition overflow: %zu + %zu * %zu\n",
167 __func__, func, line, fixed, item_size, num_items);
168 return -ENOMEM;
169 }
170
171 return inlen;
172 }
173
174 #define MLX5_FLEXIBLE_INLEN(dev, fixed, item_size, num_items) \
175 mlx5_flexible_inlen(dev, fixed, item_size, num_items, __func__, __LINE__)
176
177 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
178 int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
179 enum mlx5_cap_mode cap_mode);
180 int mlx5_query_hca_caps(struct mlx5_core_dev *dev);
181 int mlx5_query_board_id(struct mlx5_core_dev *dev);
182 int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num);
183 int mlx5_cmd_init(struct mlx5_core_dev *dev);
184 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
185 int mlx5_cmd_enable(struct mlx5_core_dev *dev);
186 void mlx5_cmd_disable(struct mlx5_core_dev *dev);
187 void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
188 enum mlx5_cmdif_state cmdif_state);
189 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id);
190 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev);
191 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev);
192 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev);
193 void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force);
194 void mlx5_error_sw_reset(struct mlx5_core_dev *dev);
195 u32 mlx5_health_check_fatal_sensors(struct mlx5_core_dev *dev);
196 int mlx5_health_wait_pci_up(struct mlx5_core_dev *dev);
197 void mlx5_disable_device(struct mlx5_core_dev *dev);
198 int mlx5_recover_device(struct mlx5_core_dev *dev);
199 int mlx5_sriov_init(struct mlx5_core_dev *dev);
200 void mlx5_sriov_cleanup(struct mlx5_core_dev *dev);
201 int mlx5_sriov_attach(struct mlx5_core_dev *dev);
202 void mlx5_sriov_detach(struct mlx5_core_dev *dev);
203 int mlx5_core_sriov_configure(struct pci_dev *dev, int num_vfs);
204 void mlx5_sriov_disable(struct pci_dev *pdev, bool num_vf_change);
205 int mlx5_core_sriov_set_msix_vec_count(struct pci_dev *vf, int msix_vec_count);
206 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id);
207 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id);
208 int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
209 void *context, u32 *element_id);
210 int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
211 void *context, u32 element_id,
212 u32 modify_bitmask);
213 int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
214 u32 element_id);
215 int mlx5_wait_for_pages(struct mlx5_core_dev *dev, int *pages);
216
217 void mlx5_cmd_flush(struct mlx5_core_dev *dev);
218 void mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
219 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
220
221 int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
222 u8 access_reg_group);
223 int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap, u8 feature_group,
224 u8 access_reg_group);
225 int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
226 u8 feature_group, u8 access_reg_group);
227
228 void mlx5_lag_add_netdev(struct mlx5_core_dev *dev, struct net_device *netdev);
229 void mlx5_lag_remove_netdev(struct mlx5_core_dev *dev, struct net_device *netdev);
230 void mlx5_lag_add_mdev(struct mlx5_core_dev *dev);
231 void mlx5_lag_remove_mdev(struct mlx5_core_dev *dev);
232 void mlx5_lag_disable_change(struct mlx5_core_dev *dev);
233 void mlx5_lag_enable_change(struct mlx5_core_dev *dev);
234
235 int mlx5_events_init(struct mlx5_core_dev *dev);
236 void mlx5_events_cleanup(struct mlx5_core_dev *dev);
237 void mlx5_events_start(struct mlx5_core_dev *dev);
238 void mlx5_events_stop(struct mlx5_core_dev *dev);
239
240 int mlx5_adev_idx_alloc(void);
241 void mlx5_adev_idx_free(int idx);
242 void mlx5_adev_cleanup(struct mlx5_core_dev *dev);
243 int mlx5_adev_init(struct mlx5_core_dev *dev);
244
245 int mlx5_attach_device(struct mlx5_core_dev *dev);
246 void mlx5_detach_device(struct mlx5_core_dev *dev, bool suspend);
247 int mlx5_register_device(struct mlx5_core_dev *dev);
248 void mlx5_unregister_device(struct mlx5_core_dev *dev);
249 void mlx5_dev_set_lightweight(struct mlx5_core_dev *dev);
250 bool mlx5_dev_is_lightweight(struct mlx5_core_dev *dev);
251 struct mlx5_core_dev *mlx5_get_next_phys_dev_lag(struct mlx5_core_dev *dev);
252 void mlx5_dev_list_lock(void);
253 void mlx5_dev_list_unlock(void);
254 int mlx5_dev_list_trylock(void);
255
256 void mlx5_fw_reporters_create(struct mlx5_core_dev *dev);
257 int mlx5_query_mtpps(struct mlx5_core_dev *dev, u32 *mtpps, u32 mtpps_size);
258 int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size);
259 int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode);
260 int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode);
261
262 struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev);
263 void mlx5_dm_cleanup(struct mlx5_core_dev *dev);
264
265 #define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) && \
266 MLX5_CAP_GEN((mdev), pps_modify) && \
267 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_fs) && \
268 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_enh_out_per_adj))
269
270 int mlx5_firmware_flash(struct mlx5_core_dev *dev, const struct firmware *fw,
271 struct netlink_ext_ack *extack);
272 int mlx5_fw_version_query(struct mlx5_core_dev *dev,
273 u32 *running_ver, u32 *stored_ver);
274
275 #ifdef CONFIG_MLX5_CORE_EN
276 int mlx5e_init(void);
277 void mlx5e_cleanup(void);
278 #else
mlx5e_init(void)279 static inline int mlx5e_init(void){ return 0; }
mlx5e_cleanup(void)280 static inline void mlx5e_cleanup(void){}
281 #endif
282
mlx5_sriov_is_enabled(struct mlx5_core_dev * dev)283 static inline bool mlx5_sriov_is_enabled(struct mlx5_core_dev *dev)
284 {
285 return pci_num_vf(dev->pdev) ? true : false;
286 }
287
288 int mlx5_rescan_drivers_locked(struct mlx5_core_dev *dev);
mlx5_rescan_drivers(struct mlx5_core_dev * dev)289 static inline int mlx5_rescan_drivers(struct mlx5_core_dev *dev)
290 {
291 int ret;
292
293 mlx5_dev_list_lock();
294 ret = mlx5_rescan_drivers_locked(dev);
295 mlx5_dev_list_unlock();
296 return ret;
297 }
298
299 void mlx5_lag_update(struct mlx5_core_dev *dev);
300
301 enum {
302 MLX5_NIC_IFC_FULL = 0,
303 MLX5_NIC_IFC_DISABLED = 1,
304 MLX5_NIC_IFC_NO_DRAM_NIC = 2,
305 MLX5_NIC_IFC_SW_RESET = 7
306 };
307
308 u8 mlx5_get_nic_state(struct mlx5_core_dev *dev);
309 void mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state);
310
mlx5_core_is_sf(const struct mlx5_core_dev * dev)311 static inline bool mlx5_core_is_sf(const struct mlx5_core_dev *dev)
312 {
313 return dev->coredev_type == MLX5_COREDEV_SF;
314 }
315
316 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx);
317 void mlx5_mdev_uninit(struct mlx5_core_dev *dev);
318 int mlx5_init_one(struct mlx5_core_dev *dev);
319 int mlx5_init_one_devl_locked(struct mlx5_core_dev *dev);
320 void mlx5_uninit_one(struct mlx5_core_dev *dev);
321 void mlx5_unload_one(struct mlx5_core_dev *dev, bool suspend);
322 void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev, bool suspend);
323 int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery);
324 int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery);
325 int mlx5_init_one_light(struct mlx5_core_dev *dev);
326 void mlx5_uninit_one_light(struct mlx5_core_dev *dev);
327 void mlx5_unload_one_light(struct mlx5_core_dev *dev);
328
329 int mlx5_vport_set_other_func_cap(struct mlx5_core_dev *dev, const void *hca_cap, u16 vport,
330 u16 opmod);
331 #define mlx5_vport_get_other_func_general_cap(dev, vport, out) \
332 mlx5_vport_get_other_func_cap(dev, vport, out, MLX5_CAP_GENERAL)
333
334 void mlx5_events_work_enqueue(struct mlx5_core_dev *dev, struct work_struct *work);
mlx5_sriov_get_vf_total_msix(struct pci_dev * pdev)335 static inline u32 mlx5_sriov_get_vf_total_msix(struct pci_dev *pdev)
336 {
337 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
338
339 return MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix);
340 }
341
342 bool mlx5_eth_supported(struct mlx5_core_dev *dev);
343 bool mlx5_rdma_supported(struct mlx5_core_dev *dev);
344 bool mlx5_vnet_supported(struct mlx5_core_dev *dev);
345 bool mlx5_same_hw_devs(struct mlx5_core_dev *dev, struct mlx5_core_dev *peer_dev);
346
mlx5_core_ec_vf_vport_base(const struct mlx5_core_dev * dev)347 static inline u16 mlx5_core_ec_vf_vport_base(const struct mlx5_core_dev *dev)
348 {
349 return MLX5_CAP_GEN_2(dev, ec_vf_vport_base);
350 }
351
mlx5_core_ec_sriov_enabled(const struct mlx5_core_dev * dev)352 static inline u16 mlx5_core_ec_sriov_enabled(const struct mlx5_core_dev *dev)
353 {
354 return mlx5_core_is_ecpf(dev) && mlx5_core_ec_vf_vport_base(dev);
355 }
356
mlx5_core_is_ec_vf_vport(const struct mlx5_core_dev * dev,u16 vport_num)357 static inline bool mlx5_core_is_ec_vf_vport(const struct mlx5_core_dev *dev, u16 vport_num)
358 {
359 int base_vport = mlx5_core_ec_vf_vport_base(dev);
360 int max_vport = base_vport + mlx5_core_max_ec_vfs(dev);
361
362 if (!mlx5_core_ec_sriov_enabled(dev))
363 return false;
364
365 return (vport_num >= base_vport && vport_num < max_vport);
366 }
367
mlx5_vport_to_func_id(const struct mlx5_core_dev * dev,u16 vport,bool ec_vf_func)368 static inline int mlx5_vport_to_func_id(const struct mlx5_core_dev *dev, u16 vport, bool ec_vf_func)
369 {
370 return ec_vf_func ? vport - mlx5_core_ec_vf_vport_base(dev) + 1
371 : vport;
372 }
373
374 #endif /* __MLX5_CORE_H__ */
375