1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V4_20_H_ 7 #define QCOM_PHY_QMP_QSERDES_TXRX_V4_20_H_ 8 9 /* Only for QMP V4_20 PHY - TX registers */ 10 #define QSERDES_V4_20_TX_LANE_MODE_1 0x88 11 #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c 12 #define QSERDES_V4_20_TX_LANE_MODE_3 0x90 13 #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4 14 #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0 15 16 /* Only for QMP V4_20 PHY - RX registers */ 17 #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008 18 #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058 19 #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac 20 #define QSERDES_V4_20_RX_DFE_3 0x110 21 #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134 22 #define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138 23 #define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150 24 #define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178 25 #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8 26 #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc 27 #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0 28 #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4 29 #define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8 30 #define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc 31 #define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0 32 #define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4 33 #define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8 34 #define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec 35 #define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0 36 #define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4 37 #define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8 38 #define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc 39 #define QSERDES_V4_20_RX_PHPRE_CTRL 0x200 40 #define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c 41 #define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c 42 43 #endif 44