1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copied from arch/arm64/include/asm/hwcap.h
4 *
5 * Copyright (C) 2012 ARM Ltd.
6 * Copyright (C) 2017 SiFive
7 */
8 #ifndef _ASM_RISCV_HWCAP_H
9 #define _ASM_RISCV_HWCAP_H
10
11 #include <asm/alternative-macros.h>
12 #include <asm/errno.h>
13 #include <linux/bits.h>
14 #include <uapi/asm/hwcap.h>
15
16 #define RISCV_ISA_EXT_a ('a' - 'a')
17 #define RISCV_ISA_EXT_b ('b' - 'a')
18 #define RISCV_ISA_EXT_c ('c' - 'a')
19 #define RISCV_ISA_EXT_d ('d' - 'a')
20 #define RISCV_ISA_EXT_f ('f' - 'a')
21 #define RISCV_ISA_EXT_h ('h' - 'a')
22 #define RISCV_ISA_EXT_i ('i' - 'a')
23 #define RISCV_ISA_EXT_j ('j' - 'a')
24 #define RISCV_ISA_EXT_k ('k' - 'a')
25 #define RISCV_ISA_EXT_m ('m' - 'a')
26 #define RISCV_ISA_EXT_p ('p' - 'a')
27 #define RISCV_ISA_EXT_q ('q' - 'a')
28 #define RISCV_ISA_EXT_s ('s' - 'a')
29 #define RISCV_ISA_EXT_u ('u' - 'a')
30 #define RISCV_ISA_EXT_v ('v' - 'a')
31
32 /*
33 * These macros represent the logical IDs of each multi-letter RISC-V ISA
34 * extension and are used in the ISA bitmap. The logical IDs start from
35 * RISCV_ISA_EXT_BASE, which allows the 0-25 range to be reserved for single
36 * letter extensions. The maximum, RISCV_ISA_EXT_MAX, is defined in order
37 * to allocate the bitmap and may be increased when necessary.
38 *
39 * New extensions should just be added to the bottom, rather than added
40 * alphabetically, in order to avoid unnecessary shuffling.
41 */
42 #define RISCV_ISA_EXT_BASE 26
43
44 #define RISCV_ISA_EXT_SSCOFPMF 26
45 #define RISCV_ISA_EXT_SSTC 27
46 #define RISCV_ISA_EXT_SVINVAL 28
47 #define RISCV_ISA_EXT_SVPBMT 29
48 #define RISCV_ISA_EXT_ZBB 30
49 #define RISCV_ISA_EXT_ZICBOM 31
50 #define RISCV_ISA_EXT_ZIHINTPAUSE 32
51 #define RISCV_ISA_EXT_SVNAPOT 33
52 #define RISCV_ISA_EXT_ZICBOZ 34
53 #define RISCV_ISA_EXT_SMAIA 35
54 #define RISCV_ISA_EXT_SSAIA 36
55 #define RISCV_ISA_EXT_ZBA 37
56 #define RISCV_ISA_EXT_ZBS 38
57 #define RISCV_ISA_EXT_ZICNTR 39
58 #define RISCV_ISA_EXT_ZICSR 40
59 #define RISCV_ISA_EXT_ZIFENCEI 41
60 #define RISCV_ISA_EXT_ZIHPM 42
61 #define RISCV_ISA_EXT_SMSTATEEN 43
62 #define RISCV_ISA_EXT_ZICOND 44
63 #define RISCV_ISA_EXT_ZBC 45
64 #define RISCV_ISA_EXT_ZBKB 46
65 #define RISCV_ISA_EXT_ZBKC 47
66 #define RISCV_ISA_EXT_ZBKX 48
67 #define RISCV_ISA_EXT_ZKND 49
68 #define RISCV_ISA_EXT_ZKNE 50
69 #define RISCV_ISA_EXT_ZKNH 51
70 #define RISCV_ISA_EXT_ZKR 52
71 #define RISCV_ISA_EXT_ZKSED 53
72 #define RISCV_ISA_EXT_ZKSH 54
73 #define RISCV_ISA_EXT_ZKT 55
74 #define RISCV_ISA_EXT_ZVBB 56
75 #define RISCV_ISA_EXT_ZVBC 57
76 #define RISCV_ISA_EXT_ZVKB 58
77 #define RISCV_ISA_EXT_ZVKG 59
78 #define RISCV_ISA_EXT_ZVKNED 60
79 #define RISCV_ISA_EXT_ZVKNHA 61
80 #define RISCV_ISA_EXT_ZVKNHB 62
81 #define RISCV_ISA_EXT_ZVKSED 63
82 #define RISCV_ISA_EXT_ZVKSH 64
83 #define RISCV_ISA_EXT_ZVKT 65
84
85 #define RISCV_ISA_EXT_MAX 128
86 #define RISCV_ISA_EXT_INVALID U32_MAX
87
88 #ifdef CONFIG_RISCV_M_MODE
89 #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA
90 #else
91 #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA
92 #endif
93
94 #ifndef __ASSEMBLY__
95
96 #include <linux/jump_label.h>
97
98 unsigned long riscv_get_elf_hwcap(void);
99
100 struct riscv_isa_ext_data {
101 const unsigned int id;
102 const char *name;
103 const char *property;
104 const unsigned int *subset_ext_ids;
105 const unsigned int subset_ext_size;
106 };
107
108 extern const struct riscv_isa_ext_data riscv_isa_ext[];
109 extern const size_t riscv_isa_ext_count;
110 extern bool riscv_isa_fallback;
111
112 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
113
114 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
115
116 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsigned int bit);
117 #define riscv_isa_extension_available(isa_bitmap, ext) \
118 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
119
120 static __always_inline bool
riscv_has_extension_likely(const unsigned long ext)121 riscv_has_extension_likely(const unsigned long ext)
122 {
123 compiletime_assert(ext < RISCV_ISA_EXT_MAX,
124 "ext must be < RISCV_ISA_EXT_MAX");
125
126 if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
127 asm goto(
128 ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1)
129 :
130 : [ext] "i" (ext)
131 :
132 : l_no);
133 } else {
134 if (!__riscv_isa_extension_available(NULL, ext))
135 goto l_no;
136 }
137
138 return true;
139 l_no:
140 return false;
141 }
142
143 static __always_inline bool
riscv_has_extension_unlikely(const unsigned long ext)144 riscv_has_extension_unlikely(const unsigned long ext)
145 {
146 compiletime_assert(ext < RISCV_ISA_EXT_MAX,
147 "ext must be < RISCV_ISA_EXT_MAX");
148
149 if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
150 asm goto(
151 ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1)
152 :
153 : [ext] "i" (ext)
154 :
155 : l_yes);
156 } else {
157 if (__riscv_isa_extension_available(NULL, ext))
158 goto l_yes;
159 }
160
161 return false;
162 l_yes:
163 return true;
164 }
165
166 #endif
167
168 #endif /* _ASM_RISCV_HWCAP_H */
169