1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_CORE_H__
6 #define __RTW89_CORE_H__
7
8 #include <linux/average.h>
9 #include <linux/bitfield.h>
10 #include <linux/firmware.h>
11 #include <linux/iopoll.h>
12 #include <linux/workqueue.h>
13 #include <net/mac80211.h>
14
15 struct rtw89_dev;
16 struct rtw89_pci_info;
17 struct rtw89_mac_gen_def;
18 struct rtw89_phy_gen_def;
19
20 extern const struct ieee80211_ops rtw89_ops;
21
22 #define MASKBYTE0 0xff
23 #define MASKBYTE1 0xff00
24 #define MASKBYTE2 0xff0000
25 #define MASKBYTE3 0xff000000
26 #define MASKBYTE4 0xff00000000ULL
27 #define MASKHWORD 0xffff0000
28 #define MASKLWORD 0x0000ffff
29 #define MASKDWORD 0xffffffff
30 #define RFREG_MASK 0xfffff
31 #define INV_RF_DATA 0xffffffff
32
33 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2)
34 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4)
35 #define CFO_TRACK_MAX_USER 64
36 #define MAX_RSSI 110
37 #define RSSI_FACTOR 1
38 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
39 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR)
40 #define RTW89_RADIOTAP_ROOM ALIGN(sizeof(struct ieee80211_radiotap_he), 64)
41
42 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
43 #define RTW89_HTC_VARIANT_HE 3
44 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2)
45 #define RTW89_HTC_VARIANT_HE_CID_OM 1
46 #define RTW89_HTC_VARIANT_HE_CID_CAS 6
47 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6)
48
49 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6)
50 enum htc_om_channel_width {
51 HTC_OM_CHANNEL_WIDTH_20 = 0,
52 HTC_OM_CHANNEL_WIDTH_40 = 1,
53 HTC_OM_CHANNEL_WIDTH_80 = 2,
54 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3,
55 };
56 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9)
57 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11)
58 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12)
59 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15)
60 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16)
61 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17)
62
63 #define RTW89_TF_PAD GENMASK(11, 0)
64 #define RTW89_TF_BASIC_USER_INFO_SZ 6
65
66 #define RTW89_GET_TF_USER_INFO_AID12(data) \
67 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0))
68 #define RTW89_GET_TF_USER_INFO_RUA(data) \
69 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12))
70 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \
71 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21))
72
73 enum rtw89_subband {
74 RTW89_CH_2G = 0,
75 RTW89_CH_5G_BAND_1 = 1,
76 /* RTW89_CH_5G_BAND_2 = 2, unused */
77 RTW89_CH_5G_BAND_3 = 3,
78 RTW89_CH_5G_BAND_4 = 4,
79
80 RTW89_CH_6G_BAND_IDX0, /* Low */
81 RTW89_CH_6G_BAND_IDX1, /* Low */
82 RTW89_CH_6G_BAND_IDX2, /* Mid */
83 RTW89_CH_6G_BAND_IDX3, /* Mid */
84 RTW89_CH_6G_BAND_IDX4, /* High */
85 RTW89_CH_6G_BAND_IDX5, /* High */
86 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
87 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
88
89 RTW89_SUBBAND_NR,
90 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1,
91 };
92
93 enum rtw89_gain_offset {
94 RTW89_GAIN_OFFSET_2G_CCK,
95 RTW89_GAIN_OFFSET_2G_OFDM,
96 RTW89_GAIN_OFFSET_5G_LOW,
97 RTW89_GAIN_OFFSET_5G_MID,
98 RTW89_GAIN_OFFSET_5G_HIGH,
99
100 RTW89_GAIN_OFFSET_NR,
101 };
102
103 enum rtw89_hci_type {
104 RTW89_HCI_TYPE_PCIE,
105 RTW89_HCI_TYPE_USB,
106 RTW89_HCI_TYPE_SDIO,
107 };
108
109 enum rtw89_core_chip_id {
110 RTL8852A,
111 RTL8852B,
112 RTL8852C,
113 RTL8851B,
114 RTL8922A,
115 };
116
117 enum rtw89_chip_gen {
118 RTW89_CHIP_AX,
119 RTW89_CHIP_BE,
120
121 RTW89_CHIP_GEN_NUM,
122 };
123
124 enum rtw89_cv {
125 CHIP_CAV,
126 CHIP_CBV,
127 CHIP_CCV,
128 CHIP_CDV,
129 CHIP_CEV,
130 CHIP_CFV,
131 CHIP_CV_MAX,
132 CHIP_CV_INVALID = CHIP_CV_MAX,
133 };
134
135 enum rtw89_bacam_ver {
136 RTW89_BACAM_V0,
137 RTW89_BACAM_V1,
138
139 RTW89_BACAM_V0_EXT = 99,
140 };
141
142 enum rtw89_core_tx_type {
143 RTW89_CORE_TX_TYPE_DATA,
144 RTW89_CORE_TX_TYPE_MGMT,
145 RTW89_CORE_TX_TYPE_FWCMD,
146 };
147
148 enum rtw89_core_rx_type {
149 RTW89_CORE_RX_TYPE_WIFI = 0,
150 RTW89_CORE_RX_TYPE_PPDU_STAT = 1,
151 RTW89_CORE_RX_TYPE_CHAN_INFO = 2,
152 RTW89_CORE_RX_TYPE_BB_SCOPE = 3,
153 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4,
154 RTW89_CORE_RX_TYPE_SS2FW = 5,
155 RTW89_CORE_RX_TYPE_TX_REPORT = 6,
156 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7,
157 RTW89_CORE_RX_TYPE_DFS_REPORT = 8,
158 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9,
159 RTW89_CORE_RX_TYPE_C2H = 10,
160 RTW89_CORE_RX_TYPE_CSI = 11,
161 RTW89_CORE_RX_TYPE_CQI = 12,
162 RTW89_CORE_RX_TYPE_H2C = 13,
163 RTW89_CORE_RX_TYPE_FWDL = 14,
164 };
165
166 enum rtw89_txq_flags {
167 RTW89_TXQ_F_AMPDU = 0,
168 RTW89_TXQ_F_BLOCK_BA = 1,
169 RTW89_TXQ_F_FORBID_BA = 2,
170 };
171
172 enum rtw89_net_type {
173 RTW89_NET_TYPE_NO_LINK = 0,
174 RTW89_NET_TYPE_AD_HOC = 1,
175 RTW89_NET_TYPE_INFRA = 2,
176 RTW89_NET_TYPE_AP_MODE = 3,
177 };
178
179 enum rtw89_wifi_role {
180 RTW89_WIFI_ROLE_NONE,
181 RTW89_WIFI_ROLE_STATION,
182 RTW89_WIFI_ROLE_AP,
183 RTW89_WIFI_ROLE_AP_VLAN,
184 RTW89_WIFI_ROLE_ADHOC,
185 RTW89_WIFI_ROLE_ADHOC_MASTER,
186 RTW89_WIFI_ROLE_MESH_POINT,
187 RTW89_WIFI_ROLE_MONITOR,
188 RTW89_WIFI_ROLE_P2P_DEVICE,
189 RTW89_WIFI_ROLE_P2P_CLIENT,
190 RTW89_WIFI_ROLE_P2P_GO,
191 RTW89_WIFI_ROLE_NAN,
192 RTW89_WIFI_ROLE_MLME_MAX
193 };
194
195 enum rtw89_upd_mode {
196 RTW89_ROLE_CREATE,
197 RTW89_ROLE_REMOVE,
198 RTW89_ROLE_TYPE_CHANGE,
199 RTW89_ROLE_INFO_CHANGE,
200 RTW89_ROLE_CON_DISCONN,
201 RTW89_ROLE_BAND_SW,
202 RTW89_ROLE_FW_RESTORE,
203 };
204
205 enum rtw89_self_role {
206 RTW89_SELF_ROLE_CLIENT,
207 RTW89_SELF_ROLE_AP,
208 RTW89_SELF_ROLE_AP_CLIENT
209 };
210
211 enum rtw89_msk_sO_el {
212 RTW89_NO_MSK,
213 RTW89_SMA,
214 RTW89_TMA,
215 RTW89_BSSID
216 };
217
218 enum rtw89_sch_tx_sel {
219 RTW89_SCH_TX_SEL_ALL,
220 RTW89_SCH_TX_SEL_HIQ,
221 RTW89_SCH_TX_SEL_MG0,
222 RTW89_SCH_TX_SEL_MACID,
223 };
224
225 /* RTW89_ADDR_CAM_SEC_NONE : not enabled
226 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast
227 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
228 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP
229 */
230 enum rtw89_add_cam_sec_mode {
231 RTW89_ADDR_CAM_SEC_NONE = 0,
232 RTW89_ADDR_CAM_SEC_ALL_UNI = 1,
233 RTW89_ADDR_CAM_SEC_NORMAL = 2,
234 RTW89_ADDR_CAM_SEC_4GROUP = 3,
235 };
236
237 enum rtw89_sec_key_type {
238 RTW89_SEC_KEY_TYPE_NONE = 0,
239 RTW89_SEC_KEY_TYPE_WEP40 = 1,
240 RTW89_SEC_KEY_TYPE_WEP104 = 2,
241 RTW89_SEC_KEY_TYPE_TKIP = 3,
242 RTW89_SEC_KEY_TYPE_WAPI = 4,
243 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5,
244 RTW89_SEC_KEY_TYPE_CCMP128 = 6,
245 RTW89_SEC_KEY_TYPE_CCMP256 = 7,
246 RTW89_SEC_KEY_TYPE_GCMP128 = 8,
247 RTW89_SEC_KEY_TYPE_GCMP256 = 9,
248 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10,
249 };
250
251 enum rtw89_port {
252 RTW89_PORT_0 = 0,
253 RTW89_PORT_1 = 1,
254 RTW89_PORT_2 = 2,
255 RTW89_PORT_3 = 3,
256 RTW89_PORT_4 = 4,
257 RTW89_PORT_NUM
258 };
259
260 enum rtw89_band {
261 RTW89_BAND_2G = 0,
262 RTW89_BAND_5G = 1,
263 RTW89_BAND_6G = 2,
264 RTW89_BAND_NUM,
265 };
266
267 enum rtw89_hw_rate {
268 RTW89_HW_RATE_CCK1 = 0x0,
269 RTW89_HW_RATE_CCK2 = 0x1,
270 RTW89_HW_RATE_CCK5_5 = 0x2,
271 RTW89_HW_RATE_CCK11 = 0x3,
272 RTW89_HW_RATE_OFDM6 = 0x4,
273 RTW89_HW_RATE_OFDM9 = 0x5,
274 RTW89_HW_RATE_OFDM12 = 0x6,
275 RTW89_HW_RATE_OFDM18 = 0x7,
276 RTW89_HW_RATE_OFDM24 = 0x8,
277 RTW89_HW_RATE_OFDM36 = 0x9,
278 RTW89_HW_RATE_OFDM48 = 0xA,
279 RTW89_HW_RATE_OFDM54 = 0xB,
280 RTW89_HW_RATE_MCS0 = 0x80,
281 RTW89_HW_RATE_MCS1 = 0x81,
282 RTW89_HW_RATE_MCS2 = 0x82,
283 RTW89_HW_RATE_MCS3 = 0x83,
284 RTW89_HW_RATE_MCS4 = 0x84,
285 RTW89_HW_RATE_MCS5 = 0x85,
286 RTW89_HW_RATE_MCS6 = 0x86,
287 RTW89_HW_RATE_MCS7 = 0x87,
288 RTW89_HW_RATE_MCS8 = 0x88,
289 RTW89_HW_RATE_MCS9 = 0x89,
290 RTW89_HW_RATE_MCS10 = 0x8A,
291 RTW89_HW_RATE_MCS11 = 0x8B,
292 RTW89_HW_RATE_MCS12 = 0x8C,
293 RTW89_HW_RATE_MCS13 = 0x8D,
294 RTW89_HW_RATE_MCS14 = 0x8E,
295 RTW89_HW_RATE_MCS15 = 0x8F,
296 RTW89_HW_RATE_MCS16 = 0x90,
297 RTW89_HW_RATE_MCS17 = 0x91,
298 RTW89_HW_RATE_MCS18 = 0x92,
299 RTW89_HW_RATE_MCS19 = 0x93,
300 RTW89_HW_RATE_MCS20 = 0x94,
301 RTW89_HW_RATE_MCS21 = 0x95,
302 RTW89_HW_RATE_MCS22 = 0x96,
303 RTW89_HW_RATE_MCS23 = 0x97,
304 RTW89_HW_RATE_MCS24 = 0x98,
305 RTW89_HW_RATE_MCS25 = 0x99,
306 RTW89_HW_RATE_MCS26 = 0x9A,
307 RTW89_HW_RATE_MCS27 = 0x9B,
308 RTW89_HW_RATE_MCS28 = 0x9C,
309 RTW89_HW_RATE_MCS29 = 0x9D,
310 RTW89_HW_RATE_MCS30 = 0x9E,
311 RTW89_HW_RATE_MCS31 = 0x9F,
312 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100,
313 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101,
314 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102,
315 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103,
316 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104,
317 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105,
318 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106,
319 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107,
320 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108,
321 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109,
322 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110,
323 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111,
324 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112,
325 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113,
326 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114,
327 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115,
328 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116,
329 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117,
330 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118,
331 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119,
332 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120,
333 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121,
334 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122,
335 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123,
336 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124,
337 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125,
338 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126,
339 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127,
340 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128,
341 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129,
342 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130,
343 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131,
344 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132,
345 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133,
346 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134,
347 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135,
348 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136,
349 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137,
350 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138,
351 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139,
352 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180,
353 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181,
354 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182,
355 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183,
356 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184,
357 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185,
358 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186,
359 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187,
360 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188,
361 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189,
362 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A,
363 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B,
364 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190,
365 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191,
366 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192,
367 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193,
368 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194,
369 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195,
370 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196,
371 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197,
372 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198,
373 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199,
374 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A,
375 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B,
376 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0,
377 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1,
378 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2,
379 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3,
380 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4,
381 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5,
382 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6,
383 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7,
384 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8,
385 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9,
386 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA,
387 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB,
388 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0,
389 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1,
390 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2,
391 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3,
392 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4,
393 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5,
394 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6,
395 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7,
396 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8,
397 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9,
398 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA,
399 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB,
400
401 RTW89_HW_RATE_V1_MCS0 = 0x100,
402 RTW89_HW_RATE_V1_MCS1 = 0x101,
403 RTW89_HW_RATE_V1_MCS2 = 0x102,
404 RTW89_HW_RATE_V1_MCS3 = 0x103,
405 RTW89_HW_RATE_V1_MCS4 = 0x104,
406 RTW89_HW_RATE_V1_MCS5 = 0x105,
407 RTW89_HW_RATE_V1_MCS6 = 0x106,
408 RTW89_HW_RATE_V1_MCS7 = 0x107,
409 RTW89_HW_RATE_V1_MCS8 = 0x108,
410 RTW89_HW_RATE_V1_MCS9 = 0x109,
411 RTW89_HW_RATE_V1_MCS10 = 0x10A,
412 RTW89_HW_RATE_V1_MCS11 = 0x10B,
413 RTW89_HW_RATE_V1_MCS12 = 0x10C,
414 RTW89_HW_RATE_V1_MCS13 = 0x10D,
415 RTW89_HW_RATE_V1_MCS14 = 0x10E,
416 RTW89_HW_RATE_V1_MCS15 = 0x10F,
417 RTW89_HW_RATE_V1_MCS16 = 0x110,
418 RTW89_HW_RATE_V1_MCS17 = 0x111,
419 RTW89_HW_RATE_V1_MCS18 = 0x112,
420 RTW89_HW_RATE_V1_MCS19 = 0x113,
421 RTW89_HW_RATE_V1_MCS20 = 0x114,
422 RTW89_HW_RATE_V1_MCS21 = 0x115,
423 RTW89_HW_RATE_V1_MCS22 = 0x116,
424 RTW89_HW_RATE_V1_MCS23 = 0x117,
425 RTW89_HW_RATE_V1_MCS24 = 0x118,
426 RTW89_HW_RATE_V1_MCS25 = 0x119,
427 RTW89_HW_RATE_V1_MCS26 = 0x11A,
428 RTW89_HW_RATE_V1_MCS27 = 0x11B,
429 RTW89_HW_RATE_V1_MCS28 = 0x11C,
430 RTW89_HW_RATE_V1_MCS29 = 0x11D,
431 RTW89_HW_RATE_V1_MCS30 = 0x11E,
432 RTW89_HW_RATE_V1_MCS31 = 0x11F,
433 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200,
434 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201,
435 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202,
436 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203,
437 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204,
438 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205,
439 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206,
440 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207,
441 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208,
442 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209,
443 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A,
444 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B,
445 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220,
446 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221,
447 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222,
448 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223,
449 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224,
450 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225,
451 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226,
452 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227,
453 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228,
454 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229,
455 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A,
456 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B,
457 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240,
458 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241,
459 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242,
460 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243,
461 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244,
462 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245,
463 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246,
464 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247,
465 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248,
466 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249,
467 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A,
468 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B,
469 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260,
470 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261,
471 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262,
472 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263,
473 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264,
474 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265,
475 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266,
476 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267,
477 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268,
478 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269,
479 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A,
480 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B,
481 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300,
482 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301,
483 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302,
484 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303,
485 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304,
486 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305,
487 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306,
488 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307,
489 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308,
490 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309,
491 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A,
492 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B,
493 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320,
494 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321,
495 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322,
496 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323,
497 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324,
498 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325,
499 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326,
500 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327,
501 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328,
502 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329,
503 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A,
504 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B,
505 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340,
506 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341,
507 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342,
508 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343,
509 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344,
510 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345,
511 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346,
512 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347,
513 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348,
514 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349,
515 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A,
516 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B,
517 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360,
518 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361,
519 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362,
520 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363,
521 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364,
522 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365,
523 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366,
524 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367,
525 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368,
526 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369,
527 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A,
528 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B,
529 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400,
530 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401,
531 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402,
532 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403,
533 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404,
534 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405,
535 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406,
536 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407,
537 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408,
538 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409,
539 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A,
540 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B,
541 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C,
542 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D,
543 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E,
544 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F,
545 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420,
546 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421,
547 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422,
548 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423,
549 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424,
550 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425,
551 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426,
552 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427,
553 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428,
554 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429,
555 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A,
556 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B,
557 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C,
558 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D,
559 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440,
560 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441,
561 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442,
562 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443,
563 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444,
564 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445,
565 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446,
566 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447,
567 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448,
568 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449,
569 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A,
570 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B,
571 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C,
572 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D,
573 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460,
574 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461,
575 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462,
576 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463,
577 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464,
578 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465,
579 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466,
580 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467,
581 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468,
582 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469,
583 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A,
584 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B,
585 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C,
586 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D,
587
588 RTW89_HW_RATE_NR,
589 RTW89_HW_RATE_INVAL,
590
591 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7),
592 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),
593 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8),
594 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0),
595 };
596
597 /* 2G channels,
598 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
599 */
600 #define RTW89_2G_CH_NUM 14
601
602 /* 5G channels,
603 * 36, 38, 40, 42, 44, 46, 48, 50,
604 * 52, 54, 56, 58, 60, 62, 64,
605 * 100, 102, 104, 106, 108, 110, 112, 114,
606 * 116, 118, 120, 122, 124, 126, 128, 130,
607 * 132, 134, 136, 138, 140, 142, 144,
608 * 149, 151, 153, 155, 157, 159, 161, 163,
609 * 165, 167, 169, 171, 173, 175, 177
610 */
611 #define RTW89_5G_CH_NUM 53
612
613 /* 6G channels,
614 * 1, 3, 5, 7, 9, 11, 13, 15,
615 * 17, 19, 21, 23, 25, 27, 29, 33,
616 * 35, 37, 39, 41, 43, 45, 47, 49,
617 * 51, 53, 55, 57, 59, 61, 65, 67,
618 * 69, 71, 73, 75, 77, 79, 81, 83,
619 * 85, 87, 89, 91, 93, 97, 99, 101,
620 * 103, 105, 107, 109, 111, 113, 115, 117,
621 * 119, 121, 123, 125, 129, 131, 133, 135,
622 * 137, 139, 141, 143, 145, 147, 149, 151,
623 * 153, 155, 157, 161, 163, 165, 167, 169,
624 * 171, 173, 175, 177, 179, 181, 183, 185,
625 * 187, 189, 193, 195, 197, 199, 201, 203,
626 * 205, 207, 209, 211, 213, 215, 217, 219,
627 * 221, 225, 227, 229, 231, 233, 235, 237,
628 * 239, 241, 243, 245, 247, 249, 251, 253,
629 */
630 #define RTW89_6G_CH_NUM 120
631
632 enum rtw89_rate_section {
633 RTW89_RS_CCK,
634 RTW89_RS_OFDM,
635 RTW89_RS_MCS, /* for HT/VHT/HE */
636 RTW89_RS_HEDCM,
637 RTW89_RS_OFFSET,
638 RTW89_RS_NUM,
639 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1,
640 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1,
641 };
642
643 enum rtw89_rate_num {
644 RTW89_RATE_CCK_NUM = 4,
645 RTW89_RATE_OFDM_NUM = 8,
646 RTW89_RATE_MCS_NUM = 12,
647 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */
648 RTW89_RATE_OFFSET_NUM = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */
649 };
650
651 enum rtw89_nss {
652 RTW89_NSS_1 = 0,
653 RTW89_NSS_2 = 1,
654 /* HE DCM only support 1ss and 2ss */
655 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1,
656 RTW89_NSS_3 = 2,
657 RTW89_NSS_4 = 3,
658 RTW89_NSS_NUM,
659 };
660
661 enum rtw89_ntx {
662 RTW89_1TX = 0,
663 RTW89_2TX = 1,
664 RTW89_NTX_NUM,
665 };
666
667 enum rtw89_beamforming_type {
668 RTW89_NONBF = 0,
669 RTW89_BF = 1,
670 RTW89_BF_NUM,
671 };
672
673 enum rtw89_regulation_type {
674 RTW89_WW = 0,
675 RTW89_ETSI = 1,
676 RTW89_FCC = 2,
677 RTW89_MKK = 3,
678 RTW89_NA = 4,
679 RTW89_IC = 5,
680 RTW89_KCC = 6,
681 RTW89_ACMA = 7,
682 RTW89_NCC = 8,
683 RTW89_MEXICO = 9,
684 RTW89_CHILE = 10,
685 RTW89_UKRAINE = 11,
686 RTW89_CN = 12,
687 RTW89_QATAR = 13,
688 RTW89_UK = 14,
689 RTW89_REGD_NUM,
690 };
691
692 enum rtw89_reg_6ghz_power {
693 RTW89_REG_6GHZ_POWER_VLP = 0,
694 RTW89_REG_6GHZ_POWER_LPI = 1,
695 RTW89_REG_6GHZ_POWER_STD = 2,
696
697 NUM_OF_RTW89_REG_6GHZ_POWER,
698 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP,
699 };
700
701 enum rtw89_fw_pkt_ofld_type {
702 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0,
703 RTW89_PKT_OFLD_TYPE_PS_POLL = 1,
704 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2,
705 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3,
706 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4,
707 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5,
708 RTW89_PKT_OFLD_TYPE_NDP = 6,
709 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7,
710 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8,
711 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12,
712 RTW89_PKT_OFLD_TYPE_NUM,
713 };
714
715 struct rtw89_txpwr_byrate {
716 s8 cck[RTW89_RATE_CCK_NUM];
717 s8 ofdm[RTW89_RATE_OFDM_NUM];
718 s8 mcs[RTW89_NSS_NUM][RTW89_RATE_MCS_NUM];
719 s8 hedcm[RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM];
720 s8 offset[RTW89_RATE_OFFSET_NUM];
721 };
722
723 enum rtw89_bandwidth_section_num {
724 RTW89_BW20_SEC_NUM = 8,
725 RTW89_BW40_SEC_NUM = 4,
726 RTW89_BW80_SEC_NUM = 2,
727 };
728
729 #define RTW89_TXPWR_LMT_PAGE_SIZE 40
730
731 struct rtw89_txpwr_limit {
732 s8 cck_20m[RTW89_BF_NUM];
733 s8 cck_40m[RTW89_BF_NUM];
734 s8 ofdm[RTW89_BF_NUM];
735 s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM];
736 s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM];
737 s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM];
738 s8 mcs_160m[RTW89_BF_NUM];
739 s8 mcs_40m_0p5[RTW89_BF_NUM];
740 s8 mcs_40m_2p5[RTW89_BF_NUM];
741 };
742
743 #define RTW89_RU_SEC_NUM 8
744
745 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE 24
746
747 struct rtw89_txpwr_limit_ru {
748 s8 ru26[RTW89_RU_SEC_NUM];
749 s8 ru52[RTW89_RU_SEC_NUM];
750 s8 ru106[RTW89_RU_SEC_NUM];
751 };
752
753 struct rtw89_rate_desc {
754 enum rtw89_nss nss;
755 enum rtw89_rate_section rs;
756 u8 idx;
757 };
758
759 #define PHY_STS_HDR_LEN 8
760 #define RF_PATH_MAX 4
761 #define RTW89_MAX_PPDU_CNT 8
762 struct rtw89_rx_phy_ppdu {
763 void *buf;
764 u32 len;
765 u8 rssi_avg;
766 u8 rssi[RF_PATH_MAX];
767 u8 mac_id;
768 u8 chan_idx;
769 u8 ie;
770 u16 rate;
771 struct {
772 bool has;
773 u8 avg_snr;
774 u8 evm_max;
775 u8 evm_min;
776 } ofdm;
777 bool to_self;
778 bool valid;
779 };
780
781 enum rtw89_mac_idx {
782 RTW89_MAC_0 = 0,
783 RTW89_MAC_1 = 1,
784 };
785
786 enum rtw89_phy_idx {
787 RTW89_PHY_0 = 0,
788 RTW89_PHY_1 = 1,
789 RTW89_PHY_MAX
790 };
791
792 enum rtw89_sub_entity_idx {
793 RTW89_SUB_ENTITY_0 = 0,
794 RTW89_SUB_ENTITY_1 = 1,
795
796 NUM_OF_RTW89_SUB_ENTITY,
797 RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY,
798 };
799
800 enum rtw89_rf_path {
801 RF_PATH_A = 0,
802 RF_PATH_B = 1,
803 RF_PATH_C = 2,
804 RF_PATH_D = 3,
805 RF_PATH_AB,
806 RF_PATH_AC,
807 RF_PATH_AD,
808 RF_PATH_BC,
809 RF_PATH_BD,
810 RF_PATH_CD,
811 RF_PATH_ABC,
812 RF_PATH_ABD,
813 RF_PATH_ACD,
814 RF_PATH_BCD,
815 RF_PATH_ABCD,
816 };
817
818 enum rtw89_rf_path_bit {
819 RF_A = BIT(0),
820 RF_B = BIT(1),
821 RF_C = BIT(2),
822 RF_D = BIT(3),
823
824 RF_AB = (RF_A | RF_B),
825 RF_AC = (RF_A | RF_C),
826 RF_AD = (RF_A | RF_D),
827 RF_BC = (RF_B | RF_C),
828 RF_BD = (RF_B | RF_D),
829 RF_CD = (RF_C | RF_D),
830
831 RF_ABC = (RF_A | RF_B | RF_C),
832 RF_ABD = (RF_A | RF_B | RF_D),
833 RF_ACD = (RF_A | RF_C | RF_D),
834 RF_BCD = (RF_B | RF_C | RF_D),
835
836 RF_ABCD = (RF_A | RF_B | RF_C | RF_D),
837 };
838
839 enum rtw89_bandwidth {
840 RTW89_CHANNEL_WIDTH_20 = 0,
841 RTW89_CHANNEL_WIDTH_40 = 1,
842 RTW89_CHANNEL_WIDTH_80 = 2,
843 RTW89_CHANNEL_WIDTH_160 = 3,
844 RTW89_CHANNEL_WIDTH_80_80 = 4,
845 RTW89_CHANNEL_WIDTH_5 = 5,
846 RTW89_CHANNEL_WIDTH_10 = 6,
847 };
848
849 enum rtw89_ps_mode {
850 RTW89_PS_MODE_NONE = 0,
851 RTW89_PS_MODE_RFOFF = 1,
852 RTW89_PS_MODE_CLK_GATED = 2,
853 RTW89_PS_MODE_PWR_GATED = 3,
854 };
855
856 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1)
857 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
858 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
859 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
860
861 enum rtw89_ru_bandwidth {
862 RTW89_RU26 = 0,
863 RTW89_RU52 = 1,
864 RTW89_RU106 = 2,
865 RTW89_RU_NUM,
866 };
867
868 enum rtw89_sc_offset {
869 RTW89_SC_DONT_CARE = 0,
870 RTW89_SC_20_UPPER = 1,
871 RTW89_SC_20_LOWER = 2,
872 RTW89_SC_20_UPMOST = 3,
873 RTW89_SC_20_LOWEST = 4,
874 RTW89_SC_20_UP2X = 5,
875 RTW89_SC_20_LOW2X = 6,
876 RTW89_SC_20_UP3X = 7,
877 RTW89_SC_20_LOW3X = 8,
878 RTW89_SC_40_UPPER = 9,
879 RTW89_SC_40_LOWER = 10,
880 };
881
882 enum rtw89_wow_flags {
883 RTW89_WOW_FLAG_EN_MAGIC_PKT,
884 RTW89_WOW_FLAG_EN_REKEY_PKT,
885 RTW89_WOW_FLAG_EN_DISCONNECT,
886 RTW89_WOW_FLAG_NUM,
887 };
888
889 struct rtw89_chan {
890 u8 channel;
891 u8 primary_channel;
892 enum rtw89_band band_type;
893 enum rtw89_bandwidth band_width;
894
895 /* The follow-up are derived from the above. We must ensure that it
896 * is assigned correctly in rtw89_chan_create() if new one is added.
897 */
898 u32 freq;
899 enum rtw89_subband subband_type;
900 enum rtw89_sc_offset pri_ch_idx;
901 };
902
903 struct rtw89_chan_rcd {
904 u8 prev_primary_channel;
905 enum rtw89_band prev_band_type;
906 bool band_changed;
907 };
908
909 struct rtw89_channel_help_params {
910 u32 tx_en;
911 };
912
913 struct rtw89_port_reg {
914 u32 port_cfg;
915 u32 tbtt_prohib;
916 u32 bcn_area;
917 u32 bcn_early;
918 u32 tbtt_early;
919 u32 tbtt_agg;
920 u32 bcn_space;
921 u32 bcn_forcetx;
922 u32 bcn_err_cnt;
923 u32 bcn_err_flag;
924 u32 dtim_ctrl;
925 u32 tbtt_shift;
926 u32 bcn_cnt_tmr;
927 u32 tsftr_l;
928 u32 tsftr_h;
929 };
930
931 struct rtw89_txwd_body {
932 __le32 dword0;
933 __le32 dword1;
934 __le32 dword2;
935 __le32 dword3;
936 __le32 dword4;
937 __le32 dword5;
938 } __packed;
939
940 struct rtw89_txwd_body_v1 {
941 __le32 dword0;
942 __le32 dword1;
943 __le32 dword2;
944 __le32 dword3;
945 __le32 dword4;
946 __le32 dword5;
947 __le32 dword6;
948 __le32 dword7;
949 } __packed;
950
951 struct rtw89_txwd_info {
952 __le32 dword0;
953 __le32 dword1;
954 __le32 dword2;
955 __le32 dword3;
956 __le32 dword4;
957 __le32 dword5;
958 } __packed;
959
960 struct rtw89_rx_desc_info {
961 u16 pkt_size;
962 u8 pkt_type;
963 u8 drv_info_size;
964 u8 shift;
965 u8 wl_hd_iv_len;
966 bool long_rxdesc;
967 bool bb_sel;
968 bool mac_info_valid;
969 u16 data_rate;
970 u8 gi_ltf;
971 u8 bw;
972 u32 free_run_cnt;
973 u8 user_id;
974 bool sr_en;
975 u8 ppdu_cnt;
976 u8 ppdu_type;
977 bool icv_err;
978 bool crc32_err;
979 bool hw_dec;
980 bool sw_dec;
981 bool addr1_match;
982 u8 frag;
983 u16 seq;
984 u8 frame_type;
985 u8 rx_pl_id;
986 bool addr_cam_valid;
987 u8 addr_cam_id;
988 u8 sec_cam_id;
989 u8 mac_id;
990 u16 offset;
991 u16 rxd_len;
992 bool ready;
993 };
994
995 struct rtw89_rxdesc_short {
996 __le32 dword0;
997 __le32 dword1;
998 __le32 dword2;
999 __le32 dword3;
1000 } __packed;
1001
1002 struct rtw89_rxdesc_long {
1003 __le32 dword0;
1004 __le32 dword1;
1005 __le32 dword2;
1006 __le32 dword3;
1007 __le32 dword4;
1008 __le32 dword5;
1009 __le32 dword6;
1010 __le32 dword7;
1011 } __packed;
1012
1013 struct rtw89_tx_desc_info {
1014 u16 pkt_size;
1015 u8 wp_offset;
1016 u8 mac_id;
1017 u8 qsel;
1018 u8 ch_dma;
1019 u8 hdr_llc_len;
1020 bool is_bmc;
1021 bool en_wd_info;
1022 bool wd_page;
1023 bool use_rate;
1024 bool dis_data_fb;
1025 bool tid_indicate;
1026 bool agg_en;
1027 bool bk;
1028 u8 ampdu_density;
1029 u8 ampdu_num;
1030 bool sec_en;
1031 u8 addr_info_nr;
1032 u8 sec_keyid;
1033 u8 sec_type;
1034 u8 sec_cam_idx;
1035 u8 sec_seq[6];
1036 u16 data_rate;
1037 u16 data_retry_lowest_rate;
1038 bool fw_dl;
1039 u16 seq;
1040 bool a_ctrl_bsr;
1041 u8 hw_ssn_sel;
1042 #define RTW89_MGMT_HW_SSN_SEL 1
1043 u8 hw_seq_mode;
1044 #define RTW89_MGMT_HW_SEQ_MODE 1
1045 bool hiq;
1046 u8 port;
1047 bool er_cap;
1048 };
1049
1050 struct rtw89_core_tx_request {
1051 enum rtw89_core_tx_type tx_type;
1052
1053 struct sk_buff *skb;
1054 struct ieee80211_vif *vif;
1055 struct ieee80211_sta *sta;
1056 struct rtw89_tx_desc_info desc_info;
1057 };
1058
1059 struct rtw89_txq {
1060 struct list_head list;
1061 unsigned long flags;
1062 int wait_cnt;
1063 };
1064
1065 struct rtw89_mac_ax_gnt {
1066 u8 gnt_bt_sw_en;
1067 u8 gnt_bt;
1068 u8 gnt_wl_sw_en;
1069 u8 gnt_wl;
1070 } __packed;
1071
1072 #define RTW89_MAC_AX_COEX_GNT_NR 2
1073 struct rtw89_mac_ax_coex_gnt {
1074 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR];
1075 };
1076
1077 enum rtw89_btc_ncnt {
1078 BTC_NCNT_POWER_ON = 0x0,
1079 BTC_NCNT_POWER_OFF,
1080 BTC_NCNT_INIT_COEX,
1081 BTC_NCNT_SCAN_START,
1082 BTC_NCNT_SCAN_FINISH,
1083 BTC_NCNT_SPECIAL_PACKET,
1084 BTC_NCNT_SWITCH_BAND,
1085 BTC_NCNT_RFK_TIMEOUT,
1086 BTC_NCNT_SHOW_COEX_INFO,
1087 BTC_NCNT_ROLE_INFO,
1088 BTC_NCNT_CONTROL,
1089 BTC_NCNT_RADIO_STATE,
1090 BTC_NCNT_CUSTOMERIZE,
1091 BTC_NCNT_WL_RFK,
1092 BTC_NCNT_WL_STA,
1093 BTC_NCNT_FWINFO,
1094 BTC_NCNT_TIMER,
1095 BTC_NCNT_NUM
1096 };
1097
1098 enum rtw89_btc_btinfo {
1099 BTC_BTINFO_L0 = 0,
1100 BTC_BTINFO_L1,
1101 BTC_BTINFO_L2,
1102 BTC_BTINFO_L3,
1103 BTC_BTINFO_H0,
1104 BTC_BTINFO_H1,
1105 BTC_BTINFO_H2,
1106 BTC_BTINFO_H3,
1107 BTC_BTINFO_MAX
1108 };
1109
1110 enum rtw89_btc_dcnt {
1111 BTC_DCNT_RUN = 0x0,
1112 BTC_DCNT_CX_RUNINFO,
1113 BTC_DCNT_RPT,
1114 BTC_DCNT_RPT_HANG,
1115 BTC_DCNT_CYCLE,
1116 BTC_DCNT_CYCLE_HANG,
1117 BTC_DCNT_W1,
1118 BTC_DCNT_W1_HANG,
1119 BTC_DCNT_B1,
1120 BTC_DCNT_B1_HANG,
1121 BTC_DCNT_TDMA_NONSYNC,
1122 BTC_DCNT_SLOT_NONSYNC,
1123 BTC_DCNT_BTCNT_HANG,
1124 BTC_DCNT_WL_SLOT_DRIFT,
1125 BTC_DCNT_WL_STA_LAST,
1126 BTC_DCNT_BT_SLOT_DRIFT,
1127 BTC_DCNT_BT_SLOT_FLOOD,
1128 BTC_DCNT_FDDT_TRIG,
1129 BTC_DCNT_E2G,
1130 BTC_DCNT_E2G_HANG,
1131 BTC_DCNT_NUM
1132 };
1133
1134 enum rtw89_btc_wl_state_cnt {
1135 BTC_WCNT_SCANAP = 0x0,
1136 BTC_WCNT_DHCP,
1137 BTC_WCNT_EAPOL,
1138 BTC_WCNT_ARP,
1139 BTC_WCNT_SCBDUPDATE,
1140 BTC_WCNT_RFK_REQ,
1141 BTC_WCNT_RFK_GO,
1142 BTC_WCNT_RFK_REJECT,
1143 BTC_WCNT_RFK_TIMEOUT,
1144 BTC_WCNT_CH_UPDATE,
1145 BTC_WCNT_NUM
1146 };
1147
1148 enum rtw89_btc_bt_state_cnt {
1149 BTC_BCNT_RETRY = 0x0,
1150 BTC_BCNT_REINIT,
1151 BTC_BCNT_REENABLE,
1152 BTC_BCNT_SCBDREAD,
1153 BTC_BCNT_RELINK,
1154 BTC_BCNT_IGNOWL,
1155 BTC_BCNT_INQPAG,
1156 BTC_BCNT_INQ,
1157 BTC_BCNT_PAGE,
1158 BTC_BCNT_ROLESW,
1159 BTC_BCNT_AFH,
1160 BTC_BCNT_INFOUPDATE,
1161 BTC_BCNT_INFOSAME,
1162 BTC_BCNT_SCBDUPDATE,
1163 BTC_BCNT_HIPRI_TX,
1164 BTC_BCNT_HIPRI_RX,
1165 BTC_BCNT_LOPRI_TX,
1166 BTC_BCNT_LOPRI_RX,
1167 BTC_BCNT_POLUT,
1168 BTC_BCNT_RATECHG,
1169 BTC_BCNT_NUM
1170 };
1171
1172 enum rtw89_btc_bt_profile {
1173 BTC_BT_NOPROFILE = 0,
1174 BTC_BT_HFP = BIT(0),
1175 BTC_BT_HID = BIT(1),
1176 BTC_BT_A2DP = BIT(2),
1177 BTC_BT_PAN = BIT(3),
1178 BTC_PROFILE_MAX = 4,
1179 };
1180
1181 struct rtw89_btc_ant_info {
1182 u8 type; /* shared, dedicated */
1183 u8 num;
1184 u8 isolation;
1185
1186 u8 single_pos: 1;/* Single antenna at S0 or S1 */
1187 u8 diversity: 1;
1188 u8 btg_pos: 2;
1189 u8 stream_cnt: 4;
1190 };
1191
1192 enum rtw89_tfc_dir {
1193 RTW89_TFC_UL,
1194 RTW89_TFC_DL,
1195 };
1196
1197 struct rtw89_btc_wl_smap {
1198 u32 busy: 1;
1199 u32 scan: 1;
1200 u32 connecting: 1;
1201 u32 roaming: 1;
1202 u32 _4way: 1;
1203 u32 rf_off: 1;
1204 u32 lps: 2;
1205 u32 ips: 1;
1206 u32 init_ok: 1;
1207 u32 traffic_dir : 2;
1208 u32 rf_off_pre: 1;
1209 u32 lps_pre: 2;
1210 };
1211
1212 enum rtw89_tfc_lv {
1213 RTW89_TFC_IDLE,
1214 RTW89_TFC_ULTRA_LOW,
1215 RTW89_TFC_LOW,
1216 RTW89_TFC_MID,
1217 RTW89_TFC_HIGH,
1218 };
1219
1220 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */
1221 DECLARE_EWMA(tp, 10, 2);
1222
1223 struct rtw89_traffic_stats {
1224 /* units in bytes */
1225 u64 tx_unicast;
1226 u64 rx_unicast;
1227 u32 tx_avg_len;
1228 u32 rx_avg_len;
1229
1230 /* count for packets */
1231 u64 tx_cnt;
1232 u64 rx_cnt;
1233
1234 /* units in Mbps */
1235 u32 tx_throughput;
1236 u32 rx_throughput;
1237 u32 tx_throughput_raw;
1238 u32 rx_throughput_raw;
1239
1240 u32 rx_tf_acc;
1241 u32 rx_tf_periodic;
1242
1243 enum rtw89_tfc_lv tx_tfc_lv;
1244 enum rtw89_tfc_lv rx_tfc_lv;
1245 struct ewma_tp tx_ewma_tp;
1246 struct ewma_tp rx_ewma_tp;
1247
1248 u16 tx_rate;
1249 u16 rx_rate;
1250 };
1251
1252 struct rtw89_btc_statistic {
1253 u8 rssi; /* 0%~110% (dBm = rssi -110) */
1254 struct rtw89_traffic_stats traffic;
1255 };
1256
1257 #define BTC_WL_RSSI_THMAX 4
1258
1259 struct rtw89_btc_wl_link_info {
1260 struct rtw89_btc_statistic stat;
1261 enum rtw89_tfc_dir dir;
1262 u8 rssi_state[BTC_WL_RSSI_THMAX];
1263 u8 mac_addr[ETH_ALEN];
1264 u8 busy;
1265 u8 ch;
1266 u8 bw;
1267 u8 band;
1268 u8 role;
1269 u8 pid;
1270 u8 phy;
1271 u8 dtim_period;
1272 u8 mode;
1273
1274 u8 mac_id;
1275 u8 tx_retry;
1276
1277 u32 bcn_period;
1278 u32 busy_t;
1279 u32 tx_time;
1280 u32 client_cnt;
1281 u32 rx_rate_drop_cnt;
1282
1283 u32 active: 1;
1284 u32 noa: 1;
1285 u32 client_ps: 1;
1286 u32 connected: 2;
1287 };
1288
1289 union rtw89_btc_wl_state_map {
1290 u32 val;
1291 struct rtw89_btc_wl_smap map;
1292 };
1293
1294 struct rtw89_btc_bt_hfp_desc {
1295 u32 exist: 1;
1296 u32 type: 2;
1297 u32 rsvd: 29;
1298 };
1299
1300 struct rtw89_btc_bt_hid_desc {
1301 u32 exist: 1;
1302 u32 slot_info: 2;
1303 u32 pair_cnt: 2;
1304 u32 type: 8;
1305 u32 rsvd: 19;
1306 };
1307
1308 struct rtw89_btc_bt_a2dp_desc {
1309 u8 exist: 1;
1310 u8 exist_last: 1;
1311 u8 play_latency: 1;
1312 u8 type: 3;
1313 u8 active: 1;
1314 u8 sink: 1;
1315
1316 u8 bitpool;
1317 u16 vendor_id;
1318 u32 device_name;
1319 u32 flush_time;
1320 };
1321
1322 struct rtw89_btc_bt_pan_desc {
1323 u32 exist: 1;
1324 u32 type: 1;
1325 u32 active: 1;
1326 u32 rsvd: 29;
1327 };
1328
1329 struct rtw89_btc_bt_rfk_info {
1330 u32 run: 1;
1331 u32 req: 1;
1332 u32 timeout: 1;
1333 u32 rsvd: 29;
1334 };
1335
1336 union rtw89_btc_bt_rfk_info_map {
1337 u32 val;
1338 struct rtw89_btc_bt_rfk_info map;
1339 };
1340
1341 struct rtw89_btc_bt_ver_info {
1342 u32 fw_coex; /* match with which coex_ver */
1343 u32 fw;
1344 };
1345
1346 struct rtw89_btc_bool_sta_chg {
1347 u32 now: 1;
1348 u32 last: 1;
1349 u32 remain: 1;
1350 u32 srvd: 29;
1351 };
1352
1353 struct rtw89_btc_u8_sta_chg {
1354 u8 now;
1355 u8 last;
1356 u8 remain;
1357 u8 rsvd;
1358 };
1359
1360 struct rtw89_btc_wl_scan_info {
1361 u8 band[RTW89_PHY_MAX];
1362 u8 phy_map;
1363 u8 rsvd;
1364 };
1365
1366 struct rtw89_btc_wl_dbcc_info {
1367 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */
1368 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */
1369 u8 real_band[RTW89_PHY_MAX];
1370 u8 role[RTW89_PHY_MAX]; /* role in each phy */
1371 };
1372
1373 struct rtw89_btc_wl_active_role {
1374 u8 connected: 1;
1375 u8 pid: 3;
1376 u8 phy: 1;
1377 u8 noa: 1;
1378 u8 band: 2;
1379
1380 u8 client_ps: 1;
1381 u8 bw: 7;
1382
1383 u8 role;
1384 u8 ch;
1385
1386 u16 tx_lvl;
1387 u16 rx_lvl;
1388 u16 tx_rate;
1389 u16 rx_rate;
1390 };
1391
1392 struct rtw89_btc_wl_active_role_v1 {
1393 u8 connected: 1;
1394 u8 pid: 3;
1395 u8 phy: 1;
1396 u8 noa: 1;
1397 u8 band: 2;
1398
1399 u8 client_ps: 1;
1400 u8 bw: 7;
1401
1402 u8 role;
1403 u8 ch;
1404
1405 u16 tx_lvl;
1406 u16 rx_lvl;
1407 u16 tx_rate;
1408 u16 rx_rate;
1409
1410 u32 noa_duration; /* ms */
1411 };
1412
1413 struct rtw89_btc_wl_active_role_v2 {
1414 u8 connected: 1;
1415 u8 pid: 3;
1416 u8 phy: 1;
1417 u8 noa: 1;
1418 u8 band: 2;
1419
1420 u8 client_ps: 1;
1421 u8 bw: 7;
1422
1423 u8 role;
1424 u8 ch;
1425
1426 u32 noa_duration; /* ms */
1427 };
1428
1429 struct rtw89_btc_wl_role_info_bpos {
1430 u16 none: 1;
1431 u16 station: 1;
1432 u16 ap: 1;
1433 u16 vap: 1;
1434 u16 adhoc: 1;
1435 u16 adhoc_master: 1;
1436 u16 mesh: 1;
1437 u16 moniter: 1;
1438 u16 p2p_device: 1;
1439 u16 p2p_gc: 1;
1440 u16 p2p_go: 1;
1441 u16 nan: 1;
1442 };
1443
1444 struct rtw89_btc_wl_scc_ctrl {
1445 u8 null_role1;
1446 u8 null_role2;
1447 u8 ebt_null; /* if tx null at EBT slot */
1448 };
1449
1450 union rtw89_btc_wl_role_info_map {
1451 u16 val;
1452 struct rtw89_btc_wl_role_info_bpos role;
1453 };
1454
1455 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */
1456 u8 connect_cnt;
1457 u8 link_mode;
1458 union rtw89_btc_wl_role_info_map role_map;
1459 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM];
1460 };
1461
1462 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */
1463 u8 connect_cnt;
1464 u8 link_mode;
1465 union rtw89_btc_wl_role_info_map role_map;
1466 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM];
1467 u32 mrole_type; /* btc_wl_mrole_type */
1468 u32 mrole_noa_duration; /* ms */
1469
1470 u32 dbcc_en: 1;
1471 u32 dbcc_chg: 1;
1472 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1473 u32 link_mode_chg: 1;
1474 u32 rsvd: 27;
1475 };
1476
1477 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */
1478 u8 connect_cnt;
1479 u8 link_mode;
1480 union rtw89_btc_wl_role_info_map role_map;
1481 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM];
1482 u32 mrole_type; /* btc_wl_mrole_type */
1483 u32 mrole_noa_duration; /* ms */
1484
1485 u32 dbcc_en: 1;
1486 u32 dbcc_chg: 1;
1487 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1488 u32 link_mode_chg: 1;
1489 u32 rsvd: 27;
1490 };
1491
1492 struct rtw89_btc_wl_ver_info {
1493 u32 fw_coex; /* match with which coex_ver */
1494 u32 fw;
1495 u32 mac;
1496 u32 bb;
1497 u32 rf;
1498 };
1499
1500 struct rtw89_btc_wl_afh_info {
1501 u8 en;
1502 u8 ch;
1503 u8 bw;
1504 u8 rsvd;
1505 } __packed;
1506
1507 struct rtw89_btc_wl_rfk_info {
1508 u32 state: 2;
1509 u32 path_map: 4;
1510 u32 phy_map: 2;
1511 u32 band: 2;
1512 u32 type: 8;
1513 u32 rsvd: 14;
1514 };
1515
1516 struct rtw89_btc_bt_smap {
1517 u32 connect: 1;
1518 u32 ble_connect: 1;
1519 u32 acl_busy: 1;
1520 u32 sco_busy: 1;
1521 u32 mesh_busy: 1;
1522 u32 inq_pag: 1;
1523 };
1524
1525 union rtw89_btc_bt_state_map {
1526 u32 val;
1527 struct rtw89_btc_bt_smap map;
1528 };
1529
1530 #define BTC_BT_RSSI_THMAX 4
1531 #define BTC_BT_AFH_GROUP 12
1532 #define BTC_BT_AFH_LE_GROUP 5
1533
1534 struct rtw89_btc_bt_link_info {
1535 struct rtw89_btc_u8_sta_chg profile_cnt;
1536 struct rtw89_btc_bool_sta_chg multi_link;
1537 struct rtw89_btc_bool_sta_chg relink;
1538 struct rtw89_btc_bt_hfp_desc hfp_desc;
1539 struct rtw89_btc_bt_hid_desc hid_desc;
1540 struct rtw89_btc_bt_a2dp_desc a2dp_desc;
1541 struct rtw89_btc_bt_pan_desc pan_desc;
1542 union rtw89_btc_bt_state_map status;
1543
1544 u8 sut_pwr_level[BTC_PROFILE_MAX];
1545 u8 golden_rx_shift[BTC_PROFILE_MAX];
1546 u8 rssi_state[BTC_BT_RSSI_THMAX];
1547 u8 afh_map[BTC_BT_AFH_GROUP];
1548 u8 afh_map_le[BTC_BT_AFH_LE_GROUP];
1549
1550 u32 role_sw: 1;
1551 u32 slave_role: 1;
1552 u32 afh_update: 1;
1553 u32 cqddr: 1;
1554 u32 rssi: 8;
1555 u32 tx_3m: 1;
1556 u32 rsvd: 19;
1557 };
1558
1559 struct rtw89_btc_3rdcx_info {
1560 u8 type; /* 0: none, 1:zigbee, 2:LTE */
1561 u8 hw_coex;
1562 u16 rsvd;
1563 };
1564
1565 struct rtw89_btc_dm_emap {
1566 u32 init: 1;
1567 u32 pta_owner: 1;
1568 u32 wl_rfk_timeout: 1;
1569 u32 bt_rfk_timeout: 1;
1570 u32 wl_fw_hang: 1;
1571 u32 cycle_hang: 1;
1572 u32 w1_hang: 1;
1573 u32 b1_hang: 1;
1574 u32 tdma_no_sync: 1;
1575 u32 slot_no_sync: 1;
1576 u32 wl_slot_drift: 1;
1577 u32 bt_slot_drift: 1;
1578 u32 role_num_mismatch: 1;
1579 u32 null1_tx_late: 1;
1580 u32 bt_afh_conflict: 1;
1581 u32 bt_leafh_conflict: 1;
1582 u32 bt_slot_flood: 1;
1583 u32 wl_e2g_hang: 1;
1584 u32 wl_ver_mismatch: 1;
1585 u32 bt_ver_mismatch: 1;
1586 };
1587
1588 union rtw89_btc_dm_error_map {
1589 u32 val;
1590 struct rtw89_btc_dm_emap map;
1591 };
1592
1593 struct rtw89_btc_rf_para {
1594 u32 tx_pwr_freerun;
1595 u32 rx_gain_freerun;
1596 u32 tx_pwr_perpkt;
1597 u32 rx_gain_perpkt;
1598 };
1599
1600 struct rtw89_btc_wl_nhm {
1601 u8 instant_wl_nhm_dbm;
1602 u8 instant_wl_nhm_per_mhz;
1603 u16 valid_record_times;
1604 s8 record_pwr[16];
1605 u8 record_ratio[16];
1606 s8 pwr; /* dbm_per_MHz */
1607 u8 ratio;
1608 u8 current_status;
1609 u8 refresh;
1610 bool start_flag;
1611 s8 pwr_max;
1612 s8 pwr_min;
1613 };
1614
1615 struct rtw89_btc_wl_info {
1616 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM];
1617 struct rtw89_btc_wl_rfk_info rfk_info;
1618 struct rtw89_btc_wl_ver_info ver_info;
1619 struct rtw89_btc_wl_afh_info afh_info;
1620 struct rtw89_btc_wl_role_info role_info;
1621 struct rtw89_btc_wl_role_info_v1 role_info_v1;
1622 struct rtw89_btc_wl_role_info_v2 role_info_v2;
1623 struct rtw89_btc_wl_scan_info scan_info;
1624 struct rtw89_btc_wl_dbcc_info dbcc_info;
1625 struct rtw89_btc_rf_para rf_para;
1626 struct rtw89_btc_wl_nhm nhm;
1627 union rtw89_btc_wl_state_map status;
1628
1629 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX];
1630 u8 rssi_level;
1631 u8 cn_report;
1632
1633 bool scbd_change;
1634 u32 scbd;
1635 };
1636
1637 struct rtw89_btc_module {
1638 struct rtw89_btc_ant_info ant;
1639 u8 rfe_type;
1640 u8 cv;
1641
1642 u8 bt_solo: 1;
1643 u8 bt_pos: 1;
1644 u8 switch_type: 1;
1645 u8 wa_type: 3;
1646
1647 u8 kt_ver_adie;
1648 };
1649
1650 #define RTW89_BTC_DM_MAXSTEP 30
1651 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8)
1652
1653 struct rtw89_btc_dm_step {
1654 u16 step[RTW89_BTC_DM_MAXSTEP];
1655 u8 step_pos;
1656 bool step_ov;
1657 };
1658
1659 struct rtw89_btc_init_info {
1660 struct rtw89_btc_module module;
1661 u8 wl_guard_ch;
1662
1663 u8 wl_only: 1;
1664 u8 wl_init_ok: 1;
1665 u8 dbcc_en: 1;
1666 u8 cx_other: 1;
1667 u8 bt_only: 1;
1668
1669 u16 rsvd;
1670 };
1671
1672 struct rtw89_btc_wl_tx_limit_para {
1673 u16 enable;
1674 u32 tx_time; /* unit: us */
1675 u16 tx_retry;
1676 };
1677
1678 enum rtw89_btc_bt_scan_type {
1679 BTC_SCAN_INQ = 0,
1680 BTC_SCAN_PAGE,
1681 BTC_SCAN_BLE,
1682 BTC_SCAN_INIT,
1683 BTC_SCAN_TV,
1684 BTC_SCAN_ADV,
1685 BTC_SCAN_MAX1,
1686 };
1687
1688 enum rtw89_btc_ble_scan_type {
1689 CXSCAN_BG = 0,
1690 CXSCAN_INIT,
1691 CXSCAN_LE,
1692 CXSCAN_MAX
1693 };
1694
1695 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0)
1696 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1)
1697
1698 struct rtw89_btc_bt_scan_info_v1 {
1699 __le16 win;
1700 __le16 intvl;
1701 __le32 flags;
1702 } __packed;
1703
1704 struct rtw89_btc_bt_scan_info_v2 {
1705 __le16 win;
1706 __le16 intvl;
1707 } __packed;
1708
1709 struct rtw89_btc_fbtc_btscan_v1 {
1710 u8 fver; /* btc_ver::fcxbtscan */
1711 u8 rsvd;
1712 __le16 rsvd2;
1713 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1];
1714 } __packed;
1715
1716 struct rtw89_btc_fbtc_btscan_v2 {
1717 u8 fver; /* btc_ver::fcxbtscan */
1718 u8 type;
1719 __le16 rsvd2;
1720 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
1721 } __packed;
1722
1723 union rtw89_btc_fbtc_btscan {
1724 struct rtw89_btc_fbtc_btscan_v1 v1;
1725 struct rtw89_btc_fbtc_btscan_v2 v2;
1726 };
1727
1728 struct rtw89_btc_bt_info {
1729 struct rtw89_btc_bt_link_info link_info;
1730 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1];
1731 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX];
1732 struct rtw89_btc_bt_ver_info ver_info;
1733 struct rtw89_btc_bool_sta_chg enable;
1734 struct rtw89_btc_bool_sta_chg inq_pag;
1735 struct rtw89_btc_rf_para rf_para;
1736 union rtw89_btc_bt_rfk_info_map rfk_info;
1737
1738 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */
1739
1740 u32 scbd;
1741 u32 feature;
1742
1743 u32 mbx_avl: 1;
1744 u32 whql_test: 1;
1745 u32 igno_wl: 1;
1746 u32 reinit: 1;
1747 u32 ble_scan_en: 1;
1748 u32 btg_type: 1;
1749 u32 inq: 1;
1750 u32 pag: 1;
1751 u32 run_patch_code: 1;
1752 u32 hi_lna_rx: 1;
1753 u32 scan_rx_low_pri: 1;
1754 u32 scan_info_update: 1;
1755 u32 rsvd: 20;
1756 };
1757
1758 struct rtw89_btc_cx {
1759 struct rtw89_btc_wl_info wl;
1760 struct rtw89_btc_bt_info bt;
1761 struct rtw89_btc_3rdcx_info other;
1762 u32 state_map;
1763 u32 cnt_bt[BTC_BCNT_NUM];
1764 u32 cnt_wl[BTC_WCNT_NUM];
1765 };
1766
1767 struct rtw89_btc_fbtc_tdma {
1768 u8 type; /* btc_ver::fcxtdma */
1769 u8 rxflctrl;
1770 u8 txpause;
1771 u8 wtgle_n;
1772 u8 leak_n;
1773 u8 ext_ctrl;
1774 u8 rxflctrl_role;
1775 u8 option_ctrl;
1776 } __packed;
1777
1778 struct rtw89_btc_fbtc_tdma_v3 {
1779 u8 fver; /* btc_ver::fcxtdma */
1780 u8 rsvd;
1781 __le16 rsvd1;
1782 struct rtw89_btc_fbtc_tdma tdma;
1783 } __packed;
1784
1785 union rtw89_btc_fbtc_tdma_le32 {
1786 struct rtw89_btc_fbtc_tdma v1;
1787 struct rtw89_btc_fbtc_tdma_v3 v3;
1788 };
1789
1790 #define CXMREG_MAX 30
1791 #define CXMREG_MAX_V2 20
1792 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/
1793 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */
1794
1795 enum rtw89_btc_bt_sta_counter {
1796 BTC_BCNT_RFK_REQ = 0,
1797 BTC_BCNT_RFK_GO = 1,
1798 BTC_BCNT_RFK_REJECT = 2,
1799 BTC_BCNT_RFK_FAIL = 3,
1800 BTC_BCNT_RFK_TIMEOUT = 4,
1801 BTC_BCNT_HI_TX = 5,
1802 BTC_BCNT_HI_RX = 6,
1803 BTC_BCNT_LO_TX = 7,
1804 BTC_BCNT_LO_RX = 8,
1805 BTC_BCNT_POLLUTED = 9,
1806 BTC_BCNT_STA_MAX
1807 };
1808
1809 enum rtw89_btc_bt_sta_counter_v105 {
1810 BTC_BCNT_RFK_REQ_V105 = 0,
1811 BTC_BCNT_HI_TX_V105 = 1,
1812 BTC_BCNT_HI_RX_V105 = 2,
1813 BTC_BCNT_LO_TX_V105 = 3,
1814 BTC_BCNT_LO_RX_V105 = 4,
1815 BTC_BCNT_POLLUTED_V105 = 5,
1816 BTC_BCNT_STA_MAX_V105
1817 };
1818
1819 struct rtw89_btc_fbtc_rpt_ctrl_v1 {
1820 u16 fver; /* btc_ver::fcxbtcrpt */
1821 u16 rpt_cnt; /* tmr counters */
1822 u32 wl_fw_coex_ver; /* match which driver's coex version */
1823 u32 wl_fw_cx_offload;
1824 u32 wl_fw_ver;
1825 u32 rpt_enable;
1826 u32 rpt_para; /* ms */
1827 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */
1828 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */
1829 u32 mb_recv_cnt; /* fw recv mailbox counter */
1830 u32 mb_a2dp_empty_cnt; /* a2dp empty count */
1831 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */
1832 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */
1833 u32 bt_rfk_cnt[BTC_BCNT_HI_TX];
1834 u32 c2h_cnt; /* fw send c2h counter */
1835 u32 h2c_cnt; /* fw recv h2c counter */
1836 } __packed;
1837
1838 struct rtw89_btc_fbtc_rpt_ctrl_info {
1839 __le32 cnt; /* fw report counter */
1840 __le32 en; /* report map */
1841 __le32 para; /* not used */
1842
1843 __le32 cnt_c2h; /* fw send c2h counter */
1844 __le32 cnt_h2c; /* fw recv h2c counter */
1845 __le32 len_c2h; /* The total length of the last C2H */
1846
1847 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
1848 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
1849 } __packed;
1850
1851 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 {
1852 __le32 cx_ver; /* match which driver's coex version */
1853 __le32 fw_ver;
1854 __le32 en; /* report map */
1855
1856 __le16 cnt; /* fw report counter */
1857 __le16 cnt_c2h; /* fw send c2h counter */
1858 __le16 cnt_h2c; /* fw recv h2c counter */
1859 __le16 len_c2h; /* The total length of the last C2H */
1860
1861 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
1862 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
1863 } __packed;
1864
1865 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info {
1866 __le32 cx_ver; /* match which driver's coex version */
1867 __le32 cx_offload;
1868 __le32 fw_ver;
1869 } __packed;
1870
1871 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty {
1872 __le32 cnt_empty; /* a2dp empty count */
1873 __le32 cnt_flowctrl; /* a2dp empty flow control counter */
1874 __le32 cnt_tx;
1875 __le32 cnt_ack;
1876 __le32 cnt_nack;
1877 } __packed;
1878
1879 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox {
1880 __le32 cnt_send_ok; /* fw send mailbox ok counter */
1881 __le32 cnt_send_fail; /* fw send mailbox fail counter */
1882 __le32 cnt_recv; /* fw recv mailbox counter */
1883 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp;
1884 } __packed;
1885
1886 struct rtw89_btc_fbtc_rpt_ctrl_v4 {
1887 u8 fver;
1888 u8 rsvd;
1889 __le16 rsvd1;
1890 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info;
1891 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info;
1892 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
1893 __le32 bt_cnt[BTC_BCNT_STA_MAX];
1894 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX];
1895 } __packed;
1896
1897 struct rtw89_btc_fbtc_rpt_ctrl_v5 {
1898 u8 fver;
1899 u8 rsvd;
1900 __le16 rsvd1;
1901
1902 u8 gnt_val[RTW89_PHY_MAX][4];
1903 __le16 bt_cnt[BTC_BCNT_STA_MAX];
1904
1905 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
1906 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
1907 } __packed;
1908
1909 struct rtw89_btc_fbtc_rpt_ctrl_v105 {
1910 u8 fver;
1911 u8 rsvd;
1912 __le16 rsvd1;
1913
1914 u8 gnt_val[RTW89_PHY_MAX][4];
1915 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
1916
1917 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
1918 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
1919 } __packed;
1920
1921 union rtw89_btc_fbtc_rpt_ctrl_ver_info {
1922 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1;
1923 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4;
1924 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5;
1925 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105;
1926 };
1927
1928 enum rtw89_fbtc_ext_ctrl_type {
1929 CXECTL_OFF = 0x0, /* tdma off */
1930 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
1931 CXECTL_EXT = 0x2,
1932 CXECTL_MAX
1933 };
1934
1935 union rtw89_btc_fbtc_rxflct {
1936 u8 val;
1937 u8 type: 3;
1938 u8 tgln_n: 5;
1939 };
1940
1941 enum rtw89_btc_cxst_state {
1942 CXST_OFF = 0x0,
1943 CXST_B2W = 0x1,
1944 CXST_W1 = 0x2,
1945 CXST_W2 = 0x3,
1946 CXST_W2B = 0x4,
1947 CXST_B1 = 0x5,
1948 CXST_B2 = 0x6,
1949 CXST_B3 = 0x7,
1950 CXST_B4 = 0x8,
1951 CXST_LK = 0x9,
1952 CXST_BLK = 0xa,
1953 CXST_E2G = 0xb,
1954 CXST_E5G = 0xc,
1955 CXST_EBT = 0xd,
1956 CXST_ENULL = 0xe,
1957 CXST_WLK = 0xf,
1958 CXST_W1FDD = 0x10,
1959 CXST_B1FDD = 0x11,
1960 CXST_MAX = 0x12,
1961 };
1962
1963 enum rtw89_btc_cxevnt {
1964 CXEVNT_TDMA_ENTRY = 0x0,
1965 CXEVNT_WL_TMR,
1966 CXEVNT_B1_TMR,
1967 CXEVNT_B2_TMR,
1968 CXEVNT_B3_TMR,
1969 CXEVNT_B4_TMR,
1970 CXEVNT_W2B_TMR,
1971 CXEVNT_B2W_TMR,
1972 CXEVNT_BCN_EARLY,
1973 CXEVNT_A2DP_EMPTY,
1974 CXEVNT_LK_END,
1975 CXEVNT_RX_ISR,
1976 CXEVNT_RX_FC0,
1977 CXEVNT_RX_FC1,
1978 CXEVNT_BT_RELINK,
1979 CXEVNT_BT_RETRY,
1980 CXEVNT_E2G,
1981 CXEVNT_E5G,
1982 CXEVNT_EBT,
1983 CXEVNT_ENULL,
1984 CXEVNT_DRV_WLK,
1985 CXEVNT_BCN_OK,
1986 CXEVNT_BT_CHANGE,
1987 CXEVNT_EBT_EXTEND,
1988 CXEVNT_E2G_NULL1,
1989 CXEVNT_B1FDD_TMR,
1990 CXEVNT_MAX
1991 };
1992
1993 enum {
1994 CXBCN_ALL = 0x0,
1995 CXBCN_ALL_OK,
1996 CXBCN_BT_SLOT,
1997 CXBCN_BT_OK,
1998 CXBCN_MAX
1999 };
2000
2001 enum btc_slot_type {
2002 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
2003 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
2004 CXSTYPE_NUM,
2005 };
2006
2007 enum { /* TIME */
2008 CXT_BT = 0x0,
2009 CXT_WL = 0x1,
2010 CXT_MAX
2011 };
2012
2013 enum { /* TIME-A2DP */
2014 CXT_FLCTRL_OFF = 0x0,
2015 CXT_FLCTRL_ON = 0x1,
2016 CXT_FLCTRL_MAX
2017 };
2018
2019 enum { /* STEP TYPE */
2020 CXSTEP_NONE = 0x0,
2021 CXSTEP_EVNT = 0x1,
2022 CXSTEP_SLOT = 0x2,
2023 CXSTEP_MAX,
2024 };
2025
2026 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */
2027 RPT_BT_AFH_SEQ_LEGACY = 0x10,
2028 RPT_BT_AFH_SEQ_LE = 0x20
2029 };
2030
2031 #define BTC_DBG_MAX1 32
2032 struct rtw89_btc_fbtc_gpio_dbg {
2033 u8 fver; /* btc_ver::fcxgpiodbg */
2034 u8 rsvd;
2035 u16 rsvd2;
2036 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */
2037 u32 pre_state; /* the debug signal is 1 or 0 */
2038 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */
2039 } __packed;
2040
2041 struct rtw89_btc_fbtc_mreg_val_v1 {
2042 u8 fver; /* btc_ver::fcxmreg */
2043 u8 reg_num;
2044 __le16 rsvd;
2045 __le32 mreg_val[CXMREG_MAX];
2046 } __packed;
2047
2048 struct rtw89_btc_fbtc_mreg_val_v2 {
2049 u8 fver; /* btc_ver::fcxmreg */
2050 u8 reg_num;
2051 __le16 rsvd;
2052 __le32 mreg_val[CXMREG_MAX_V2];
2053 } __packed;
2054
2055 union rtw89_btc_fbtc_mreg_val {
2056 struct rtw89_btc_fbtc_mreg_val_v1 v1;
2057 struct rtw89_btc_fbtc_mreg_val_v2 v2;
2058 };
2059
2060 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \
2061 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \
2062 .offset = cpu_to_le32(__offset), }
2063
2064 struct rtw89_btc_fbtc_mreg {
2065 __le16 type;
2066 __le16 bytes;
2067 __le32 offset;
2068 } __packed;
2069
2070 struct rtw89_btc_fbtc_slot {
2071 __le16 dur;
2072 __le32 cxtbl;
2073 __le16 cxtype;
2074 } __packed;
2075
2076 struct rtw89_btc_fbtc_slots {
2077 u8 fver; /* btc_ver::fcxslots */
2078 u8 tbl_num;
2079 __le16 rsvd;
2080 __le32 update_map;
2081 struct rtw89_btc_fbtc_slot slot[CXST_MAX];
2082 } __packed;
2083
2084 struct rtw89_btc_fbtc_step {
2085 u8 type;
2086 u8 val;
2087 __le16 difft;
2088 } __packed;
2089
2090 struct rtw89_btc_fbtc_steps_v2 {
2091 u8 fver; /* btc_ver::fcxstep */
2092 u8 rsvd;
2093 __le16 cnt;
2094 __le16 pos_old;
2095 __le16 pos_new;
2096 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2097 } __packed;
2098
2099 struct rtw89_btc_fbtc_steps_v3 {
2100 u8 fver;
2101 u8 en;
2102 __le16 rsvd;
2103 __le32 cnt;
2104 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2105 } __packed;
2106
2107 union rtw89_btc_fbtc_steps_info {
2108 struct rtw89_btc_fbtc_steps_v2 v2;
2109 struct rtw89_btc_fbtc_steps_v3 v3;
2110 };
2111
2112 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */
2113 u8 fver; /* btc_ver::fcxcysta */
2114 u8 rsvd;
2115 __le16 cycles; /* total cycle number */
2116 __le16 cycles_a2dp[CXT_FLCTRL_MAX];
2117 __le16 a2dpept; /* a2dp empty cnt */
2118 __le16 a2dpeptto; /* a2dp empty timeout cnt*/
2119 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */
2120 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */
2121 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2122 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */
2123 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */
2124 __le16 tavg_a2dpept; /* avg a2dp empty time */
2125 __le16 tmax_a2dpept; /* max a2dp empty time */
2126 __le16 tavg_lk; /* avg leak-slot time */
2127 __le16 tmax_lk; /* max leak-slot time */
2128 __le32 slot_cnt[CXST_MAX]; /* slot count */
2129 __le32 bcn_cnt[CXBCN_MAX];
2130 __le32 leakrx_cnt; /* the rximr occur at leak slot */
2131 __le32 collision_cnt; /* counter for event/timer occur at same time */
2132 __le32 skip_cnt;
2133 __le32 exception;
2134 __le32 except_cnt;
2135 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX];
2136 } __packed;
2137
2138 struct rtw89_btc_fbtc_fdd_try_info {
2139 __le16 cycles[CXT_FLCTRL_MAX];
2140 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */
2141 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */
2142 } __packed;
2143
2144 struct rtw89_btc_fbtc_cycle_time_info {
2145 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2146 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2147 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2148 } __packed;
2149
2150 struct rtw89_btc_fbtc_cycle_time_info_v5 {
2151 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2152 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2153 } __packed;
2154
2155 struct rtw89_btc_fbtc_a2dp_trx_stat {
2156 u8 empty_cnt;
2157 u8 retry_cnt;
2158 u8 tx_rate;
2159 u8 tx_cnt;
2160 u8 ack_cnt;
2161 u8 nack_cnt;
2162 u8 rsvd1;
2163 u8 rsvd2;
2164 } __packed;
2165
2166 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 {
2167 u8 empty_cnt;
2168 u8 retry_cnt;
2169 u8 tx_rate;
2170 u8 tx_cnt;
2171 u8 ack_cnt;
2172 u8 nack_cnt;
2173 u8 no_empty_cnt;
2174 u8 rsvd;
2175 } __packed;
2176
2177 struct rtw89_btc_fbtc_cycle_a2dp_empty_info {
2178 __le16 cnt; /* a2dp empty cnt */
2179 __le16 cnt_timeout; /* a2dp empty timeout cnt*/
2180 __le16 tavg; /* avg a2dp empty time */
2181 __le16 tmax; /* max a2dp empty time */
2182 } __packed;
2183
2184 struct rtw89_btc_fbtc_cycle_leak_info {
2185 __le32 cnt_rximr; /* the rximr occur at leak slot */
2186 __le16 tavg; /* avg leak-slot time */
2187 __le16 tmax; /* max leak-slot time */
2188 } __packed;
2189
2190 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0)
2191 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10)
2192
2193 struct rtw89_btc_fbtc_cycle_fddt_info {
2194 __le16 train_cycle;
2195 __le16 tp;
2196
2197 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2198 s8 bt_tx_power; /* decrease Tx power (dB) */
2199 s8 bt_rx_gain; /* LNA constrain level */
2200 u8 no_empty_cnt;
2201
2202 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2203 u8 cn; /* condition_num */
2204 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2205 u8 train_result; /* refer to enum btc_fddt_check_map */
2206 } __packed;
2207
2208 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0)
2209 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4)
2210
2211 struct rtw89_btc_fbtc_cycle_fddt_info_v5 {
2212 __le16 train_cycle;
2213 __le16 tp;
2214
2215 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2216 s8 bt_tx_power; /* decrease Tx power (dB) */
2217 s8 bt_rx_gain; /* LNA constrain level */
2218 u8 no_empty_cnt;
2219
2220 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2221 u8 cn; /* condition_num */
2222 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2223 u8 train_result; /* refer to enum btc_fddt_check_map */
2224 } __packed;
2225
2226 struct rtw89_btc_fbtc_fddt_cell_status {
2227 s8 wl_tx_pwr;
2228 s8 bt_tx_pwr;
2229 s8 bt_rx_gain;
2230 u8 state_phase; /* [0:3] train state, [4:7] train phase */
2231 } __packed;
2232
2233 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */
2234 u8 fver;
2235 u8 rsvd;
2236 __le16 cycles; /* total cycle number */
2237 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX];
2238 struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2239 struct rtw89_btc_fbtc_fdd_try_info fdd_try;
2240 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2241 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX];
2242 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2243 __le32 slot_cnt[CXST_MAX]; /* slot count */
2244 __le32 bcn_cnt[CXBCN_MAX];
2245 __le32 collision_cnt; /* counter for event/timer occur at the same time */
2246 __le32 skip_cnt;
2247 __le32 except_cnt;
2248 __le32 except_map;
2249 } __packed;
2250
2251 #define FDD_TRAIN_WL_DIRECTION 2
2252 #define FDD_TRAIN_WL_RSSI_LEVEL 5
2253 #define FDD_TRAIN_BT_RSSI_LEVEL 5
2254
2255 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */
2256 u8 fver;
2257 u8 rsvd;
2258 u8 collision_cnt; /* counter for event/timer occur at the same time */
2259 u8 except_cnt;
2260
2261 __le16 skip_cnt;
2262 __le16 cycles; /* total cycle number */
2263
2264 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2265 __le16 slot_cnt[CXST_MAX]; /* slot count */
2266 __le16 bcn_cnt[CXBCN_MAX];
2267 struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2268 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2269 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2270 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2271 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX];
2272 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2273 [FDD_TRAIN_WL_RSSI_LEVEL]
2274 [FDD_TRAIN_BT_RSSI_LEVEL];
2275 __le32 except_map;
2276 } __packed;
2277
2278 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */
2279 u8 fver;
2280 u8 rsvd;
2281 u8 collision_cnt; /* counter for event/timer occur at the same time */
2282 u8 except_cnt;
2283 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2284
2285 __le16 skip_cnt;
2286 __le16 cycles; /* total cycle number */
2287
2288 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2289 __le16 slot_cnt[CXST_MAX]; /* slot count */
2290 __le16 bcn_cnt[CXBCN_MAX];
2291 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2292 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2293 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2294 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2295 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX];
2296 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2297 [FDD_TRAIN_WL_RSSI_LEVEL]
2298 [FDD_TRAIN_BT_RSSI_LEVEL];
2299 __le32 except_map;
2300 } __packed;
2301
2302 union rtw89_btc_fbtc_cysta_info {
2303 struct rtw89_btc_fbtc_cysta_v2 v2;
2304 struct rtw89_btc_fbtc_cysta_v3 v3;
2305 struct rtw89_btc_fbtc_cysta_v4 v4;
2306 struct rtw89_btc_fbtc_cysta_v5 v5;
2307 };
2308
2309 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */
2310 u8 fver; /* btc_ver::fcxnullsta */
2311 u8 rsvd;
2312 __le16 rsvd2;
2313 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2314 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2315 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */
2316 } __packed;
2317
2318 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */
2319 u8 fver; /* btc_ver::fcxnullsta */
2320 u8 rsvd;
2321 __le16 rsvd2;
2322 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2323 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2324 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */
2325 } __packed;
2326
2327 union rtw89_btc_fbtc_cynullsta_info {
2328 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */
2329 struct rtw89_btc_fbtc_cynullsta_v2 v2;
2330 };
2331
2332 struct rtw89_btc_fbtc_btver {
2333 u8 fver; /* btc_ver::fcxbtver */
2334 u8 rsvd;
2335 __le16 rsvd2;
2336 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2337 __le32 fw_ver;
2338 __le32 feature;
2339 } __packed;
2340
2341 struct rtw89_btc_fbtc_btafh {
2342 u8 fver; /* btc_ver::fcxbtafh */
2343 u8 rsvd;
2344 __le16 rsvd2;
2345 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */
2346 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */
2347 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */
2348 } __packed;
2349
2350 struct rtw89_btc_fbtc_btafh_v2 {
2351 u8 fver; /* btc_ver::fcxbtafh */
2352 u8 rsvd;
2353 u8 rsvd2;
2354 u8 map_type;
2355 u8 afh_l[4];
2356 u8 afh_m[4];
2357 u8 afh_h[4];
2358 u8 afh_le_a[4];
2359 u8 afh_le_b[4];
2360 } __packed;
2361
2362 struct rtw89_btc_fbtc_btdevinfo {
2363 u8 fver; /* btc_ver::fcxbtdevinfo */
2364 u8 rsvd;
2365 __le16 vendor_id;
2366 __le32 dev_name; /* only 24 bits valid */
2367 __le32 flush_time;
2368 } __packed;
2369
2370 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0)
2371 struct rtw89_btc_rf_trx_para {
2372 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2373 u32 wl_rx_gain; /* rx gain table index (TBD.) */
2374 u8 bt_tx_power; /* decrease Tx power (dB) */
2375 u8 bt_rx_gain; /* LNA constrain level */
2376 };
2377
2378 struct rtw89_btc_trx_info {
2379 u8 tx_lvl;
2380 u8 rx_lvl;
2381 u8 wl_rssi;
2382 u8 bt_rssi;
2383
2384 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2385 s8 rx_gain; /* rx gain table index (TBD.) */
2386 s8 bt_tx_power; /* decrease Tx power (dB) */
2387 s8 bt_rx_gain; /* LNA constrain level */
2388
2389 u8 cn; /* condition_num */
2390 s8 nhm;
2391 u8 bt_profile;
2392 u8 rsvd2;
2393
2394 u16 tx_rate;
2395 u16 rx_rate;
2396
2397 u32 tx_tp;
2398 u32 rx_tp;
2399 u32 rx_err_ratio;
2400 };
2401
2402 struct rtw89_btc_dm {
2403 struct rtw89_btc_fbtc_slot slot[CXST_MAX];
2404 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX];
2405 struct rtw89_btc_fbtc_tdma tdma;
2406 struct rtw89_btc_fbtc_tdma tdma_now;
2407 struct rtw89_mac_ax_coex_gnt gnt;
2408 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */
2409 struct rtw89_btc_rf_trx_para rf_trx_para;
2410 struct rtw89_btc_wl_tx_limit_para wl_tx_limit;
2411 struct rtw89_btc_dm_step dm_step;
2412 struct rtw89_btc_wl_scc_ctrl wl_scc;
2413 struct rtw89_btc_trx_info trx_info;
2414 union rtw89_btc_dm_error_map error;
2415 u32 cnt_dm[BTC_DCNT_NUM];
2416 u32 cnt_notify[BTC_NCNT_NUM];
2417
2418 u32 update_slot_map;
2419 u32 set_ant_path;
2420
2421 u32 wl_only: 1;
2422 u32 wl_fw_cx_offload: 1;
2423 u32 freerun: 1;
2424 u32 fddt_train: 1;
2425 u32 wl_ps_ctrl: 2;
2426 u32 wl_mimo_ps: 1;
2427 u32 leak_ap: 1;
2428 u32 noisy_level: 3;
2429 u32 coex_info_map: 8;
2430 u32 bt_only: 1;
2431 u32 wl_btg_rx: 1;
2432 u32 trx_para_level: 8;
2433 u32 wl_stb_chg: 1;
2434 u32 pta_owner: 1;
2435 u32 tdma_instant_excute: 1;
2436
2437 u16 slot_dur[CXST_MAX];
2438
2439 u8 run_reason;
2440 u8 run_action;
2441
2442 u8 wl_lna2: 1;
2443 };
2444
2445 struct rtw89_btc_ctrl {
2446 u32 manual: 1;
2447 u32 igno_bt: 1;
2448 u32 always_freerun: 1;
2449 u32 trace_step: 16;
2450 u32 rsvd: 12;
2451 };
2452
2453 struct rtw89_btc_dbg {
2454 /* cmd "rb" */
2455 bool rb_done;
2456 u32 rb_val;
2457 };
2458
2459 enum rtw89_btc_btf_fw_event {
2460 BTF_EVNT_RPT = 0,
2461 BTF_EVNT_BT_INFO = 1,
2462 BTF_EVNT_BT_SCBD = 2,
2463 BTF_EVNT_BT_REG = 3,
2464 BTF_EVNT_CX_RUNINFO = 4,
2465 BTF_EVNT_BT_PSD = 5,
2466 BTF_EVNT_BUF_OVERFLOW,
2467 BTF_EVNT_C2H_LOOPBACK,
2468 BTF_EVNT_MAX,
2469 };
2470
2471 enum btf_fw_event_report {
2472 BTC_RPT_TYPE_CTRL = 0x0,
2473 BTC_RPT_TYPE_TDMA,
2474 BTC_RPT_TYPE_SLOT,
2475 BTC_RPT_TYPE_CYSTA,
2476 BTC_RPT_TYPE_STEP,
2477 BTC_RPT_TYPE_NULLSTA,
2478 BTC_RPT_TYPE_MREG,
2479 BTC_RPT_TYPE_GPIO_DBG,
2480 BTC_RPT_TYPE_BT_VER,
2481 BTC_RPT_TYPE_BT_SCAN,
2482 BTC_RPT_TYPE_BT_AFH,
2483 BTC_RPT_TYPE_BT_DEVICE,
2484 BTC_RPT_TYPE_TEST,
2485 BTC_RPT_TYPE_MAX = 31
2486 };
2487
2488 enum rtw_btc_btf_reg_type {
2489 REG_MAC = 0x0,
2490 REG_BB = 0x1,
2491 REG_RF = 0x2,
2492 REG_BT_RF = 0x3,
2493 REG_BT_MODEM = 0x4,
2494 REG_BT_BLUEWIZE = 0x5,
2495 REG_BT_VENDOR = 0x6,
2496 REG_BT_LE = 0x7,
2497 REG_MAX_TYPE,
2498 };
2499
2500 struct rtw89_btc_rpt_cmn_info {
2501 u32 rx_cnt;
2502 u32 rx_len;
2503 u32 req_len; /* expected rsp len */
2504 u8 req_fver; /* expected rsp fver */
2505 u8 rsp_fver; /* fver from fw */
2506 u8 valid;
2507 } __packed;
2508
2509 union rtw89_btc_fbtc_btafh_info {
2510 struct rtw89_btc_fbtc_btafh v1;
2511 struct rtw89_btc_fbtc_btafh_v2 v2;
2512 };
2513
2514 struct rtw89_btc_report_ctrl_state {
2515 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2516 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo;
2517 };
2518
2519 struct rtw89_btc_rpt_fbtc_tdma {
2520 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2521 union rtw89_btc_fbtc_tdma_le32 finfo;
2522 };
2523
2524 struct rtw89_btc_rpt_fbtc_slots {
2525 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2526 struct rtw89_btc_fbtc_slots finfo; /* info from fw */
2527 };
2528
2529 struct rtw89_btc_rpt_fbtc_cysta {
2530 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2531 union rtw89_btc_fbtc_cysta_info finfo;
2532 };
2533
2534 struct rtw89_btc_rpt_fbtc_step {
2535 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2536 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */
2537 };
2538
2539 struct rtw89_btc_rpt_fbtc_nullsta {
2540 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2541 union rtw89_btc_fbtc_cynullsta_info finfo;
2542 };
2543
2544 struct rtw89_btc_rpt_fbtc_mreg {
2545 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2546 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */
2547 };
2548
2549 struct rtw89_btc_rpt_fbtc_gpio_dbg {
2550 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2551 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */
2552 };
2553
2554 struct rtw89_btc_rpt_fbtc_btver {
2555 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2556 struct rtw89_btc_fbtc_btver finfo; /* info from fw */
2557 };
2558
2559 struct rtw89_btc_rpt_fbtc_btscan {
2560 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2561 union rtw89_btc_fbtc_btscan finfo; /* info from fw */
2562 };
2563
2564 struct rtw89_btc_rpt_fbtc_btafh {
2565 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2566 union rtw89_btc_fbtc_btafh_info finfo;
2567 };
2568
2569 struct rtw89_btc_rpt_fbtc_btdev {
2570 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2571 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */
2572 };
2573
2574 enum rtw89_btc_btfre_type {
2575 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */
2576 BTFRE_UNDEF_TYPE,
2577 BTFRE_EXCEPTION,
2578 BTFRE_MAX,
2579 };
2580
2581 struct rtw89_btc_btf_fwinfo {
2582 u32 cnt_c2h;
2583 u32 cnt_h2c;
2584 u32 cnt_h2c_fail;
2585 u32 event[BTF_EVNT_MAX];
2586
2587 u32 err[BTFRE_MAX];
2588 u32 len_mismch;
2589 u32 fver_mismch;
2590 u32 rpt_en_map;
2591
2592 struct rtw89_btc_report_ctrl_state rpt_ctrl;
2593 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma;
2594 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots;
2595 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta;
2596 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step;
2597 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta;
2598 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval;
2599 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg;
2600 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver;
2601 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan;
2602 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh;
2603 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev;
2604 };
2605
2606 struct rtw89_btc_ver {
2607 enum rtw89_core_chip_id chip_id;
2608 u32 fw_ver_code;
2609
2610 u8 fcxbtcrpt;
2611 u8 fcxtdma;
2612 u8 fcxslots;
2613 u8 fcxcysta;
2614 u8 fcxstep;
2615 u8 fcxnullsta;
2616 u8 fcxmreg;
2617 u8 fcxgpiodbg;
2618 u8 fcxbtver;
2619 u8 fcxbtscan;
2620 u8 fcxbtafh;
2621 u8 fcxbtdevinfo;
2622 u8 fwlrole;
2623 u8 frptmap;
2624 u8 fcxctrl;
2625
2626 u16 info_buf;
2627 u8 max_role_num;
2628 };
2629
2630 #define RTW89_BTC_POLICY_MAXLEN 512
2631
2632 struct rtw89_btc {
2633 const struct rtw89_btc_ver *ver;
2634
2635 struct rtw89_btc_cx cx;
2636 struct rtw89_btc_dm dm;
2637 struct rtw89_btc_ctrl ctrl;
2638 struct rtw89_btc_module mdinfo;
2639 struct rtw89_btc_btf_fwinfo fwinfo;
2640 struct rtw89_btc_dbg dbg;
2641
2642 struct work_struct eapol_notify_work;
2643 struct work_struct arp_notify_work;
2644 struct work_struct dhcp_notify_work;
2645 struct work_struct icmp_notify_work;
2646
2647 u32 bt_req_len;
2648
2649 u8 policy[RTW89_BTC_POLICY_MAXLEN];
2650 u16 policy_len;
2651 u16 policy_type;
2652 bool bt_req_en;
2653 bool update_policy_force;
2654 bool lps;
2655 };
2656
2657 enum rtw89_btc_hmsg {
2658 RTW89_BTC_HMSG_TMR_EN = 0x0,
2659 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1,
2660 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2,
2661 RTW89_BTC_HMSG_FW_EV = 0x3,
2662 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4,
2663 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5,
2664
2665 NUM_OF_RTW89_BTC_HMSG,
2666 };
2667
2668 enum rtw89_ra_mode {
2669 RTW89_RA_MODE_CCK = BIT(0),
2670 RTW89_RA_MODE_OFDM = BIT(1),
2671 RTW89_RA_MODE_HT = BIT(2),
2672 RTW89_RA_MODE_VHT = BIT(3),
2673 RTW89_RA_MODE_HE = BIT(4),
2674 };
2675
2676 enum rtw89_ra_report_mode {
2677 RTW89_RA_RPT_MODE_LEGACY,
2678 RTW89_RA_RPT_MODE_HT,
2679 RTW89_RA_RPT_MODE_VHT,
2680 RTW89_RA_RPT_MODE_HE,
2681 };
2682
2683 enum rtw89_dig_noisy_level {
2684 RTW89_DIG_NOISY_LEVEL0 = -1,
2685 RTW89_DIG_NOISY_LEVEL1 = 0,
2686 RTW89_DIG_NOISY_LEVEL2 = 1,
2687 RTW89_DIG_NOISY_LEVEL3 = 2,
2688 RTW89_DIG_NOISY_LEVEL_MAX = 3,
2689 };
2690
2691 enum rtw89_gi_ltf {
2692 RTW89_GILTF_LGI_4XHE32 = 0,
2693 RTW89_GILTF_SGI_4XHE08 = 1,
2694 RTW89_GILTF_2XHE16 = 2,
2695 RTW89_GILTF_2XHE08 = 3,
2696 RTW89_GILTF_1XHE16 = 4,
2697 RTW89_GILTF_1XHE08 = 5,
2698 RTW89_GILTF_MAX
2699 };
2700
2701 enum rtw89_rx_frame_type {
2702 RTW89_RX_TYPE_MGNT = 0,
2703 RTW89_RX_TYPE_CTRL = 1,
2704 RTW89_RX_TYPE_DATA = 2,
2705 RTW89_RX_TYPE_RSVD = 3,
2706 };
2707
2708 struct rtw89_ra_info {
2709 u8 is_dis_ra:1;
2710 /* Bit0 : CCK
2711 * Bit1 : OFDM
2712 * Bit2 : HT
2713 * Bit3 : VHT
2714 * Bit4 : HE
2715 * Bit5 : EHT
2716 */
2717 u8 mode_ctrl:6;
2718 u8 bw_cap:3; /* enum rtw89_bandwidth */
2719 u8 macid;
2720 u8 dcm_cap:1;
2721 u8 er_cap:1;
2722 u8 init_rate_lv:2;
2723 u8 upd_all:1;
2724 u8 en_sgi:1;
2725 u8 ldpc_cap:1;
2726 u8 stbc_cap:1;
2727 u8 ss_num:3;
2728 u8 giltf:3;
2729 u8 upd_bw_nss_mask:1;
2730 u8 upd_mask:1;
2731 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */
2732 /* BFee CSI */
2733 u8 band_num;
2734 u8 ra_csi_rate_en:1;
2735 u8 fixed_csi_rate_en:1;
2736 u8 cr_tbl_sel:1;
2737 u8 fix_giltf_en:1;
2738 u8 fix_giltf:3;
2739 u8 rsvd2:1;
2740 u8 csi_mcs_ss_idx;
2741 u8 csi_mode:2;
2742 u8 csi_gi_ltf:3;
2743 u8 csi_bw:3;
2744 };
2745
2746 #define RTW89_PPDU_MAX_USR 4
2747 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4
2748 #define RTW89_PPDU_MAC_INFO_SIZE 8
2749 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96
2750
2751 #define RTW89_MAX_RX_AGG_NUM 64
2752 #define RTW89_MAX_TX_AGG_NUM 128
2753
2754 struct rtw89_ampdu_params {
2755 u16 agg_num;
2756 bool amsdu;
2757 };
2758
2759 struct rtw89_ra_report {
2760 struct rate_info txrate;
2761 u32 bit_rate;
2762 u16 hw_rate;
2763 bool might_fallback_legacy;
2764 };
2765
2766 DECLARE_EWMA(rssi, 10, 16);
2767 DECLARE_EWMA(evm, 10, 16);
2768 DECLARE_EWMA(snr, 10, 16);
2769
2770 struct rtw89_ba_cam_entry {
2771 struct list_head list;
2772 u8 tid;
2773 };
2774
2775 #define RTW89_MAX_ADDR_CAM_NUM 128
2776 #define RTW89_MAX_BSSID_CAM_NUM 20
2777 #define RTW89_MAX_SEC_CAM_NUM 128
2778 #define RTW89_MAX_BA_CAM_NUM 8
2779 #define RTW89_SEC_CAM_IN_ADDR_CAM 7
2780
2781 struct rtw89_addr_cam_entry {
2782 u8 addr_cam_idx;
2783 u8 offset;
2784 u8 len;
2785 u8 valid : 1;
2786 u8 addr_mask : 6;
2787 u8 wapi : 1;
2788 u8 mask_sel : 2;
2789 u8 bssid_cam_idx: 6;
2790
2791 u8 sec_ent_mode;
2792 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM);
2793 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM];
2794 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM];
2795 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM];
2796 };
2797
2798 struct rtw89_bssid_cam_entry {
2799 u8 bssid[ETH_ALEN];
2800 u8 phy_idx;
2801 u8 bssid_cam_idx;
2802 u8 offset;
2803 u8 len;
2804 u8 valid : 1;
2805 u8 num;
2806 };
2807
2808 struct rtw89_sec_cam_entry {
2809 u8 sec_cam_idx;
2810 u8 offset;
2811 u8 len;
2812 u8 type : 4;
2813 u8 ext_key : 1;
2814 u8 spp_mode : 1;
2815 /* 256 bits */
2816 u8 key[32];
2817 };
2818
2819 struct rtw89_sta {
2820 u8 mac_id;
2821 bool disassoc;
2822 bool er_cap;
2823 struct rtw89_dev *rtwdev;
2824 struct rtw89_vif *rtwvif;
2825 struct rtw89_ra_info ra;
2826 struct rtw89_ra_report ra_report;
2827 int max_agg_wait;
2828 u8 prev_rssi;
2829 struct ewma_rssi avg_rssi;
2830 struct ewma_rssi rssi[RF_PATH_MAX];
2831 struct ewma_snr avg_snr;
2832 struct ewma_evm evm_min[RF_PATH_MAX];
2833 struct ewma_evm evm_max[RF_PATH_MAX];
2834 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];
2835 struct ieee80211_rx_status rx_status;
2836 u16 rx_hw_rate;
2837 __le32 htc_template;
2838 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */
2839 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */
2840 struct list_head ba_cam_list;
2841 struct sk_buff_head roc_queue;
2842
2843 bool use_cfg_mask;
2844 struct cfg80211_bitrate_mask mask;
2845
2846 bool cctl_tx_time;
2847 u32 ampdu_max_time:4;
2848 bool cctl_tx_retry_limit;
2849 u32 data_tx_cnt_lmt:6;
2850 };
2851
2852 struct rtw89_efuse {
2853 bool valid;
2854 bool power_k_valid;
2855 u8 xtal_cap;
2856 u8 addr[ETH_ALEN];
2857 u8 rfe_type;
2858 char country_code[2];
2859 };
2860
2861 struct rtw89_phy_rate_pattern {
2862 u64 ra_mask;
2863 u16 rate;
2864 u8 ra_mode;
2865 bool enable;
2866 };
2867
2868 struct rtw89_tx_wait_info {
2869 struct rcu_head rcu_head;
2870 struct completion completion;
2871 bool tx_done;
2872 };
2873
2874 struct rtw89_tx_skb_data {
2875 struct rtw89_tx_wait_info __rcu *wait;
2876 u8 hci_priv[];
2877 };
2878
2879 #define RTW89_ROC_IDLE_TIMEOUT 500
2880 #define RTW89_ROC_TX_TIMEOUT 30
2881 enum rtw89_roc_state {
2882 RTW89_ROC_IDLE,
2883 RTW89_ROC_NORMAL,
2884 RTW89_ROC_MGMT,
2885 };
2886
2887 struct rtw89_roc {
2888 struct ieee80211_channel chan;
2889 struct delayed_work roc_work;
2890 enum ieee80211_roc_type type;
2891 enum rtw89_roc_state state;
2892 int duration;
2893 };
2894
2895 #define RTW89_P2P_MAX_NOA_NUM 2
2896
2897 struct rtw89_p2p_ie_head {
2898 u8 eid;
2899 u8 ie_len;
2900 u8 oui[3];
2901 u8 oui_type;
2902 } __packed;
2903
2904 struct rtw89_noa_attr_head {
2905 u8 attr_type;
2906 __le16 attr_len;
2907 u8 index;
2908 u8 oppps_ctwindow;
2909 } __packed;
2910
2911 struct rtw89_p2p_noa_ie {
2912 struct rtw89_p2p_ie_head p2p_head;
2913 struct rtw89_noa_attr_head noa_head;
2914 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM];
2915 } __packed;
2916
2917 struct rtw89_p2p_noa_setter {
2918 struct rtw89_p2p_noa_ie ie;
2919 u8 noa_count;
2920 u8 noa_index;
2921 };
2922
2923 struct rtw89_vif {
2924 struct list_head list;
2925 struct rtw89_dev *rtwdev;
2926 struct rtw89_roc roc;
2927 enum rtw89_sub_entity_idx sub_entity_idx;
2928 enum rtw89_reg_6ghz_power reg_6ghz_power;
2929
2930 u8 mac_id;
2931 u8 port;
2932 u8 mac_addr[ETH_ALEN];
2933 u8 bssid[ETH_ALEN];
2934 u8 phy_idx;
2935 u8 mac_idx;
2936 u8 net_type;
2937 u8 wifi_role;
2938 u8 self_role;
2939 u8 wmm;
2940 u8 bcn_hit_cond;
2941 u8 hit_rule;
2942 u8 last_noa_nr;
2943 bool offchan;
2944 bool trigger;
2945 bool lsig_txop;
2946 u8 tgt_ind;
2947 u8 frm_tgt_ind;
2948 bool wowlan_pattern;
2949 bool wowlan_uc;
2950 bool wowlan_magic;
2951 bool is_hesta;
2952 bool last_a_ctrl;
2953 bool dyn_tb_bedge_en;
2954 u8 def_tri_idx;
2955 u32 tdls_peer;
2956 struct work_struct update_beacon_work;
2957 struct rtw89_addr_cam_entry addr_cam;
2958 struct rtw89_bssid_cam_entry bssid_cam;
2959 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
2960 struct rtw89_traffic_stats stats;
2961 struct rtw89_phy_rate_pattern rate_pattern;
2962 struct cfg80211_scan_request *scan_req;
2963 struct ieee80211_scan_ies *scan_ies;
2964 struct list_head general_pkt_list;
2965 struct rtw89_p2p_noa_setter p2p_noa;
2966 };
2967
2968 enum rtw89_lv1_rcvy_step {
2969 RTW89_LV1_RCVY_STEP_1,
2970 RTW89_LV1_RCVY_STEP_2,
2971 };
2972
2973 struct rtw89_hci_ops {
2974 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req);
2975 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch);
2976 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop);
2977 void (*reset)(struct rtw89_dev *rtwdev);
2978 int (*start)(struct rtw89_dev *rtwdev);
2979 void (*stop)(struct rtw89_dev *rtwdev);
2980 void (*pause)(struct rtw89_dev *rtwdev, bool pause);
2981 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power);
2982 void (*recalc_int_mit)(struct rtw89_dev *rtwdev);
2983
2984 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr);
2985 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr);
2986 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr);
2987 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data);
2988 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);
2989 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);
2990
2991 int (*mac_pre_init)(struct rtw89_dev *rtwdev);
2992 int (*mac_post_init)(struct rtw89_dev *rtwdev);
2993 int (*deinit)(struct rtw89_dev *rtwdev);
2994
2995 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch);
2996 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step);
2997 void (*dump_err_status)(struct rtw89_dev *rtwdev);
2998 int (*napi_poll)(struct napi_struct *napi, int budget);
2999
3000 /* Deal with locks inside recovery_start and recovery_complete callbacks
3001 * by hci instance, and handle things which need to consider under SER.
3002 * e.g. turn on/off interrupts except for the one for halt notification.
3003 */
3004 void (*recovery_start)(struct rtw89_dev *rtwdev);
3005 void (*recovery_complete)(struct rtw89_dev *rtwdev);
3006
3007 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable);
3008 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable);
3009 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable);
3010 int (*poll_txdma_ch)(struct rtw89_dev *rtwdev);
3011 void (*clr_idx_all)(struct rtw89_dev *rtwdev);
3012 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev);
3013 void (*disable_intr)(struct rtw89_dev *rtwdev);
3014 void (*enable_intr)(struct rtw89_dev *rtwdev);
3015 int (*rst_bdram)(struct rtw89_dev *rtwdev);
3016 };
3017
3018 struct rtw89_hci_info {
3019 const struct rtw89_hci_ops *ops;
3020 enum rtw89_hci_type type;
3021 u32 rpwm_addr;
3022 u32 cpwm_addr;
3023 bool paused;
3024 };
3025
3026 struct rtw89_chip_ops {
3027 int (*enable_bb_rf)(struct rtw89_dev *rtwdev);
3028 int (*disable_bb_rf)(struct rtw89_dev *rtwdev);
3029 void (*bb_reset)(struct rtw89_dev *rtwdev,
3030 enum rtw89_phy_idx phy_idx);
3031 void (*bb_sethw)(struct rtw89_dev *rtwdev);
3032 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3033 u32 addr, u32 mask);
3034 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3035 u32 addr, u32 mask, u32 data);
3036 void (*set_channel)(struct rtw89_dev *rtwdev,
3037 const struct rtw89_chan *chan,
3038 enum rtw89_mac_idx mac_idx,
3039 enum rtw89_phy_idx phy_idx);
3040 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter,
3041 struct rtw89_channel_help_params *p,
3042 const struct rtw89_chan *chan,
3043 enum rtw89_mac_idx mac_idx,
3044 enum rtw89_phy_idx phy_idx);
3045 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map);
3046 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
3047 void (*fem_setup)(struct rtw89_dev *rtwdev);
3048 void (*rfe_gpio)(struct rtw89_dev *rtwdev);
3049 void (*rfk_init)(struct rtw89_dev *rtwdev);
3050 void (*rfk_channel)(struct rtw89_dev *rtwdev);
3051 void (*rfk_band_changed)(struct rtw89_dev *rtwdev,
3052 enum rtw89_phy_idx phy_idx);
3053 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start);
3054 void (*rfk_track)(struct rtw89_dev *rtwdev);
3055 void (*power_trim)(struct rtw89_dev *rtwdev);
3056 void (*set_txpwr)(struct rtw89_dev *rtwdev,
3057 const struct rtw89_chan *chan,
3058 enum rtw89_phy_idx phy_idx);
3059 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev,
3060 enum rtw89_phy_idx phy_idx);
3061 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3062 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path);
3063 void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg);
3064 void (*query_ppdu)(struct rtw89_dev *rtwdev,
3065 struct rtw89_rx_phy_ppdu *phy_ppdu,
3066 struct ieee80211_rx_status *status);
3067 void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en);
3068 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev);
3069 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev,
3070 s8 pw_ofst, enum rtw89_mac_idx mac_idx);
3071 int (*pwr_on_func)(struct rtw89_dev *rtwdev);
3072 int (*pwr_off_func)(struct rtw89_dev *rtwdev);
3073 void (*query_rxdesc)(struct rtw89_dev *rtwdev,
3074 struct rtw89_rx_desc_info *desc_info,
3075 u8 *data, u32 data_offset);
3076 void (*fill_txdesc)(struct rtw89_dev *rtwdev,
3077 struct rtw89_tx_desc_info *desc_info,
3078 void *txdesc);
3079 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev,
3080 struct rtw89_tx_desc_info *desc_info,
3081 void *txdesc);
3082 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl);
3083 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev,
3084 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
3085 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx,
3086 u32 *tx_en, enum rtw89_sch_tx_sel sel);
3087 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
3088 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev,
3089 struct rtw89_vif *rtwvif,
3090 struct rtw89_sta *rtwsta);
3091
3092 void (*btc_set_rfe)(struct rtw89_dev *rtwdev);
3093 void (*btc_init_cfg)(struct rtw89_dev *rtwdev);
3094 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
3095 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);
3096 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
3097 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
3098 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
3099 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type);
3100 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level);
3101 };
3102
3103 enum rtw89_dma_ch {
3104 RTW89_DMA_ACH0 = 0,
3105 RTW89_DMA_ACH1 = 1,
3106 RTW89_DMA_ACH2 = 2,
3107 RTW89_DMA_ACH3 = 3,
3108 RTW89_DMA_ACH4 = 4,
3109 RTW89_DMA_ACH5 = 5,
3110 RTW89_DMA_ACH6 = 6,
3111 RTW89_DMA_ACH7 = 7,
3112 RTW89_DMA_B0MG = 8,
3113 RTW89_DMA_B0HI = 9,
3114 RTW89_DMA_B1MG = 10,
3115 RTW89_DMA_B1HI = 11,
3116 RTW89_DMA_H2C = 12,
3117 RTW89_DMA_CH_NUM = 13
3118 };
3119
3120 enum rtw89_qta_mode {
3121 RTW89_QTA_SCC,
3122 RTW89_QTA_DLFW,
3123 RTW89_QTA_WOW,
3124
3125 /* keep last */
3126 RTW89_QTA_INVALID,
3127 };
3128
3129 struct rtw89_hfc_ch_cfg {
3130 u16 min;
3131 u16 max;
3132 #define grp_0 0
3133 #define grp_1 1
3134 #define grp_num 2
3135 u8 grp;
3136 };
3137
3138 struct rtw89_hfc_ch_info {
3139 u16 aval;
3140 u16 used;
3141 };
3142
3143 struct rtw89_hfc_pub_cfg {
3144 u16 grp0;
3145 u16 grp1;
3146 u16 pub_max;
3147 u16 wp_thrd;
3148 };
3149
3150 struct rtw89_hfc_pub_info {
3151 u16 g0_used;
3152 u16 g1_used;
3153 u16 g0_aval;
3154 u16 g1_aval;
3155 u16 pub_aval;
3156 u16 wp_aval;
3157 };
3158
3159 struct rtw89_hfc_prec_cfg {
3160 u16 ch011_prec;
3161 u16 h2c_prec;
3162 u16 wp_ch07_prec;
3163 u16 wp_ch811_prec;
3164 u8 ch011_full_cond;
3165 u8 h2c_full_cond;
3166 u8 wp_ch07_full_cond;
3167 u8 wp_ch811_full_cond;
3168 };
3169
3170 struct rtw89_hfc_param {
3171 bool en;
3172 bool h2c_en;
3173 u8 mode;
3174 const struct rtw89_hfc_ch_cfg *ch_cfg;
3175 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM];
3176 struct rtw89_hfc_pub_cfg pub_cfg;
3177 struct rtw89_hfc_pub_info pub_info;
3178 struct rtw89_hfc_prec_cfg prec_cfg;
3179 };
3180
3181 struct rtw89_hfc_param_ini {
3182 const struct rtw89_hfc_ch_cfg *ch_cfg;
3183 const struct rtw89_hfc_pub_cfg *pub_cfg;
3184 const struct rtw89_hfc_prec_cfg *prec_cfg;
3185 u8 mode;
3186 };
3187
3188 struct rtw89_dle_size {
3189 u16 pge_size;
3190 u16 lnk_pge_num;
3191 u16 unlnk_pge_num;
3192 };
3193
3194 struct rtw89_wde_quota {
3195 u16 hif;
3196 u16 wcpu;
3197 u16 pkt_in;
3198 u16 cpu_io;
3199 };
3200
3201 struct rtw89_ple_quota {
3202 u16 cma0_tx;
3203 u16 cma1_tx;
3204 u16 c2h;
3205 u16 h2c;
3206 u16 wcpu;
3207 u16 mpdu_proc;
3208 u16 cma0_dma;
3209 u16 cma1_dma;
3210 u16 bb_rpt;
3211 u16 wd_rel;
3212 u16 cpu_io;
3213 u16 tx_rpt;
3214 };
3215
3216 struct rtw89_dle_mem {
3217 enum rtw89_qta_mode mode;
3218 const struct rtw89_dle_size *wde_size;
3219 const struct rtw89_dle_size *ple_size;
3220 const struct rtw89_wde_quota *wde_min_qt;
3221 const struct rtw89_wde_quota *wde_max_qt;
3222 const struct rtw89_ple_quota *ple_min_qt;
3223 const struct rtw89_ple_quota *ple_max_qt;
3224 };
3225
3226 struct rtw89_reg_def {
3227 u32 addr;
3228 u32 mask;
3229 };
3230
3231 struct rtw89_reg2_def {
3232 u32 addr;
3233 u32 data;
3234 };
3235
3236 struct rtw89_reg3_def {
3237 u32 addr;
3238 u32 mask;
3239 u32 data;
3240 };
3241
3242 struct rtw89_reg5_def {
3243 u8 flag; /* recognized by parsers */
3244 u8 path;
3245 u32 addr;
3246 u32 mask;
3247 u32 data;
3248 };
3249
3250 struct rtw89_phy_table {
3251 const struct rtw89_reg2_def *regs;
3252 u32 n_regs;
3253 enum rtw89_rf_path rf_path;
3254 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
3255 enum rtw89_rf_path rf_path, void *data);
3256 };
3257
3258 struct rtw89_txpwr_table {
3259 const void *data;
3260 u32 size;
3261 void (*load)(struct rtw89_dev *rtwdev,
3262 const struct rtw89_txpwr_table *tbl);
3263 };
3264
3265 struct rtw89_txpwr_rule_2ghz {
3266 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
3267 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3268 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3269 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3270 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3271 };
3272
3273 struct rtw89_txpwr_rule_5ghz {
3274 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
3275 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3276 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3277 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3278 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3279 };
3280
3281 struct rtw89_txpwr_rule_6ghz {
3282 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
3283 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3284 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3285 [RTW89_6G_CH_NUM];
3286 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3287 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3288 [RTW89_6G_CH_NUM];
3289 };
3290
3291 struct rtw89_rfe_parms {
3292 struct rtw89_txpwr_rule_2ghz rule_2ghz;
3293 struct rtw89_txpwr_rule_5ghz rule_5ghz;
3294 struct rtw89_txpwr_rule_6ghz rule_6ghz;
3295 };
3296
3297 struct rtw89_rfe_parms_conf {
3298 const struct rtw89_rfe_parms *rfe_parms;
3299 u8 rfe_type;
3300 };
3301
3302 struct rtw89_page_regs {
3303 u32 hci_fc_ctrl;
3304 u32 ch_page_ctrl;
3305 u32 ach_page_ctrl;
3306 u32 ach_page_info;
3307 u32 pub_page_info3;
3308 u32 pub_page_ctrl1;
3309 u32 pub_page_ctrl2;
3310 u32 pub_page_info1;
3311 u32 pub_page_info2;
3312 u32 wp_page_ctrl1;
3313 u32 wp_page_ctrl2;
3314 u32 wp_page_info1;
3315 };
3316
3317 struct rtw89_imr_info {
3318 u32 wdrls_imr_set;
3319 u32 wsec_imr_reg;
3320 u32 wsec_imr_set;
3321 u32 mpdu_tx_imr_set;
3322 u32 mpdu_rx_imr_set;
3323 u32 sta_sch_imr_set;
3324 u32 txpktctl_imr_b0_reg;
3325 u32 txpktctl_imr_b0_clr;
3326 u32 txpktctl_imr_b0_set;
3327 u32 txpktctl_imr_b1_reg;
3328 u32 txpktctl_imr_b1_clr;
3329 u32 txpktctl_imr_b1_set;
3330 u32 wde_imr_clr;
3331 u32 wde_imr_set;
3332 u32 ple_imr_clr;
3333 u32 ple_imr_set;
3334 u32 host_disp_imr_clr;
3335 u32 host_disp_imr_set;
3336 u32 cpu_disp_imr_clr;
3337 u32 cpu_disp_imr_set;
3338 u32 other_disp_imr_clr;
3339 u32 other_disp_imr_set;
3340 u32 bbrpt_com_err_imr_reg;
3341 u32 bbrpt_chinfo_err_imr_reg;
3342 u32 bbrpt_err_imr_set;
3343 u32 bbrpt_dfs_err_imr_reg;
3344 u32 ptcl_imr_clr;
3345 u32 ptcl_imr_set;
3346 u32 cdma_imr_0_reg;
3347 u32 cdma_imr_0_clr;
3348 u32 cdma_imr_0_set;
3349 u32 cdma_imr_1_reg;
3350 u32 cdma_imr_1_clr;
3351 u32 cdma_imr_1_set;
3352 u32 phy_intf_imr_reg;
3353 u32 phy_intf_imr_clr;
3354 u32 phy_intf_imr_set;
3355 u32 rmac_imr_reg;
3356 u32 rmac_imr_clr;
3357 u32 rmac_imr_set;
3358 u32 tmac_imr_reg;
3359 u32 tmac_imr_clr;
3360 u32 tmac_imr_set;
3361 };
3362
3363 struct rtw89_xtal_info {
3364 u32 xcap_reg;
3365 u32 sc_xo_mask;
3366 u32 sc_xi_mask;
3367 };
3368
3369 struct rtw89_rrsr_cfgs {
3370 struct rtw89_reg3_def ref_rate;
3371 struct rtw89_reg3_def rsc;
3372 };
3373
3374 struct rtw89_dig_regs {
3375 u32 seg0_pd_reg;
3376 u32 pd_lower_bound_mask;
3377 u32 pd_spatial_reuse_en;
3378 u32 bmode_pd_reg;
3379 u32 bmode_cca_rssi_limit_en;
3380 u32 bmode_pd_lower_bound_reg;
3381 u32 bmode_rssi_nocca_low_th_mask;
3382 struct rtw89_reg_def p0_lna_init;
3383 struct rtw89_reg_def p1_lna_init;
3384 struct rtw89_reg_def p0_tia_init;
3385 struct rtw89_reg_def p1_tia_init;
3386 struct rtw89_reg_def p0_rxb_init;
3387 struct rtw89_reg_def p1_rxb_init;
3388 struct rtw89_reg_def p0_p20_pagcugc_en;
3389 struct rtw89_reg_def p0_s20_pagcugc_en;
3390 struct rtw89_reg_def p1_p20_pagcugc_en;
3391 struct rtw89_reg_def p1_s20_pagcugc_en;
3392 };
3393
3394 struct rtw89_phy_ul_tb_info {
3395 bool dyn_tb_tri_en;
3396 u8 def_if_bandedge;
3397 };
3398
3399 struct rtw89_antdiv_stats {
3400 struct ewma_rssi cck_rssi_avg;
3401 struct ewma_rssi ofdm_rssi_avg;
3402 struct ewma_rssi non_legacy_rssi_avg;
3403 u16 pkt_cnt_cck;
3404 u16 pkt_cnt_ofdm;
3405 u16 pkt_cnt_non_legacy;
3406 u32 evm;
3407 };
3408
3409 struct rtw89_antdiv_info {
3410 struct rtw89_antdiv_stats target_stats;
3411 struct rtw89_antdiv_stats main_stats;
3412 struct rtw89_antdiv_stats aux_stats;
3413 u8 training_count;
3414 u8 rssi_pre;
3415 bool get_stats;
3416 };
3417
3418 enum rtw89_chanctx_state {
3419 RTW89_CHANCTX_STATE_MCC_START,
3420 RTW89_CHANCTX_STATE_MCC_STOP,
3421 };
3422
3423 enum rtw89_chanctx_callbacks {
3424 RTW89_CHANCTX_CALLBACK_PLACEHOLDER,
3425
3426 NUM_OF_RTW89_CHANCTX_CALLBACKS,
3427 };
3428
3429 struct rtw89_chanctx_listener {
3430 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS])
3431 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state);
3432 };
3433
3434 struct rtw89_chip_info {
3435 enum rtw89_core_chip_id chip_id;
3436 enum rtw89_chip_gen chip_gen;
3437 const struct rtw89_chip_ops *ops;
3438 const struct rtw89_mac_gen_def *mac_def;
3439 const struct rtw89_phy_gen_def *phy_def;
3440 const char *fw_basename;
3441 u8 fw_format_max;
3442 bool try_ce_fw;
3443 u32 needed_fw_elms;
3444 u32 fifo_size;
3445 bool small_fifo_size;
3446 u32 dle_scc_rsvd_size;
3447 u16 max_amsdu_limit;
3448 bool dis_2g_40m_ul_ofdma;
3449 u32 rsvd_ple_ofst;
3450 const struct rtw89_hfc_param_ini *hfc_param_ini;
3451 const struct rtw89_dle_mem *dle_mem;
3452 u8 wde_qempty_acq_num;
3453 u8 wde_qempty_mgq_sel;
3454 u32 rf_base_addr[2];
3455 u8 support_chanctx_num;
3456 u8 support_bands;
3457 bool support_bw160;
3458 bool support_unii4;
3459 bool support_ul_tb_ctrl;
3460 bool hw_sec_hdr;
3461 u8 rf_path_num;
3462 u8 tx_nss;
3463 u8 rx_nss;
3464 u8 acam_num;
3465 u8 bcam_num;
3466 u8 scam_num;
3467 u8 bacam_num;
3468 u8 bacam_dynamic_num;
3469 enum rtw89_bacam_ver bacam_ver;
3470
3471 u8 sec_ctrl_efuse_size;
3472 u32 physical_efuse_size;
3473 u32 logical_efuse_size;
3474 u32 limit_efuse_size;
3475 u32 dav_phy_efuse_size;
3476 u32 dav_log_efuse_size;
3477 u32 phycap_addr;
3478 u32 phycap_size;
3479
3480 const struct rtw89_pwr_cfg * const *pwr_on_seq;
3481 const struct rtw89_pwr_cfg * const *pwr_off_seq;
3482 const struct rtw89_phy_table *bb_table;
3483 const struct rtw89_phy_table *bb_gain_table;
3484 const struct rtw89_phy_table *rf_table[RF_PATH_MAX];
3485 const struct rtw89_phy_table *nctl_table;
3486 const struct rtw89_rfk_tbl *nctl_post_table;
3487 const struct rtw89_txpwr_table *byr_table;
3488 const struct rtw89_phy_dig_gain_table *dig_table;
3489 const struct rtw89_dig_regs *dig_regs;
3490 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table;
3491
3492 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */
3493 const struct rtw89_rfe_parms_conf *rfe_parms_conf;
3494 const struct rtw89_rfe_parms *dflt_parms;
3495 const struct rtw89_chanctx_listener *chanctx_listener;
3496
3497 u8 txpwr_factor_rf;
3498 u8 txpwr_factor_mac;
3499
3500 u32 para_ver;
3501 u32 wlcx_desired;
3502 u8 btcx_desired;
3503 u8 scbd;
3504 u8 mailbox;
3505
3506 u8 afh_guard_ch;
3507 const u8 *wl_rssi_thres;
3508 const u8 *bt_rssi_thres;
3509 u8 rssi_tol;
3510
3511 u8 mon_reg_num;
3512 const struct rtw89_btc_fbtc_mreg *mon_reg;
3513 u8 rf_para_ulink_num;
3514 const struct rtw89_btc_rf_trx_para *rf_para_ulink;
3515 u8 rf_para_dlink_num;
3516 const struct rtw89_btc_rf_trx_para *rf_para_dlink;
3517 u8 ps_mode_supported;
3518 u8 low_power_hci_modes;
3519
3520 u32 h2c_cctl_func_id;
3521 u32 hci_func_en_addr;
3522 u32 h2c_desc_size;
3523 u32 txwd_body_size;
3524 u32 h2c_ctrl_reg;
3525 const u32 *h2c_regs;
3526 struct rtw89_reg_def h2c_counter_reg;
3527 u32 c2h_ctrl_reg;
3528 const u32 *c2h_regs;
3529 struct rtw89_reg_def c2h_counter_reg;
3530 const struct rtw89_page_regs *page_regs;
3531 bool cfo_src_fd;
3532 bool cfo_hw_comp;
3533 const struct rtw89_reg_def *dcfo_comp;
3534 u8 dcfo_comp_sft;
3535 const struct rtw89_imr_info *imr_info;
3536 const struct rtw89_rrsr_cfgs *rrsr_cfgs;
3537 u32 bss_clr_map_reg;
3538 u32 dma_ch_mask;
3539 u32 edcca_lvl_reg;
3540 const struct wiphy_wowlan_support *wowlan_stub;
3541 const struct rtw89_xtal_info *xtal_info;
3542 };
3543
3544 union rtw89_bus_info {
3545 const struct rtw89_pci_info *pci;
3546 };
3547
3548 struct rtw89_driver_info {
3549 const struct rtw89_chip_info *chip;
3550 union rtw89_bus_info bus;
3551 };
3552
3553 enum rtw89_hcifc_mode {
3554 RTW89_HCIFC_POH = 0,
3555 RTW89_HCIFC_STF = 1,
3556 RTW89_HCIFC_SDIO = 2,
3557
3558 /* keep last */
3559 RTW89_HCIFC_MODE_INVALID,
3560 };
3561
3562 struct rtw89_dle_info {
3563 enum rtw89_qta_mode qta_mode;
3564 u16 ple_pg_size;
3565 u16 c0_rx_qta;
3566 u16 c1_rx_qta;
3567 };
3568
3569 enum rtw89_host_rpr_mode {
3570 RTW89_RPR_MODE_POH = 0,
3571 RTW89_RPR_MODE_STF
3572 };
3573
3574 #define RTW89_COMPLETION_BUF_SIZE 24
3575 #define RTW89_WAIT_COND_IDLE UINT_MAX
3576
3577 struct rtw89_completion_data {
3578 bool err;
3579 u8 buf[RTW89_COMPLETION_BUF_SIZE];
3580 };
3581
3582 struct rtw89_wait_info {
3583 atomic_t cond;
3584 struct completion completion;
3585 struct rtw89_completion_data data;
3586 };
3587
3588 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100)
3589
rtw89_init_wait(struct rtw89_wait_info * wait)3590 static inline void rtw89_init_wait(struct rtw89_wait_info *wait)
3591 {
3592 init_completion(&wait->completion);
3593 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
3594 }
3595
3596 struct rtw89_mac_info {
3597 struct rtw89_dle_info dle_info;
3598 struct rtw89_hfc_param hfc_param;
3599 enum rtw89_qta_mode qta_mode;
3600 u8 rpwm_seq_num;
3601 u8 cpwm_seq_num;
3602
3603 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */
3604 struct rtw89_wait_info fw_ofld_wait;
3605 };
3606
3607 enum rtw89_fw_type {
3608 RTW89_FW_NORMAL = 1,
3609 RTW89_FW_WOWLAN = 3,
3610 RTW89_FW_NORMAL_CE = 5,
3611 RTW89_FW_BBMCU0 = 64,
3612 RTW89_FW_BBMCU1 = 65,
3613 RTW89_FW_LOGFMT = 255,
3614 };
3615
3616 enum rtw89_fw_feature {
3617 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT,
3618 RTW89_FW_FEATURE_SCAN_OFFLOAD,
3619 RTW89_FW_FEATURE_TX_WAKE,
3620 RTW89_FW_FEATURE_CRASH_TRIGGER,
3621 RTW89_FW_FEATURE_NO_PACKET_DROP,
3622 RTW89_FW_FEATURE_NO_DEEP_PS,
3623 RTW89_FW_FEATURE_NO_LPS_PG,
3624 RTW89_FW_FEATURE_BEACON_FILTER,
3625 };
3626
3627 struct rtw89_fw_suit {
3628 enum rtw89_fw_type type;
3629 const u8 *data;
3630 u32 size;
3631 u8 major_ver;
3632 u8 minor_ver;
3633 u8 sub_ver;
3634 u8 sub_idex;
3635 u16 build_year;
3636 u16 build_mon;
3637 u16 build_date;
3638 u16 build_hour;
3639 u16 build_min;
3640 u8 cmd_ver;
3641 u8 hdr_ver;
3642 u32 commitid;
3643 };
3644
3645 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \
3646 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx))
3647 #define RTW89_FW_SUIT_VER_CODE(s) \
3648 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex)
3649
3650 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \
3651 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \
3652 (mfw_hdr)->ver.minor, \
3653 (mfw_hdr)->ver.sub, \
3654 (mfw_hdr)->ver.idx)
3655
3656 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \
3657 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \
3658 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \
3659 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \
3660 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX))
3661
3662 struct rtw89_fw_req_info {
3663 const struct firmware *firmware;
3664 struct completion completion;
3665 };
3666
3667 struct rtw89_fw_log {
3668 struct rtw89_fw_suit suit;
3669 bool enable;
3670 u32 last_fmt_id;
3671 u32 fmt_count;
3672 const __le32 *fmt_ids;
3673 const char *(*fmts)[];
3674 };
3675
3676 struct rtw89_fw_elm_info {
3677 struct rtw89_phy_table *bb_tbl;
3678 struct rtw89_phy_table *bb_gain;
3679 struct rtw89_phy_table *rf_radio[RF_PATH_MAX];
3680 struct rtw89_phy_table *rf_nctl;
3681 };
3682
3683 struct rtw89_fw_info {
3684 struct rtw89_fw_req_info req;
3685 int fw_format;
3686 u8 h2c_seq;
3687 u8 rec_seq;
3688 u8 h2c_counter;
3689 u8 c2h_counter;
3690 struct rtw89_fw_suit normal;
3691 struct rtw89_fw_suit wowlan;
3692 struct rtw89_fw_suit bbmcu0;
3693 struct rtw89_fw_suit bbmcu1;
3694 struct rtw89_fw_log log;
3695 u32 feature_map;
3696 struct rtw89_fw_elm_info elm_info;
3697 };
3698
3699 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \
3700 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat)))
3701
3702 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \
3703 ((_fw)->feature_map |= BIT(_fw_feature))
3704
3705 struct rtw89_cam_info {
3706 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM);
3707 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM);
3708 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
3709 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM);
3710 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM];
3711 };
3712
3713 enum rtw89_sar_sources {
3714 RTW89_SAR_SOURCE_NONE,
3715 RTW89_SAR_SOURCE_COMMON,
3716
3717 RTW89_SAR_SOURCE_NR,
3718 };
3719
3720 enum rtw89_sar_subband {
3721 RTW89_SAR_2GHZ_SUBBAND,
3722 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */
3723 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */
3724 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */
3725 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
3726 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
3727 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */
3728 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
3729 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
3730 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */
3731
3732 RTW89_SAR_SUBBAND_NR,
3733 };
3734
3735 struct rtw89_sar_cfg_common {
3736 bool set[RTW89_SAR_SUBBAND_NR];
3737 s32 cfg[RTW89_SAR_SUBBAND_NR];
3738 };
3739
3740 struct rtw89_sar_info {
3741 /* used to decide how to acces SAR cfg union */
3742 enum rtw89_sar_sources src;
3743
3744 /* reserved for different knids of SAR cfg struct.
3745 * supposed that a single cfg struct cannot handle various SAR sources.
3746 */
3747 union {
3748 struct rtw89_sar_cfg_common cfg_common;
3749 };
3750 };
3751
3752 enum rtw89_tas_state {
3753 RTW89_TAS_STATE_DPR_OFF,
3754 RTW89_TAS_STATE_DPR_ON,
3755 RTW89_TAS_STATE_DPR_FORBID,
3756 };
3757
3758 #define RTW89_TAS_MAX_WINDOW 50
3759 struct rtw89_tas_info {
3760 s16 txpwr_history[RTW89_TAS_MAX_WINDOW];
3761 s32 total_txpwr;
3762 u8 cur_idx;
3763 s8 dpr_gap;
3764 s8 delta;
3765 enum rtw89_tas_state state;
3766 bool enable;
3767 };
3768
3769 struct rtw89_chanctx_cfg {
3770 enum rtw89_sub_entity_idx idx;
3771 };
3772
3773 enum rtw89_entity_mode {
3774 RTW89_ENTITY_MODE_SCC,
3775 RTW89_ENTITY_MODE_MCC_PREPARE,
3776 RTW89_ENTITY_MODE_MCC,
3777
3778 NUM_OF_RTW89_ENTITY_MODE,
3779 RTW89_ENTITY_MODE_INVALID = NUM_OF_RTW89_ENTITY_MODE,
3780 };
3781
3782 struct rtw89_sub_entity {
3783 struct cfg80211_chan_def chandef;
3784 struct rtw89_chan chan;
3785 struct rtw89_chan_rcd rcd;
3786 struct rtw89_chanctx_cfg *cfg;
3787 };
3788
3789 struct rtw89_hal {
3790 u32 rx_fltr;
3791 u8 cv;
3792 u8 acv;
3793 u32 antenna_tx;
3794 u32 antenna_rx;
3795 u8 tx_nss;
3796 u8 rx_nss;
3797 bool tx_path_diversity;
3798 bool ant_diversity;
3799 bool ant_diversity_fixed;
3800 bool support_cckpd;
3801 bool support_igi;
3802 atomic_t roc_entity_idx;
3803
3804 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY);
3805 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY];
3806 struct cfg80211_chan_def roc_chandef;
3807
3808 bool entity_active;
3809 enum rtw89_entity_mode entity_mode;
3810
3811 u32 edcca_bak;
3812 };
3813
3814 #define RTW89_MAX_MAC_ID_NUM 128
3815 #define RTW89_MAX_PKT_OFLD_NUM 255
3816
3817 enum rtw89_flags {
3818 RTW89_FLAG_POWERON,
3819 RTW89_FLAG_FW_RDY,
3820 RTW89_FLAG_RUNNING,
3821 RTW89_FLAG_BFEE_MON,
3822 RTW89_FLAG_BFEE_EN,
3823 RTW89_FLAG_BFEE_TIMER_KEEP,
3824 RTW89_FLAG_NAPI_RUNNING,
3825 RTW89_FLAG_LEISURE_PS,
3826 RTW89_FLAG_LOW_POWER_MODE,
3827 RTW89_FLAG_INACTIVE_PS,
3828 RTW89_FLAG_CRASH_SIMULATING,
3829 RTW89_FLAG_SER_HANDLING,
3830 RTW89_FLAG_WOWLAN,
3831 RTW89_FLAG_FORBIDDEN_TRACK_WROK,
3832 RTW89_FLAG_CHANGING_INTERFACE,
3833
3834 NUM_OF_RTW89_FLAGS,
3835 };
3836
3837 enum rtw89_pkt_drop_sel {
3838 RTW89_PKT_DROP_SEL_MACID_BE_ONCE,
3839 RTW89_PKT_DROP_SEL_MACID_BK_ONCE,
3840 RTW89_PKT_DROP_SEL_MACID_VI_ONCE,
3841 RTW89_PKT_DROP_SEL_MACID_VO_ONCE,
3842 RTW89_PKT_DROP_SEL_MACID_ALL,
3843 RTW89_PKT_DROP_SEL_MG0_ONCE,
3844 RTW89_PKT_DROP_SEL_HIQ_ONCE,
3845 RTW89_PKT_DROP_SEL_HIQ_PORT,
3846 RTW89_PKT_DROP_SEL_HIQ_MBSSID,
3847 RTW89_PKT_DROP_SEL_BAND,
3848 RTW89_PKT_DROP_SEL_BAND_ONCE,
3849 RTW89_PKT_DROP_SEL_REL_MACID,
3850 RTW89_PKT_DROP_SEL_REL_HIQ_PORT,
3851 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID,
3852 };
3853
3854 struct rtw89_pkt_drop_params {
3855 enum rtw89_pkt_drop_sel sel;
3856 enum rtw89_mac_idx mac_band;
3857 u8 macid;
3858 u8 port;
3859 u8 mbssid;
3860 bool tf_trs;
3861 u32 macid_band_sel[4];
3862 };
3863
3864 struct rtw89_pkt_stat {
3865 u16 beacon_nr;
3866 u32 rx_rate_cnt[RTW89_HW_RATE_NR];
3867 };
3868
3869 DECLARE_EWMA(thermal, 4, 4);
3870
3871 struct rtw89_phy_stat {
3872 struct ewma_thermal avg_thermal[RF_PATH_MAX];
3873 struct rtw89_pkt_stat cur_pkt_stat;
3874 struct rtw89_pkt_stat last_pkt_stat;
3875 };
3876
3877 #define RTW89_DACK_PATH_NR 2
3878 #define RTW89_DACK_IDX_NR 2
3879 #define RTW89_DACK_MSBK_NR 16
3880 struct rtw89_dack_info {
3881 bool dack_done;
3882 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR];
3883 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
3884 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
3885 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
3886 u32 dack_cnt;
3887 bool addck_timeout[RTW89_DACK_PATH_NR];
3888 bool dadck_timeout[RTW89_DACK_PATH_NR];
3889 bool msbk_timeout[RTW89_DACK_PATH_NR];
3890 };
3891
3892 #define RTW89_IQK_CHS_NR 2
3893 #define RTW89_IQK_PATH_NR 4
3894
3895 struct rtw89_rfk_mcc_info {
3896 u8 ch[RTW89_IQK_CHS_NR];
3897 u8 band[RTW89_IQK_CHS_NR];
3898 u8 table_idx;
3899 };
3900
3901 struct rtw89_lck_info {
3902 u8 thermal[RF_PATH_MAX];
3903 };
3904
3905 struct rtw89_rx_dck_info {
3906 u8 thermal[RF_PATH_MAX];
3907 };
3908
3909 struct rtw89_iqk_info {
3910 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3911 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3912 bool lok_fail[RTW89_IQK_PATH_NR];
3913 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3914 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3915 u32 iqk_fail_cnt;
3916 bool is_iqk_init;
3917 u32 iqk_channel[RTW89_IQK_CHS_NR];
3918 u8 iqk_band[RTW89_IQK_PATH_NR];
3919 u8 iqk_ch[RTW89_IQK_PATH_NR];
3920 u8 iqk_bw[RTW89_IQK_PATH_NR];
3921 u8 iqk_times;
3922 u8 version;
3923 u32 nb_txcfir[RTW89_IQK_PATH_NR];
3924 u32 nb_rxcfir[RTW89_IQK_PATH_NR];
3925 u32 bp_txkresult[RTW89_IQK_PATH_NR];
3926 u32 bp_rxkresult[RTW89_IQK_PATH_NR];
3927 u32 bp_iqkenable[RTW89_IQK_PATH_NR];
3928 bool is_wb_txiqk[RTW89_IQK_PATH_NR];
3929 bool is_wb_rxiqk[RTW89_IQK_PATH_NR];
3930 bool is_nbiqk;
3931 bool iqk_fft_en;
3932 bool iqk_xym_en;
3933 bool iqk_sram_en;
3934 bool iqk_cfir_en;
3935 u32 syn1to2;
3936 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3937 u8 iqk_table_idx[RTW89_IQK_PATH_NR];
3938 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3939 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3940 };
3941
3942 #define RTW89_DPK_RF_PATH 2
3943 #define RTW89_DPK_AVG_THERMAL_NUM 8
3944 #define RTW89_DPK_BKUP_NUM 2
3945 struct rtw89_dpk_bkup_para {
3946 enum rtw89_band band;
3947 enum rtw89_bandwidth bw;
3948 u8 ch;
3949 bool path_ok;
3950 u8 mdpd_en;
3951 u8 txagc_dpk;
3952 u8 ther_dpk;
3953 u8 gs;
3954 u16 pwsf;
3955 };
3956
3957 struct rtw89_dpk_info {
3958 bool is_dpk_enable;
3959 bool is_dpk_reload_en;
3960 u8 dpk_gs[RTW89_PHY_MAX];
3961 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3962 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3963 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3964 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3965 u8 cur_idx[RTW89_DPK_RF_PATH];
3966 u8 cur_k_set;
3967 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3968 };
3969
3970 struct rtw89_fem_info {
3971 bool elna_2g;
3972 bool elna_5g;
3973 bool epa_2g;
3974 bool epa_5g;
3975 bool epa_6g;
3976 };
3977
3978 struct rtw89_phy_ch_info {
3979 u8 rssi_min;
3980 u16 rssi_min_macid;
3981 u8 pre_rssi_min;
3982 u8 rssi_max;
3983 u16 rssi_max_macid;
3984 u8 rxsc_160;
3985 u8 rxsc_80;
3986 u8 rxsc_40;
3987 u8 rxsc_20;
3988 u8 rxsc_l;
3989 u8 is_noisy;
3990 };
3991
3992 struct rtw89_agc_gaincode_set {
3993 u8 lna_idx;
3994 u8 tia_idx;
3995 u8 rxb_idx;
3996 };
3997
3998 #define IGI_RSSI_TH_NUM 5
3999 #define FA_TH_NUM 4
4000 #define LNA_GAIN_NUM 7
4001 #define TIA_GAIN_NUM 2
4002 struct rtw89_dig_info {
4003 struct rtw89_agc_gaincode_set cur_gaincode;
4004 bool force_gaincode_idx_en;
4005 struct rtw89_agc_gaincode_set force_gaincode;
4006 u8 igi_rssi_th[IGI_RSSI_TH_NUM];
4007 u16 fa_th[FA_TH_NUM];
4008 u8 igi_rssi;
4009 u8 igi_fa_rssi;
4010 u8 fa_rssi_ofst;
4011 u8 dyn_igi_max;
4012 u8 dyn_igi_min;
4013 bool dyn_pd_th_en;
4014 u8 dyn_pd_th_max;
4015 u8 pd_low_th_ofst;
4016 u8 ib_pbk;
4017 s8 ib_pkpwr;
4018 s8 lna_gain_a[LNA_GAIN_NUM];
4019 s8 lna_gain_g[LNA_GAIN_NUM];
4020 s8 *lna_gain;
4021 s8 tia_gain_a[TIA_GAIN_NUM];
4022 s8 tia_gain_g[TIA_GAIN_NUM];
4023 s8 *tia_gain;
4024 bool is_linked_pre;
4025 bool bypass_dig;
4026 };
4027
4028 enum rtw89_multi_cfo_mode {
4029 RTW89_PKT_BASED_AVG_MODE = 0,
4030 RTW89_ENTRY_BASED_AVG_MODE = 1,
4031 RTW89_TP_BASED_AVG_MODE = 2,
4032 };
4033
4034 enum rtw89_phy_cfo_status {
4035 RTW89_PHY_DCFO_STATE_NORMAL = 0,
4036 RTW89_PHY_DCFO_STATE_ENHANCE = 1,
4037 RTW89_PHY_DCFO_STATE_HOLD = 2,
4038 RTW89_PHY_DCFO_STATE_MAX
4039 };
4040
4041 enum rtw89_phy_cfo_ul_ofdma_acc_mode {
4042 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0,
4043 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1
4044 };
4045
4046 struct rtw89_cfo_tracking_info {
4047 u16 cfo_timer_ms;
4048 bool cfo_trig_by_timer_en;
4049 enum rtw89_phy_cfo_status phy_cfo_status;
4050 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode;
4051 u8 phy_cfo_trk_cnt;
4052 bool is_adjust;
4053 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode;
4054 bool apply_compensation;
4055 u8 crystal_cap;
4056 u8 crystal_cap_default;
4057 u8 def_x_cap;
4058 s8 x_cap_ofst;
4059 u32 sta_cfo_tolerance;
4060 s32 cfo_tail[CFO_TRACK_MAX_USER];
4061 u16 cfo_cnt[CFO_TRACK_MAX_USER];
4062 s32 cfo_avg_pre;
4063 s32 cfo_avg[CFO_TRACK_MAX_USER];
4064 s32 pre_cfo_avg[CFO_TRACK_MAX_USER];
4065 s32 dcfo_avg;
4066 s32 dcfo_avg_pre;
4067 u32 packet_count;
4068 u32 packet_count_pre;
4069 s32 residual_cfo_acc;
4070 u8 phy_cfotrk_state;
4071 u8 phy_cfotrk_cnt;
4072 bool divergence_lock_en;
4073 u8 x_cap_lb;
4074 u8 x_cap_ub;
4075 u8 lock_cnt;
4076 };
4077
4078 enum rtw89_tssi_alimk_band {
4079 TSSI_ALIMK_2G = 0,
4080 TSSI_ALIMK_5GL,
4081 TSSI_ALIMK_5GM,
4082 TSSI_ALIMK_5GH,
4083 TSSI_ALIMK_MAX
4084 };
4085
4086 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
4087 #define TSSI_TRIM_CH_GROUP_NUM 8
4088 #define TSSI_TRIM_CH_GROUP_NUM_6G 16
4089
4090 #define TSSI_CCK_CH_GROUP_NUM 6
4091 #define TSSI_MCS_2G_CH_GROUP_NUM 5
4092 #define TSSI_MCS_5G_CH_GROUP_NUM 14
4093 #define TSSI_MCS_6G_CH_GROUP_NUM 32
4094 #define TSSI_MCS_CH_GROUP_NUM \
4095 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
4096 #define TSSI_MAX_CH_NUM 67
4097 #define TSSI_ALIMK_VALUE_NUM 8
4098
4099 struct rtw89_tssi_info {
4100 u8 thermal[RF_PATH_MAX];
4101 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM];
4102 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G];
4103 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM];
4104 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM];
4105 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM];
4106 s8 extra_ofst[RF_PATH_MAX];
4107 bool tssi_tracking_check[RF_PATH_MAX];
4108 u8 default_txagc_offset[RF_PATH_MAX];
4109 u32 base_thermal[RF_PATH_MAX];
4110 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM];
4111 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM];
4112 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM];
4113 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX];
4114 u32 tssi_alimk_time;
4115 };
4116
4117 struct rtw89_power_trim_info {
4118 bool pg_thermal_trim;
4119 bool pg_pa_bias_trim;
4120 u8 thermal_trim[RF_PATH_MAX];
4121 u8 pa_bias_trim[RF_PATH_MAX];
4122 };
4123
4124 struct rtw89_regd {
4125 char alpha2[3];
4126 u8 txpwr_regd[RTW89_BAND_NUM];
4127 };
4128
4129 struct rtw89_regulatory_info {
4130 const struct rtw89_regd *regd;
4131 enum rtw89_reg_6ghz_power reg_6ghz_power;
4132 };
4133
4134 enum rtw89_ifs_clm_application {
4135 RTW89_IFS_CLM_INIT = 0,
4136 RTW89_IFS_CLM_BACKGROUND = 1,
4137 RTW89_IFS_CLM_ACS = 2,
4138 RTW89_IFS_CLM_DIG = 3,
4139 RTW89_IFS_CLM_TDMA_DIG = 4,
4140 RTW89_IFS_CLM_DBG = 5,
4141 RTW89_IFS_CLM_DBG_MANUAL = 6
4142 };
4143
4144 enum rtw89_env_racing_lv {
4145 RTW89_RAC_RELEASE = 0,
4146 RTW89_RAC_LV_1 = 1,
4147 RTW89_RAC_LV_2 = 2,
4148 RTW89_RAC_LV_3 = 3,
4149 RTW89_RAC_LV_4 = 4,
4150 RTW89_RAC_MAX_NUM = 5
4151 };
4152
4153 struct rtw89_ccx_para_info {
4154 enum rtw89_env_racing_lv rac_lv;
4155 u16 mntr_time;
4156 u8 nhm_manual_th_ofst;
4157 u8 nhm_manual_th0;
4158 enum rtw89_ifs_clm_application ifs_clm_app;
4159 u32 ifs_clm_manual_th_times;
4160 u32 ifs_clm_manual_th0;
4161 u8 fahm_manual_th_ofst;
4162 u8 fahm_manual_th0;
4163 u8 fahm_numer_opt;
4164 u8 fahm_denom_opt;
4165 };
4166
4167 enum rtw89_ccx_edcca_opt_sc_idx {
4168 RTW89_CCX_EDCCA_SEG0_P0 = 0,
4169 RTW89_CCX_EDCCA_SEG0_S1 = 1,
4170 RTW89_CCX_EDCCA_SEG0_S2 = 2,
4171 RTW89_CCX_EDCCA_SEG0_S3 = 3,
4172 RTW89_CCX_EDCCA_SEG1_P0 = 4,
4173 RTW89_CCX_EDCCA_SEG1_S1 = 5,
4174 RTW89_CCX_EDCCA_SEG1_S2 = 6,
4175 RTW89_CCX_EDCCA_SEG1_S3 = 7
4176 };
4177
4178 enum rtw89_ccx_edcca_opt_bw_idx {
4179 RTW89_CCX_EDCCA_BW20_0 = 0,
4180 RTW89_CCX_EDCCA_BW20_1 = 1,
4181 RTW89_CCX_EDCCA_BW20_2 = 2,
4182 RTW89_CCX_EDCCA_BW20_3 = 3,
4183 RTW89_CCX_EDCCA_BW20_4 = 4,
4184 RTW89_CCX_EDCCA_BW20_5 = 5,
4185 RTW89_CCX_EDCCA_BW20_6 = 6,
4186 RTW89_CCX_EDCCA_BW20_7 = 7
4187 };
4188
4189 #define RTW89_NHM_TH_NUM 11
4190 #define RTW89_FAHM_TH_NUM 11
4191 #define RTW89_NHM_RPT_NUM 12
4192 #define RTW89_FAHM_RPT_NUM 12
4193 #define RTW89_IFS_CLM_NUM 4
4194 struct rtw89_env_monitor_info {
4195 u8 ccx_watchdog_result;
4196 bool ccx_ongoing;
4197 u8 ccx_rac_lv;
4198 bool ccx_manual_ctrl;
4199 u16 ifs_clm_mntr_time;
4200 enum rtw89_ifs_clm_application ifs_clm_app;
4201 u16 ccx_period;
4202 u8 ccx_unit_idx;
4203 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM];
4204 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM];
4205 u16 ifs_clm_tx;
4206 u16 ifs_clm_edcca_excl_cca;
4207 u16 ifs_clm_ofdmfa;
4208 u16 ifs_clm_ofdmcca_excl_fa;
4209 u16 ifs_clm_cckfa;
4210 u16 ifs_clm_cckcca_excl_fa;
4211 u16 ifs_clm_total_ifs;
4212 u8 ifs_clm_his[RTW89_IFS_CLM_NUM];
4213 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM];
4214 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM];
4215 u8 ifs_clm_tx_ratio;
4216 u8 ifs_clm_edcca_excl_cca_ratio;
4217 u8 ifs_clm_cck_fa_ratio;
4218 u8 ifs_clm_ofdm_fa_ratio;
4219 u8 ifs_clm_cck_cca_excl_fa_ratio;
4220 u8 ifs_clm_ofdm_cca_excl_fa_ratio;
4221 u16 ifs_clm_cck_fa_permil;
4222 u16 ifs_clm_ofdm_fa_permil;
4223 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM];
4224 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM];
4225 };
4226
4227 enum rtw89_ser_rcvy_step {
4228 RTW89_SER_DRV_STOP_TX,
4229 RTW89_SER_DRV_STOP_RX,
4230 RTW89_SER_DRV_STOP_RUN,
4231 RTW89_SER_HAL_STOP_DMA,
4232 RTW89_SER_SUPPRESS_LOG,
4233 RTW89_NUM_OF_SER_FLAGS
4234 };
4235
4236 struct rtw89_ser {
4237 u8 state;
4238 u8 alarm_event;
4239 bool prehandle_l1;
4240
4241 struct work_struct ser_hdl_work;
4242 struct delayed_work ser_alarm_work;
4243 const struct state_ent *st_tbl;
4244 const struct event_ent *ev_tbl;
4245 struct list_head msg_q;
4246 spinlock_t msg_q_lock; /* lock when read/write ser msg */
4247 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS);
4248 };
4249
4250 enum rtw89_mac_ax_ps_mode {
4251 RTW89_MAC_AX_PS_MODE_ACTIVE = 0,
4252 RTW89_MAC_AX_PS_MODE_LEGACY = 1,
4253 RTW89_MAC_AX_PS_MODE_WMMPS = 2,
4254 RTW89_MAC_AX_PS_MODE_MAX = 3,
4255 };
4256
4257 enum rtw89_last_rpwm_mode {
4258 RTW89_LAST_RPWM_PS = 0x0,
4259 RTW89_LAST_RPWM_ACTIVE = 0x6,
4260 };
4261
4262 struct rtw89_lps_parm {
4263 u8 macid;
4264 u8 psmode; /* enum rtw89_mac_ax_ps_mode */
4265 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */
4266 };
4267
4268 struct rtw89_ppdu_sts_info {
4269 struct sk_buff_head rx_queue[RTW89_PHY_MAX];
4270 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX];
4271 };
4272
4273 struct rtw89_early_h2c {
4274 struct list_head list;
4275 u8 *h2c;
4276 u16 h2c_len;
4277 };
4278
4279 struct rtw89_hw_scan_info {
4280 struct ieee80211_vif *scanning_vif;
4281 struct list_head pkt_list[NUM_NL80211_BANDS];
4282 struct rtw89_chan op_chan;
4283 u32 last_chan_idx;
4284 };
4285
4286 enum rtw89_phy_bb_gain_band {
4287 RTW89_BB_GAIN_BAND_2G = 0,
4288 RTW89_BB_GAIN_BAND_5G_L = 1,
4289 RTW89_BB_GAIN_BAND_5G_M = 2,
4290 RTW89_BB_GAIN_BAND_5G_H = 3,
4291 RTW89_BB_GAIN_BAND_6G_L = 4,
4292 RTW89_BB_GAIN_BAND_6G_M = 5,
4293 RTW89_BB_GAIN_BAND_6G_H = 6,
4294 RTW89_BB_GAIN_BAND_6G_UH = 7,
4295
4296 RTW89_BB_GAIN_BAND_NR,
4297 };
4298
4299 enum rtw89_phy_bb_rxsc_num {
4300 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */
4301 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */
4302 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */
4303 };
4304
4305 struct rtw89_phy_bb_gain_info {
4306 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
4307 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM];
4308 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
4309 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
4310 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
4311 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */
4312 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX];
4313 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
4314 [RTW89_BB_RXSC_NUM_40];
4315 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
4316 [RTW89_BB_RXSC_NUM_80];
4317 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
4318 [RTW89_BB_RXSC_NUM_160];
4319 };
4320
4321 struct rtw89_phy_efuse_gain {
4322 bool offset_valid;
4323 bool comp_valid;
4324 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
4325 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */
4326 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */
4327 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
4328 };
4329
4330 #define RTW89_MAX_PATTERN_NUM 18
4331 #define RTW89_MAX_PATTERN_MASK_SIZE 4
4332 #define RTW89_MAX_PATTERN_SIZE 128
4333
4334 struct rtw89_wow_cam_info {
4335 bool r_w;
4336 u8 idx;
4337 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE];
4338 u16 crc;
4339 bool negative_pattern_match;
4340 bool skip_mac_hdr;
4341 bool uc;
4342 bool mc;
4343 bool bc;
4344 bool valid;
4345 };
4346
4347 struct rtw89_wow_param {
4348 struct ieee80211_vif *wow_vif;
4349 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM);
4350 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM];
4351 u8 pattern_cnt;
4352 };
4353
4354 struct rtw89_mcc_info {
4355 struct rtw89_wait_info wait;
4356 };
4357
4358 struct rtw89_dev {
4359 struct ieee80211_hw *hw;
4360 struct device *dev;
4361 const struct ieee80211_ops *ops;
4362
4363 bool dbcc_en;
4364 struct rtw89_hw_scan_info scan_info;
4365 const struct rtw89_chip_info *chip;
4366 const struct rtw89_pci_info *pci_info;
4367 const struct rtw89_rfe_parms *rfe_parms;
4368 struct rtw89_hal hal;
4369 struct rtw89_mcc_info mcc;
4370 struct rtw89_mac_info mac;
4371 struct rtw89_fw_info fw;
4372 struct rtw89_hci_info hci;
4373 struct rtw89_efuse efuse;
4374 struct rtw89_traffic_stats stats;
4375
4376 /* ensures exclusive access from mac80211 callbacks */
4377 struct mutex mutex;
4378 struct list_head rtwvifs_list;
4379 /* used to protect rf read write */
4380 struct mutex rf_mutex;
4381 struct workqueue_struct *txq_wq;
4382 struct work_struct txq_work;
4383 struct delayed_work txq_reinvoke_work;
4384 /* used to protect ba_list and forbid_ba_list */
4385 spinlock_t ba_lock;
4386 /* txqs to setup ba session */
4387 struct list_head ba_list;
4388 /* txqs to forbid ba session */
4389 struct list_head forbid_ba_list;
4390 struct work_struct ba_work;
4391 /* used to protect rpwm */
4392 spinlock_t rpwm_lock;
4393
4394 struct rtw89_cam_info cam_info;
4395
4396 struct sk_buff_head c2h_queue;
4397 struct work_struct c2h_work;
4398 struct work_struct ips_work;
4399 struct work_struct load_firmware_work;
4400 struct work_struct cancel_6ghz_probe_work;
4401
4402 struct list_head early_h2c_list;
4403
4404 struct rtw89_ser ser;
4405
4406 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM);
4407 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM);
4408 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS);
4409 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM);
4410
4411 struct rtw89_phy_stat phystat;
4412 struct rtw89_dack_info dack;
4413 struct rtw89_iqk_info iqk;
4414 struct rtw89_dpk_info dpk;
4415 struct rtw89_rfk_mcc_info rfk_mcc;
4416 struct rtw89_lck_info lck;
4417 struct rtw89_rx_dck_info rx_dck;
4418 bool is_tssi_mode[RF_PATH_MAX];
4419 bool is_bt_iqk_timeout;
4420
4421 struct rtw89_fem_info fem;
4422 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM];
4423 struct rtw89_tssi_info tssi;
4424 struct rtw89_power_trim_info pwr_trim;
4425
4426 struct rtw89_cfo_tracking_info cfo_tracking;
4427 struct rtw89_env_monitor_info env_monitor;
4428 struct rtw89_dig_info dig;
4429 struct rtw89_phy_ch_info ch_info;
4430 struct rtw89_phy_bb_gain_info bb_gain;
4431 struct rtw89_phy_efuse_gain efuse_gain;
4432 struct rtw89_phy_ul_tb_info ul_tb_info;
4433 struct rtw89_antdiv_info antdiv;
4434
4435 struct delayed_work track_work;
4436 struct delayed_work chanctx_work;
4437 struct delayed_work coex_act1_work;
4438 struct delayed_work coex_bt_devinfo_work;
4439 struct delayed_work coex_rfk_chk_work;
4440 struct delayed_work cfo_track_work;
4441 struct delayed_work forbid_ba_work;
4442 struct delayed_work roc_work;
4443 struct delayed_work antdiv_work;
4444 struct rtw89_ppdu_sts_info ppdu_sts;
4445 u8 total_sta_assoc;
4446 bool scanning;
4447
4448 struct rtw89_regulatory_info regulatory;
4449 struct rtw89_sar_info sar;
4450 struct rtw89_tas_info tas;
4451
4452 struct rtw89_btc btc;
4453 enum rtw89_ps_mode ps_mode;
4454 bool lps_enabled;
4455
4456 struct rtw89_wow_param wow;
4457
4458 /* napi structure */
4459 struct net_device netdev;
4460 struct napi_struct napi;
4461 int napi_budget_countdown;
4462
4463 /* HCI related data, keep last */
4464 u8 priv[] __aligned(sizeof(void *));
4465 };
4466
rtw89_hci_tx_write(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)4467 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev,
4468 struct rtw89_core_tx_request *tx_req)
4469 {
4470 return rtwdev->hci.ops->tx_write(rtwdev, tx_req);
4471 }
4472
rtw89_hci_reset(struct rtw89_dev * rtwdev)4473 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev)
4474 {
4475 rtwdev->hci.ops->reset(rtwdev);
4476 }
4477
rtw89_hci_start(struct rtw89_dev * rtwdev)4478 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev)
4479 {
4480 return rtwdev->hci.ops->start(rtwdev);
4481 }
4482
rtw89_hci_stop(struct rtw89_dev * rtwdev)4483 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev)
4484 {
4485 rtwdev->hci.ops->stop(rtwdev);
4486 }
4487
rtw89_hci_deinit(struct rtw89_dev * rtwdev)4488 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev)
4489 {
4490 return rtwdev->hci.ops->deinit(rtwdev);
4491 }
4492
rtw89_hci_pause(struct rtw89_dev * rtwdev,bool pause)4493 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause)
4494 {
4495 rtwdev->hci.ops->pause(rtwdev, pause);
4496 }
4497
rtw89_hci_switch_mode(struct rtw89_dev * rtwdev,bool low_power)4498 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power)
4499 {
4500 rtwdev->hci.ops->switch_mode(rtwdev, low_power);
4501 }
4502
rtw89_hci_recalc_int_mit(struct rtw89_dev * rtwdev)4503 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev)
4504 {
4505 rtwdev->hci.ops->recalc_int_mit(rtwdev);
4506 }
4507
rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev * rtwdev,u8 txch)4508 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch)
4509 {
4510 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch);
4511 }
4512
rtw89_hci_tx_kick_off(struct rtw89_dev * rtwdev,u8 txch)4513 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)
4514 {
4515 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch);
4516 }
4517
rtw89_hci_flush_queues(struct rtw89_dev * rtwdev,u32 queues,bool drop)4518 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues,
4519 bool drop)
4520 {
4521 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
4522 return;
4523
4524 if (rtwdev->hci.ops->flush_queues)
4525 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop);
4526 }
4527
rtw89_hci_recovery_start(struct rtw89_dev * rtwdev)4528 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev)
4529 {
4530 if (rtwdev->hci.ops->recovery_start)
4531 rtwdev->hci.ops->recovery_start(rtwdev);
4532 }
4533
rtw89_hci_recovery_complete(struct rtw89_dev * rtwdev)4534 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev)
4535 {
4536 if (rtwdev->hci.ops->recovery_complete)
4537 rtwdev->hci.ops->recovery_complete(rtwdev);
4538 }
4539
rtw89_hci_enable_intr(struct rtw89_dev * rtwdev)4540 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev)
4541 {
4542 if (rtwdev->hci.ops->enable_intr)
4543 rtwdev->hci.ops->enable_intr(rtwdev);
4544 }
4545
rtw89_hci_disable_intr(struct rtw89_dev * rtwdev)4546 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev)
4547 {
4548 if (rtwdev->hci.ops->disable_intr)
4549 rtwdev->hci.ops->disable_intr(rtwdev);
4550 }
4551
rtw89_hci_ctrl_txdma_ch(struct rtw89_dev * rtwdev,bool enable)4552 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable)
4553 {
4554 if (rtwdev->hci.ops->ctrl_txdma_ch)
4555 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable);
4556 }
4557
rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev * rtwdev,bool enable)4558 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable)
4559 {
4560 if (rtwdev->hci.ops->ctrl_txdma_fw_ch)
4561 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable);
4562 }
4563
rtw89_hci_ctrl_trxhci(struct rtw89_dev * rtwdev,bool enable)4564 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable)
4565 {
4566 if (rtwdev->hci.ops->ctrl_trxhci)
4567 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable);
4568 }
4569
rtw89_hci_poll_txdma_ch(struct rtw89_dev * rtwdev)4570 static inline int rtw89_hci_poll_txdma_ch(struct rtw89_dev *rtwdev)
4571 {
4572 int ret = 0;
4573
4574 if (rtwdev->hci.ops->poll_txdma_ch)
4575 ret = rtwdev->hci.ops->poll_txdma_ch(rtwdev);
4576 return ret;
4577 }
4578
rtw89_hci_clr_idx_all(struct rtw89_dev * rtwdev)4579 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev)
4580 {
4581 if (rtwdev->hci.ops->clr_idx_all)
4582 rtwdev->hci.ops->clr_idx_all(rtwdev);
4583 }
4584
rtw89_hci_rst_bdram(struct rtw89_dev * rtwdev)4585 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev)
4586 {
4587 int ret = 0;
4588
4589 if (rtwdev->hci.ops->rst_bdram)
4590 ret = rtwdev->hci.ops->rst_bdram(rtwdev);
4591 return ret;
4592 }
4593
rtw89_hci_clear(struct rtw89_dev * rtwdev,struct pci_dev * pdev)4594 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev)
4595 {
4596 if (rtwdev->hci.ops->clear)
4597 rtwdev->hci.ops->clear(rtwdev, pdev);
4598 }
4599
4600 static inline
RTW89_TX_SKB_CB(struct sk_buff * skb)4601 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb)
4602 {
4603 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
4604
4605 return (struct rtw89_tx_skb_data *)info->status.status_driver_data;
4606 }
4607
rtw89_read8(struct rtw89_dev * rtwdev,u32 addr)4608 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)
4609 {
4610 return rtwdev->hci.ops->read8(rtwdev, addr);
4611 }
4612
rtw89_read16(struct rtw89_dev * rtwdev,u32 addr)4613 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr)
4614 {
4615 return rtwdev->hci.ops->read16(rtwdev, addr);
4616 }
4617
rtw89_read32(struct rtw89_dev * rtwdev,u32 addr)4618 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr)
4619 {
4620 return rtwdev->hci.ops->read32(rtwdev, addr);
4621 }
4622
rtw89_write8(struct rtw89_dev * rtwdev,u32 addr,u8 data)4623 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
4624 {
4625 rtwdev->hci.ops->write8(rtwdev, addr, data);
4626 }
4627
rtw89_write16(struct rtw89_dev * rtwdev,u32 addr,u16 data)4628 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
4629 {
4630 rtwdev->hci.ops->write16(rtwdev, addr, data);
4631 }
4632
rtw89_write32(struct rtw89_dev * rtwdev,u32 addr,u32 data)4633 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
4634 {
4635 rtwdev->hci.ops->write32(rtwdev, addr, data);
4636 }
4637
4638 static inline void
rtw89_write8_set(struct rtw89_dev * rtwdev,u32 addr,u8 bit)4639 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
4640 {
4641 u8 val;
4642
4643 val = rtw89_read8(rtwdev, addr);
4644 rtw89_write8(rtwdev, addr, val | bit);
4645 }
4646
4647 static inline void
rtw89_write16_set(struct rtw89_dev * rtwdev,u32 addr,u16 bit)4648 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
4649 {
4650 u16 val;
4651
4652 val = rtw89_read16(rtwdev, addr);
4653 rtw89_write16(rtwdev, addr, val | bit);
4654 }
4655
4656 static inline void
rtw89_write32_set(struct rtw89_dev * rtwdev,u32 addr,u32 bit)4657 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
4658 {
4659 u32 val;
4660
4661 val = rtw89_read32(rtwdev, addr);
4662 rtw89_write32(rtwdev, addr, val | bit);
4663 }
4664
4665 static inline void
rtw89_write8_clr(struct rtw89_dev * rtwdev,u32 addr,u8 bit)4666 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
4667 {
4668 u8 val;
4669
4670 val = rtw89_read8(rtwdev, addr);
4671 rtw89_write8(rtwdev, addr, val & ~bit);
4672 }
4673
4674 static inline void
rtw89_write16_clr(struct rtw89_dev * rtwdev,u32 addr,u16 bit)4675 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
4676 {
4677 u16 val;
4678
4679 val = rtw89_read16(rtwdev, addr);
4680 rtw89_write16(rtwdev, addr, val & ~bit);
4681 }
4682
4683 static inline void
rtw89_write32_clr(struct rtw89_dev * rtwdev,u32 addr,u32 bit)4684 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
4685 {
4686 u32 val;
4687
4688 val = rtw89_read32(rtwdev, addr);
4689 rtw89_write32(rtwdev, addr, val & ~bit);
4690 }
4691
4692 static inline u32
rtw89_read32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)4693 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
4694 {
4695 u32 shift = __ffs(mask);
4696 u32 orig;
4697 u32 ret;
4698
4699 orig = rtw89_read32(rtwdev, addr);
4700 ret = (orig & mask) >> shift;
4701
4702 return ret;
4703 }
4704
4705 static inline u16
rtw89_read16_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)4706 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
4707 {
4708 u32 shift = __ffs(mask);
4709 u32 orig;
4710 u32 ret;
4711
4712 orig = rtw89_read16(rtwdev, addr);
4713 ret = (orig & mask) >> shift;
4714
4715 return ret;
4716 }
4717
4718 static inline u8
rtw89_read8_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)4719 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
4720 {
4721 u32 shift = __ffs(mask);
4722 u32 orig;
4723 u32 ret;
4724
4725 orig = rtw89_read8(rtwdev, addr);
4726 ret = (orig & mask) >> shift;
4727
4728 return ret;
4729 }
4730
4731 static inline void
rtw89_write32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data)4732 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data)
4733 {
4734 u32 shift = __ffs(mask);
4735 u32 orig;
4736 u32 set;
4737
4738 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr);
4739
4740 orig = rtw89_read32(rtwdev, addr);
4741 set = (orig & ~mask) | ((data << shift) & mask);
4742 rtw89_write32(rtwdev, addr, set);
4743 }
4744
4745 static inline void
rtw89_write16_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u16 data)4746 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data)
4747 {
4748 u32 shift;
4749 u16 orig, set;
4750
4751 mask &= 0xffff;
4752 shift = __ffs(mask);
4753
4754 orig = rtw89_read16(rtwdev, addr);
4755 set = (orig & ~mask) | ((data << shift) & mask);
4756 rtw89_write16(rtwdev, addr, set);
4757 }
4758
4759 static inline void
rtw89_write8_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u8 data)4760 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data)
4761 {
4762 u32 shift;
4763 u8 orig, set;
4764
4765 mask &= 0xff;
4766 shift = __ffs(mask);
4767
4768 orig = rtw89_read8(rtwdev, addr);
4769 set = (orig & ~mask) | ((data << shift) & mask);
4770 rtw89_write8(rtwdev, addr, set);
4771 }
4772
4773 static inline u32
rtw89_read_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)4774 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
4775 u32 addr, u32 mask)
4776 {
4777 u32 val;
4778
4779 mutex_lock(&rtwdev->rf_mutex);
4780 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
4781 mutex_unlock(&rtwdev->rf_mutex);
4782
4783 return val;
4784 }
4785
4786 static inline void
rtw89_write_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)4787 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
4788 u32 addr, u32 mask, u32 data)
4789 {
4790 mutex_lock(&rtwdev->rf_mutex);
4791 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
4792 mutex_unlock(&rtwdev->rf_mutex);
4793 }
4794
rtw89_txq_to_txq(struct rtw89_txq * rtwtxq)4795 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq)
4796 {
4797 void *p = rtwtxq;
4798
4799 return container_of(p, struct ieee80211_txq, drv_priv);
4800 }
4801
rtw89_core_txq_init(struct rtw89_dev * rtwdev,struct ieee80211_txq * txq)4802 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev,
4803 struct ieee80211_txq *txq)
4804 {
4805 struct rtw89_txq *rtwtxq;
4806
4807 if (!txq)
4808 return;
4809
4810 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
4811 INIT_LIST_HEAD(&rtwtxq->list);
4812 }
4813
rtwvif_to_vif(struct rtw89_vif * rtwvif)4814 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif)
4815 {
4816 void *p = rtwvif;
4817
4818 return container_of(p, struct ieee80211_vif, drv_priv);
4819 }
4820
rtwvif_to_vif_safe(struct rtw89_vif * rtwvif)4821 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif)
4822 {
4823 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL;
4824 }
4825
vif_to_rtwvif_safe(struct ieee80211_vif * vif)4826 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif)
4827 {
4828 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL;
4829 }
4830
rtwsta_to_sta(struct rtw89_sta * rtwsta)4831 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta)
4832 {
4833 void *p = rtwsta;
4834
4835 return container_of(p, struct ieee80211_sta, drv_priv);
4836 }
4837
rtwsta_to_sta_safe(struct rtw89_sta * rtwsta)4838 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta)
4839 {
4840 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL;
4841 }
4842
sta_to_rtwsta_safe(struct ieee80211_sta * sta)4843 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta)
4844 {
4845 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL;
4846 }
4847
rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)4848 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)
4849 {
4850 if (hw_bw == RTW89_CHANNEL_WIDTH_160)
4851 return RATE_INFO_BW_160;
4852 else if (hw_bw == RTW89_CHANNEL_WIDTH_80)
4853 return RATE_INFO_BW_80;
4854 else if (hw_bw == RTW89_CHANNEL_WIDTH_40)
4855 return RATE_INFO_BW_40;
4856 else
4857 return RATE_INFO_BW_20;
4858 }
4859
4860 static inline
rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)4861 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)
4862 {
4863 switch (hw_band) {
4864 default:
4865 case RTW89_BAND_2G:
4866 return NL80211_BAND_2GHZ;
4867 case RTW89_BAND_5G:
4868 return NL80211_BAND_5GHZ;
4869 case RTW89_BAND_6G:
4870 return NL80211_BAND_6GHZ;
4871 }
4872 }
4873
4874 static inline
rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)4875 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)
4876 {
4877 switch (nl_band) {
4878 default:
4879 case NL80211_BAND_2GHZ:
4880 return RTW89_BAND_2G;
4881 case NL80211_BAND_5GHZ:
4882 return RTW89_BAND_5G;
4883 case NL80211_BAND_6GHZ:
4884 return RTW89_BAND_6G;
4885 }
4886 }
4887
4888 static inline
nl_to_rtw89_bandwidth(enum nl80211_chan_width width)4889 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width)
4890 {
4891 switch (width) {
4892 default:
4893 WARN(1, "Not support bandwidth %d\n", width);
4894 fallthrough;
4895 case NL80211_CHAN_WIDTH_20_NOHT:
4896 case NL80211_CHAN_WIDTH_20:
4897 return RTW89_CHANNEL_WIDTH_20;
4898 case NL80211_CHAN_WIDTH_40:
4899 return RTW89_CHANNEL_WIDTH_40;
4900 case NL80211_CHAN_WIDTH_80:
4901 return RTW89_CHANNEL_WIDTH_80;
4902 case NL80211_CHAN_WIDTH_160:
4903 return RTW89_CHANNEL_WIDTH_160;
4904 }
4905 }
4906
4907 static inline
rtw89_get_addr_cam_of(struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)4908 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif,
4909 struct rtw89_sta *rtwsta)
4910 {
4911 if (rtwsta) {
4912 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
4913
4914 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls)
4915 return &rtwsta->addr_cam;
4916 }
4917 return &rtwvif->addr_cam;
4918 }
4919
4920 static inline
rtw89_get_bssid_cam_of(struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)4921 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif,
4922 struct rtw89_sta *rtwsta)
4923 {
4924 if (rtwsta) {
4925 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
4926
4927 if (sta->tdls)
4928 return &rtwsta->bssid_cam;
4929 }
4930 return &rtwvif->bssid_cam;
4931 }
4932
4933 static inline
rtw89_chip_set_channel_prepare(struct rtw89_dev * rtwdev,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)4934 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev,
4935 struct rtw89_channel_help_params *p,
4936 const struct rtw89_chan *chan,
4937 enum rtw89_mac_idx mac_idx,
4938 enum rtw89_phy_idx phy_idx)
4939 {
4940 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan,
4941 mac_idx, phy_idx);
4942 }
4943
4944 static inline
rtw89_chip_set_channel_done(struct rtw89_dev * rtwdev,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)4945 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev,
4946 struct rtw89_channel_help_params *p,
4947 const struct rtw89_chan *chan,
4948 enum rtw89_mac_idx mac_idx,
4949 enum rtw89_phy_idx phy_idx)
4950 {
4951 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan,
4952 mac_idx, phy_idx);
4953 }
4954
4955 static inline
rtw89_chandef_get(struct rtw89_dev * rtwdev,enum rtw89_sub_entity_idx idx)4956 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev,
4957 enum rtw89_sub_entity_idx idx)
4958 {
4959 struct rtw89_hal *hal = &rtwdev->hal;
4960 enum rtw89_sub_entity_idx roc_idx = atomic_read(&hal->roc_entity_idx);
4961
4962 if (roc_idx == idx)
4963 return &hal->roc_chandef;
4964
4965 return &hal->sub[idx].chandef;
4966 }
4967
4968 static inline
rtw89_chan_get(struct rtw89_dev * rtwdev,enum rtw89_sub_entity_idx idx)4969 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev,
4970 enum rtw89_sub_entity_idx idx)
4971 {
4972 struct rtw89_hal *hal = &rtwdev->hal;
4973
4974 return &hal->sub[idx].chan;
4975 }
4976
4977 static inline
rtw89_chan_rcd_get(struct rtw89_dev * rtwdev,enum rtw89_sub_entity_idx idx)4978 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev,
4979 enum rtw89_sub_entity_idx idx)
4980 {
4981 struct rtw89_hal *hal = &rtwdev->hal;
4982
4983 return &hal->sub[idx].rcd;
4984 }
4985
4986 static inline
rtw89_scan_chan_get(struct rtw89_dev * rtwdev)4987 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev)
4988 {
4989 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif;
4990 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif);
4991
4992 if (rtwvif)
4993 return rtw89_chan_get(rtwdev, rtwvif->sub_entity_idx);
4994 else
4995 return rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
4996 }
4997
rtw89_chip_fem_setup(struct rtw89_dev * rtwdev)4998 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
4999 {
5000 const struct rtw89_chip_info *chip = rtwdev->chip;
5001
5002 if (chip->ops->fem_setup)
5003 chip->ops->fem_setup(rtwdev);
5004 }
5005
rtw89_chip_rfe_gpio(struct rtw89_dev * rtwdev)5006 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev)
5007 {
5008 const struct rtw89_chip_info *chip = rtwdev->chip;
5009
5010 if (chip->ops->rfe_gpio)
5011 chip->ops->rfe_gpio(rtwdev);
5012 }
5013
rtw89_chip_bb_sethw(struct rtw89_dev * rtwdev)5014 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev)
5015 {
5016 const struct rtw89_chip_info *chip = rtwdev->chip;
5017
5018 if (chip->ops->bb_sethw)
5019 chip->ops->bb_sethw(rtwdev);
5020 }
5021
rtw89_chip_rfk_init(struct rtw89_dev * rtwdev)5022 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev)
5023 {
5024 const struct rtw89_chip_info *chip = rtwdev->chip;
5025
5026 if (chip->ops->rfk_init)
5027 chip->ops->rfk_init(rtwdev);
5028 }
5029
rtw89_chip_rfk_channel(struct rtw89_dev * rtwdev)5030 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev)
5031 {
5032 const struct rtw89_chip_info *chip = rtwdev->chip;
5033
5034 if (chip->ops->rfk_channel)
5035 chip->ops->rfk_channel(rtwdev);
5036 }
5037
rtw89_chip_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)5038 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev,
5039 enum rtw89_phy_idx phy_idx)
5040 {
5041 const struct rtw89_chip_info *chip = rtwdev->chip;
5042
5043 if (chip->ops->rfk_band_changed)
5044 chip->ops->rfk_band_changed(rtwdev, phy_idx);
5045 }
5046
rtw89_chip_rfk_scan(struct rtw89_dev * rtwdev,bool start)5047 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start)
5048 {
5049 const struct rtw89_chip_info *chip = rtwdev->chip;
5050
5051 if (chip->ops->rfk_scan)
5052 chip->ops->rfk_scan(rtwdev, start);
5053 }
5054
rtw89_chip_rfk_track(struct rtw89_dev * rtwdev)5055 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev)
5056 {
5057 const struct rtw89_chip_info *chip = rtwdev->chip;
5058
5059 if (chip->ops->rfk_track)
5060 chip->ops->rfk_track(rtwdev);
5061 }
5062
rtw89_chip_set_txpwr_ctrl(struct rtw89_dev * rtwdev)5063 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev)
5064 {
5065 const struct rtw89_chip_info *chip = rtwdev->chip;
5066
5067 if (chip->ops->set_txpwr_ctrl)
5068 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0);
5069 }
5070
rtw89_chip_power_trim(struct rtw89_dev * rtwdev)5071 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev)
5072 {
5073 const struct rtw89_chip_info *chip = rtwdev->chip;
5074
5075 if (chip->ops->power_trim)
5076 chip->ops->power_trim(rtwdev);
5077 }
5078
rtw89_chip_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)5079 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev,
5080 enum rtw89_phy_idx phy_idx)
5081 {
5082 const struct rtw89_chip_info *chip = rtwdev->chip;
5083
5084 if (chip->ops->init_txpwr_unit)
5085 chip->ops->init_txpwr_unit(rtwdev, phy_idx);
5086 }
5087
rtw89_chip_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)5088 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev,
5089 enum rtw89_rf_path rf_path)
5090 {
5091 const struct rtw89_chip_info *chip = rtwdev->chip;
5092
5093 if (!chip->ops->get_thermal)
5094 return 0x10;
5095
5096 return chip->ops->get_thermal(rtwdev, rf_path);
5097 }
5098
rtw89_chip_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)5099 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev,
5100 struct rtw89_rx_phy_ppdu *phy_ppdu,
5101 struct ieee80211_rx_status *status)
5102 {
5103 const struct rtw89_chip_info *chip = rtwdev->chip;
5104
5105 if (chip->ops->query_ppdu)
5106 chip->ops->query_ppdu(rtwdev, phy_ppdu, status);
5107 }
5108
rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev * rtwdev,bool bt_en)5109 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev,
5110 bool bt_en)
5111 {
5112 const struct rtw89_chip_info *chip = rtwdev->chip;
5113
5114 if (chip->ops->bb_ctrl_btc_preagc)
5115 chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en);
5116 }
5117
rtw89_chip_cfg_txrx_path(struct rtw89_dev * rtwdev)5118 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev)
5119 {
5120 const struct rtw89_chip_info *chip = rtwdev->chip;
5121
5122 if (chip->ops->cfg_txrx_path)
5123 chip->ops->cfg_txrx_path(rtwdev);
5124 }
5125
5126 static inline
rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif)5127 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
5128 struct ieee80211_vif *vif)
5129 {
5130 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
5131 const struct rtw89_chip_info *chip = rtwdev->chip;
5132
5133 if (!vif->bss_conf.he_support || !vif->cfg.assoc)
5134 return;
5135
5136 if (chip->ops->set_txpwr_ul_tb_offset)
5137 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx);
5138 }
5139
rtw89_load_txpwr_table(struct rtw89_dev * rtwdev,const struct rtw89_txpwr_table * tbl)5140 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
5141 const struct rtw89_txpwr_table *tbl)
5142 {
5143 tbl->load(rtwdev, tbl);
5144 }
5145
rtw89_regd_get(struct rtw89_dev * rtwdev,u8 band)5146 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band)
5147 {
5148 const struct rtw89_regd *regd = rtwdev->regulatory.regd;
5149
5150 return regd->txpwr_regd[band];
5151 }
5152
rtw89_ctrl_btg(struct rtw89_dev * rtwdev,bool btg)5153 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
5154 {
5155 const struct rtw89_chip_info *chip = rtwdev->chip;
5156
5157 if (chip->ops->ctrl_btg)
5158 chip->ops->ctrl_btg(rtwdev, btg);
5159 }
5160
5161 static inline
rtw89_chip_query_rxdesc(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)5162 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev,
5163 struct rtw89_rx_desc_info *desc_info,
5164 u8 *data, u32 data_offset)
5165 {
5166 const struct rtw89_chip_info *chip = rtwdev->chip;
5167
5168 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset);
5169 }
5170
5171 static inline
rtw89_chip_fill_txdesc(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)5172 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev,
5173 struct rtw89_tx_desc_info *desc_info,
5174 void *txdesc)
5175 {
5176 const struct rtw89_chip_info *chip = rtwdev->chip;
5177
5178 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc);
5179 }
5180
5181 static inline
rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)5182 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev,
5183 struct rtw89_tx_desc_info *desc_info,
5184 void *txdesc)
5185 {
5186 const struct rtw89_chip_info *chip = rtwdev->chip;
5187
5188 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc);
5189 }
5190
5191 static inline
rtw89_chip_mac_cfg_gnt(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex_gnt * gnt_cfg)5192 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev,
5193 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
5194 {
5195 const struct rtw89_chip_info *chip = rtwdev->chip;
5196
5197 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg);
5198 }
5199
rtw89_chip_cfg_ctrl_path(struct rtw89_dev * rtwdev,bool wl)5200 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
5201 {
5202 const struct rtw89_chip_info *chip = rtwdev->chip;
5203
5204 chip->ops->cfg_ctrl_path(rtwdev, wl);
5205 }
5206
5207 static inline
rtw89_chip_stop_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 * tx_en,enum rtw89_sch_tx_sel sel)5208 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
5209 u32 *tx_en, enum rtw89_sch_tx_sel sel)
5210 {
5211 const struct rtw89_chip_info *chip = rtwdev->chip;
5212
5213 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel);
5214 }
5215
5216 static inline
rtw89_chip_resume_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en)5217 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
5218 {
5219 const struct rtw89_chip_info *chip = rtwdev->chip;
5220
5221 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en);
5222 }
5223
5224 static inline
rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)5225 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev,
5226 struct rtw89_vif *rtwvif,
5227 struct rtw89_sta *rtwsta)
5228 {
5229 const struct rtw89_chip_info *chip = rtwdev->chip;
5230
5231 if (!chip->ops->h2c_dctl_sec_cam)
5232 return 0;
5233 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta);
5234 }
5235
get_hdr_bssid(struct ieee80211_hdr * hdr)5236 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr)
5237 {
5238 __le16 fc = hdr->frame_control;
5239
5240 if (ieee80211_has_tods(fc))
5241 return hdr->addr1;
5242 else if (ieee80211_has_fromds(fc))
5243 return hdr->addr2;
5244 else
5245 return hdr->addr3;
5246 }
5247
rtw89_sta_has_beamformer_cap(struct ieee80211_sta * sta)5248 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta)
5249 {
5250 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
5251 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) ||
5252 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] &
5253 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
5254 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] &
5255 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER))
5256 return true;
5257 return false;
5258 }
5259
rtw89_fw_suit_get(struct rtw89_dev * rtwdev,enum rtw89_fw_type type)5260 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev,
5261 enum rtw89_fw_type type)
5262 {
5263 struct rtw89_fw_info *fw_info = &rtwdev->fw;
5264
5265 switch (type) {
5266 case RTW89_FW_WOWLAN:
5267 return &fw_info->wowlan;
5268 case RTW89_FW_LOGFMT:
5269 return &fw_info->log.suit;
5270 case RTW89_FW_BBMCU0:
5271 return &fw_info->bbmcu0;
5272 case RTW89_FW_BBMCU1:
5273 return &fw_info->bbmcu1;
5274 default:
5275 break;
5276 }
5277
5278 return &fw_info->normal;
5279 }
5280
rtw89_alloc_skb_for_rx(struct rtw89_dev * rtwdev,unsigned int length)5281 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev,
5282 unsigned int length)
5283 {
5284 struct sk_buff *skb;
5285
5286 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
5287 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM);
5288 if (!skb)
5289 return NULL;
5290
5291 skb_reserve(skb, RTW89_RADIOTAP_ROOM);
5292 return skb;
5293 }
5294
5295 return dev_alloc_skb(length);
5296 }
5297
rtw89_core_tx_wait_complete(struct rtw89_dev * rtwdev,struct rtw89_tx_skb_data * skb_data,bool tx_done)5298 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev,
5299 struct rtw89_tx_skb_data *skb_data,
5300 bool tx_done)
5301 {
5302 struct rtw89_tx_wait_info *wait;
5303
5304 rcu_read_lock();
5305
5306 wait = rcu_dereference(skb_data->wait);
5307 if (!wait)
5308 goto out;
5309
5310 wait->tx_done = tx_done;
5311 complete(&wait->completion);
5312
5313 out:
5314 rcu_read_unlock();
5315 }
5316
5317 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
5318 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel);
5319 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
5320 struct sk_buff *skb, bool fwdl);
5321 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel);
5322 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
5323 int qsel, unsigned int timeout);
5324 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
5325 struct rtw89_tx_desc_info *desc_info,
5326 void *txdesc);
5327 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
5328 struct rtw89_tx_desc_info *desc_info,
5329 void *txdesc);
5330 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
5331 struct rtw89_tx_desc_info *desc_info,
5332 void *txdesc);
5333 void rtw89_core_rx(struct rtw89_dev *rtwdev,
5334 struct rtw89_rx_desc_info *desc_info,
5335 struct sk_buff *skb);
5336 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
5337 struct rtw89_rx_desc_info *desc_info,
5338 u8 *data, u32 data_offset);
5339 void rtw89_core_napi_start(struct rtw89_dev *rtwdev);
5340 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev);
5341 void rtw89_core_napi_init(struct rtw89_dev *rtwdev);
5342 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev);
5343 int rtw89_core_sta_add(struct rtw89_dev *rtwdev,
5344 struct ieee80211_vif *vif,
5345 struct ieee80211_sta *sta);
5346 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev,
5347 struct ieee80211_vif *vif,
5348 struct ieee80211_sta *sta);
5349 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev,
5350 struct ieee80211_vif *vif,
5351 struct ieee80211_sta *sta);
5352 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev,
5353 struct ieee80211_vif *vif,
5354 struct ieee80211_sta *sta);
5355 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev,
5356 struct ieee80211_vif *vif,
5357 struct ieee80211_sta *sta);
5358 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
5359 struct ieee80211_sta *sta,
5360 struct cfg80211_tid_config *tid_config);
5361 int rtw89_core_init(struct rtw89_dev *rtwdev);
5362 void rtw89_core_deinit(struct rtw89_dev *rtwdev);
5363 int rtw89_core_register(struct rtw89_dev *rtwdev);
5364 void rtw89_core_unregister(struct rtw89_dev *rtwdev);
5365 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
5366 u32 bus_data_size,
5367 const struct rtw89_chip_info *chip);
5368 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev);
5369 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev);
5370 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef);
5371 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef,
5372 struct rtw89_chan *chan);
5373 void rtw89_set_channel(struct rtw89_dev *rtwdev);
5374 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
5375 struct rtw89_chan *chan);
5376 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size);
5377 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit);
5378 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits);
5379 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
5380 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx);
5381 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
5382 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx);
5383 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc);
5384 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev);
5385 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate);
5386 int rtw89_regd_setup(struct rtw89_dev *rtwdev);
5387 int rtw89_regd_init(struct rtw89_dev *rtwdev,
5388 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request));
5389 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request);
5390 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
5391 struct rtw89_traffic_stats *stats);
5392 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond);
5393 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
5394 const struct rtw89_completion_data *data);
5395 int rtw89_core_start(struct rtw89_dev *rtwdev);
5396 void rtw89_core_stop(struct rtw89_dev *rtwdev);
5397 void rtw89_core_update_beacon_work(struct work_struct *work);
5398 void rtw89_roc_work(struct work_struct *work);
5399 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
5400 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
5401 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
5402 const u8 *mac_addr, bool hw_scan);
5403 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
5404 struct ieee80211_vif *vif, bool hw_scan);
5405 void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev,
5406 struct rtw89_vif *rtwvif, bool active);
5407 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event);
5408
5409 #endif
5410