1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_TXRX_H__
6 #define __RTW89_TXRX_H__
7
8 #include "debug.h"
9
10 #define DATA_RATE_MODE_CTRL_MASK GENMASK(8, 7)
11 #define DATA_RATE_MODE_CTRL_MASK_V1 GENMASK(10, 8)
12 #define DATA_RATE_NOT_HT_IDX_MASK GENMASK(3, 0)
13 #define DATA_RATE_MODE_NON_HT 0x0
14 #define DATA_RATE_HT_IDX_MASK GENMASK(4, 0)
15 #define DATA_RATE_HT_IDX_MASK_V1 GENMASK(4, 0)
16 #define DATA_RATE_MODE_HT 0x1
17 #define DATA_RATE_VHT_HE_NSS_MASK GENMASK(6, 4)
18 #define DATA_RATE_VHT_HE_IDX_MASK GENMASK(3, 0)
19 #define DATA_RATE_NSS_MASK_V1 GENMASK(7, 5)
20 #define DATA_RATE_MCS_MASK_V1 GENMASK(4, 0)
21 #define DATA_RATE_MODE_VHT 0x2
22 #define DATA_RATE_MODE_HE 0x3
23 #define DATA_RATE_MODE_EHT 0x4
24
rtw89_get_data_rate_mode(struct rtw89_dev * rtwdev,u16 hw_rate)25 static inline u8 rtw89_get_data_rate_mode(struct rtw89_dev *rtwdev, u16 hw_rate)
26 {
27 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
28 return u16_get_bits(hw_rate, DATA_RATE_MODE_CTRL_MASK_V1);
29
30 return u16_get_bits(hw_rate, DATA_RATE_MODE_CTRL_MASK);
31 }
32
rtw89_get_data_not_ht_idx(struct rtw89_dev * rtwdev,u16 hw_rate)33 static inline u8 rtw89_get_data_not_ht_idx(struct rtw89_dev *rtwdev, u16 hw_rate)
34 {
35 return u16_get_bits(hw_rate, DATA_RATE_NOT_HT_IDX_MASK);
36 }
37
rtw89_get_data_ht_mcs(struct rtw89_dev * rtwdev,u16 hw_rate)38 static inline u8 rtw89_get_data_ht_mcs(struct rtw89_dev *rtwdev, u16 hw_rate)
39 {
40 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
41 return u16_get_bits(hw_rate, DATA_RATE_HT_IDX_MASK_V1);
42
43 return u16_get_bits(hw_rate, DATA_RATE_HT_IDX_MASK);
44 }
45
rtw89_get_data_mcs(struct rtw89_dev * rtwdev,u16 hw_rate)46 static inline u8 rtw89_get_data_mcs(struct rtw89_dev *rtwdev, u16 hw_rate)
47 {
48 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
49 return u16_get_bits(hw_rate, DATA_RATE_MCS_MASK_V1);
50
51 return u16_get_bits(hw_rate, DATA_RATE_VHT_HE_IDX_MASK);
52 }
53
rtw89_get_data_nss(struct rtw89_dev * rtwdev,u16 hw_rate)54 static inline u8 rtw89_get_data_nss(struct rtw89_dev *rtwdev, u16 hw_rate)
55 {
56 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
57 return u16_get_bits(hw_rate, DATA_RATE_NSS_MASK_V1);
58
59 return u16_get_bits(hw_rate, DATA_RATE_VHT_HE_NSS_MASK);
60 }
61
62 /* TX WD BODY DWORD 0 */
63 #define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24)
64 #define RTW89_TXWD_BODY0_WP_OFFSET_V1 GENMASK(28, 24)
65 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23)
66 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22)
67 #define RTW89_TXWD_BODY0_FW_DL BIT(20)
68 #define RTW89_TXWD_BODY0_CHANNEL_DMA GENMASK(19, 16)
69 #define RTW89_TXWD_BODY0_HDR_LLC_LEN GENMASK(15, 11)
70 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7)
71 #define RTW89_TXWD_BODY0_HW_AMSDU BIT(5)
72 #define RTW89_TXWD_BODY0_HW_SSN_SEL GENMASK(3, 2)
73 #define RTW89_TXWD_BODY0_HW_SSN_MODE GENMASK(1, 0)
74
75 /* TX WD BODY DWORD 1 */
76 #define RTW89_TXWD_BODY1_ADDR_INFO_NUM GENMASK(31, 26)
77 #define RTW89_TXWD_BODY1_PAYLOAD_ID GENMASK(31, 16)
78 #define RTW89_TXWD_BODY1_SEC_KEYID GENMASK(5, 4)
79 #define RTW89_TXWD_BODY1_SEC_TYPE GENMASK(3, 0)
80
81 /* TX WD BODY DWORD 2 */
82 #define RTW89_TXWD_BODY2_MACID GENMASK(30, 24)
83 #define RTW89_TXWD_BODY2_TID_INDICATE BIT(23)
84 #define RTW89_TXWD_BODY2_QSEL GENMASK(22, 17)
85 #define RTW89_TXWD_BODY2_TXPKT_SIZE GENMASK(13, 0)
86
87 /* TX WD BODY DWORD 3 */
88 #define RTW89_TXWD_BODY3_BK BIT(13)
89 #define RTW89_TXWD_BODY3_AGG_EN BIT(12)
90 #define RTW89_TXWD_BODY3_SW_SEQ GENMASK(11, 0)
91
92 /* TX WD BODY DWORD 4 */
93 #define RTW89_TXWD_BODY4_SEC_IV_L1 GENMASK(31, 24)
94 #define RTW89_TXWD_BODY4_SEC_IV_L0 GENMASK(23, 16)
95
96 /* TX WD BODY DWORD 5 */
97 #define RTW89_TXWD_BODY5_SEC_IV_H5 GENMASK(31, 24)
98 #define RTW89_TXWD_BODY5_SEC_IV_H4 GENMASK(23, 16)
99 #define RTW89_TXWD_BODY5_SEC_IV_H3 GENMASK(15, 8)
100 #define RTW89_TXWD_BODY5_SEC_IV_H2 GENMASK(7, 0)
101
102 /* TX WD BODY DWORD 6 (V1) */
103
104 /* TX WD BODY DWORD 7 (V1) */
105 #define RTW89_TXWD_BODY7_USE_RATE_V1 BIT(31)
106 #define RTW89_TXWD_BODY7_DATA_BW GENMASK(29, 28)
107 #define RTW89_TXWD_BODY7_GI_LTF GENMASK(27, 25)
108 #define RTW89_TXWD_BODY7_DATA_RATE GENMASK(24, 16)
109
110 /* TX WD INFO DWORD 0 */
111 #define RTW89_TXWD_INFO0_USE_RATE BIT(30)
112 #define RTW89_TXWD_INFO0_DATA_BW GENMASK(29, 28)
113 #define RTW89_TXWD_INFO0_GI_LTF GENMASK(27, 25)
114 #define RTW89_TXWD_INFO0_DATA_RATE GENMASK(24, 16)
115 #define RTW89_TXWD_INFO0_DATA_ER BIT(15)
116 #define RTW89_TXWD_INFO0_DISDATAFB BIT(10)
117 #define RTW89_TXWD_INFO0_DATA_BW_ER BIT(8)
118 #define RTW89_TXWD_INFO0_MULTIPORT_ID GENMASK(6, 4)
119
120 /* TX WD INFO DWORD 1 */
121 #define RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(24, 16)
122 #define RTW89_TXWD_INFO1_A_CTRL_BSR BIT(14)
123 #define RTW89_TXWD_INFO1_MAX_AGGNUM GENMASK(7, 0)
124
125 /* TX WD INFO DWORD 2 */
126 #define RTW89_TXWD_INFO2_AMPDU_DENSITY GENMASK(20, 18)
127 #define RTW89_TXWD_INFO2_SEC_TYPE GENMASK(12, 9)
128 #define RTW89_TXWD_INFO2_SEC_HW_ENC BIT(8)
129 #define RTW89_TXWD_INFO2_FORCE_KEY_EN BIT(8)
130 #define RTW89_TXWD_INFO2_SEC_CAM_IDX GENMASK(7, 0)
131
132 /* TX WD INFO DWORD 3 */
133
134 /* TX WD INFO DWORD 4 */
135 #define RTW89_TXWD_INFO4_RTS_EN BIT(27)
136 #define RTW89_TXWD_INFO4_HW_RTS_EN BIT(31)
137
138 /* TX WD INFO DWORD 5 */
139
140 /* RX WD dword0 */
141 #define AX_RXD_RPKT_LEN_MASK GENMASK(13, 0)
142 #define AX_RXD_SHIFT_MASK GENMASK(15, 14)
143 #define AX_RXD_WL_HD_IV_LEN_MASK GENMASK(21, 16)
144 #define AX_RXD_BB_SEL BIT(22)
145 #define AX_RXD_MAC_INFO_VLD BIT(23)
146 #define AX_RXD_RPKT_TYPE_MASK GENMASK(27, 24)
147 #define AX_RXD_DRV_INFO_SIZE_MASK GENMASK(30, 28)
148 #define AX_RXD_LONG_RXD BIT(31)
149
150 /* RX WD dword1 */
151 #define AX_RXD_PPDU_TYPE_MASK GENMASK(3, 0)
152 #define AX_RXD_PPDU_CNT_MASK GENMASK(6, 4)
153 #define AX_RXD_SR_EN BIT(7)
154 #define AX_RXD_USER_ID_MASK GENMASK(15, 8)
155 #define AX_RXD_USER_ID_v1_MASK GENMASK(13, 8)
156 #define AX_RXD_RX_DATARATE_MASK GENMASK(24, 16)
157 #define AX_RXD_RX_GI_LTF_MASK GENMASK(27, 25)
158 #define AX_RXD_NON_SRG_PPDU BIT(28)
159 #define AX_RXD_INTER_PPDU BIT(29)
160 #define AX_RXD_NON_SRG_PPDU_v1 BIT(14)
161 #define AX_RXD_INTER_PPDU_v1 BIT(15)
162 #define AX_RXD_BW_MASK GENMASK(31, 30)
163 #define AX_RXD_BW_v1_MASK GENMASK(31, 29)
164
165 /* RX WD dword2 */
166 #define AX_RXD_FREERUN_CNT_MASK GENMASK(31, 0)
167
168 /* RX WD dword3 */
169 #define AX_RXD_A1_MATCH BIT(0)
170 #define AX_RXD_SW_DEC BIT(1)
171 #define AX_RXD_HW_DEC BIT(2)
172 #define AX_RXD_AMPDU BIT(3)
173 #define AX_RXD_AMPDU_END_PKT BIT(4)
174 #define AX_RXD_AMSDU BIT(5)
175 #define AX_RXD_AMSDU_CUT BIT(6)
176 #define AX_RXD_LAST_MSDU BIT(7)
177 #define AX_RXD_BYPASS BIT(8)
178 #define AX_RXD_CRC32_ERR BIT(9)
179 #define AX_RXD_ICV_ERR BIT(10)
180 #define AX_RXD_MAGIC_WAKE BIT(11)
181 #define AX_RXD_UNICAST_WAKE BIT(12)
182 #define AX_RXD_PATTERN_WAKE BIT(13)
183 #define AX_RXD_GET_CH_INFO_MASK GENMASK(15, 14)
184 #define AX_RXD_PATTERN_IDX_MASK GENMASK(20, 16)
185 #define AX_RXD_TARGET_IDC_MASK GENMASK(23, 21)
186 #define AX_RXD_CHKSUM_OFFLOAD_EN BIT(24)
187 #define AX_RXD_WITH_LLC BIT(25)
188 #define AX_RXD_RX_STATISTICS BIT(26)
189
190 /* RX WD dword4 */
191 #define AX_RXD_TYPE_MASK GENMASK(1, 0)
192 #define AX_RXD_MC BIT(2)
193 #define AX_RXD_BC BIT(3)
194 #define AX_RXD_MD BIT(4)
195 #define AX_RXD_MF BIT(5)
196 #define AX_RXD_PWR BIT(6)
197 #define AX_RXD_QOS BIT(7)
198 #define AX_RXD_TID_MASK GENMASK(11, 8)
199 #define AX_RXD_EOSP BIT(12)
200 #define AX_RXD_HTC BIT(13)
201 #define AX_RXD_QNULL BIT(14)
202 #define AX_RXD_SEQ_MASK GENMASK(27, 16)
203 #define AX_RXD_FRAG_MASK GENMASK(31, 28)
204
205 /* RX WD dword5 */
206 #define AX_RXD_SEC_CAM_IDX_MASK GENMASK(7, 0)
207 #define AX_RXD_ADDR_CAM_MASK GENMASK(15, 8)
208 #define AX_RXD_MAC_ID_MASK GENMASK(23, 16)
209 #define AX_RXD_RX_PL_ID_MASK GENMASK(27, 24)
210 #define AX_RXD_ADDR_CAM_VLD BIT(28)
211 #define AX_RXD_ADDR_FWD_EN BIT(29)
212 #define AX_RXD_RX_PL_MATCH BIT(30)
213
214 /* RX WD dword6 */
215 #define AX_RXD_MAC_ADDR_MASK GENMASK(31, 0)
216
217 /* RX WD dword7 */
218 #define AX_RXD_MAC_ADDR_H_MASK GENMASK(15, 0)
219 #define AX_RXD_SMART_ANT BIT(16)
220 #define AX_RXD_SEC_TYPE_MASK GENMASK(20, 17)
221 #define AX_RXD_HDR_CNV BIT(21)
222 #define AX_RXD_HDR_OFFSET_MASK GENMASK(26, 22)
223 #define AX_RXD_BIP_KEYID BIT(27)
224 #define AX_RXD_BIP_ENC BIT(28)
225
226 struct rtw89_rxinfo_user {
227 __le32 w0;
228 };
229
230 #define RTW89_RXINFO_USER_MAC_ID_VALID BIT(0)
231 #define RTW89_RXINFO_USER_DATA BIT(1)
232 #define RTW89_RXINFO_USER_CTRL BIT(2)
233 #define RTW89_RXINFO_USER_MGMT BIT(3)
234 #define RTW89_RXINFO_USER_BCM BIT(4)
235 #define RTW89_RXINFO_USER_MACID GENMASK(15, 8)
236
237 struct rtw89_rxinfo {
238 __le32 w0;
239 __le32 w1;
240 struct rtw89_rxinfo_user user[];
241 } __packed;
242
243 #define RTW89_RXINFO_W0_USR_NUM GENMASK(3, 0)
244 #define RTW89_RXINFO_W0_FW_DEFINE GENMASK(15, 8)
245 #define RTW89_RXINFO_W0_LSIG_LEN GENMASK(27, 16)
246 #define RTW89_RXINFO_W0_IS_TO_SELF BIT(28)
247 #define RTW89_RXINFO_W0_RX_CNT_VLD BIT(29)
248 #define RTW89_RXINFO_W0_LONG_RXD GENMASK(31, 30)
249 #define RTW89_RXINFO_W1_SERVICE GENMASK(15, 0)
250 #define RTW89_RXINFO_W1_PLCP_LEN GENMASK(23, 16)
251
252 struct rtw89_phy_sts_hdr {
253 __le32 w0;
254 __le32 w1;
255 } __packed;
256
257 #define RTW89_PHY_STS_HDR_W0_IE_MAP GENMASK(4, 0)
258 #define RTW89_PHY_STS_HDR_W0_LEN GENMASK(15, 8)
259 #define RTW89_PHY_STS_HDR_W0_RSSI_AVG GENMASK(31, 24)
260 #define RTW89_PHY_STS_HDR_W1_RSSI_A GENMASK(7, 0)
261 #define RTW89_PHY_STS_HDR_W1_RSSI_B GENMASK(15, 8)
262 #define RTW89_PHY_STS_HDR_W1_RSSI_C GENMASK(23, 16)
263 #define RTW89_PHY_STS_HDR_W1_RSSI_D GENMASK(31, 24)
264
265 struct rtw89_phy_sts_iehdr {
266 __le32 w0;
267 };
268
269 #define RTW89_PHY_STS_IEHDR_TYPE GENMASK(4, 0)
270 #define RTW89_PHY_STS_IEHDR_LEN GENMASK(11, 5)
271
272 struct rtw89_phy_sts_ie0 {
273 __le32 w0;
274 __le32 w1;
275 __le32 w2;
276 } __packed;
277
278 #define RTW89_PHY_STS_IE01_W0_CH_IDX GENMASK(23, 16)
279 #define RTW89_PHY_STS_IE01_W1_FD_CFO GENMASK(19, 8)
280 #define RTW89_PHY_STS_IE01_W1_PREMB_CFO GENMASK(31, 20)
281 #define RTW89_PHY_STS_IE01_W2_AVG_SNR GENMASK(5, 0)
282 #define RTW89_PHY_STS_IE01_W2_EVM_MAX GENMASK(15, 8)
283 #define RTW89_PHY_STS_IE01_W2_EVM_MIN GENMASK(23, 16)
284
285 enum rtw89_tx_channel {
286 RTW89_TXCH_ACH0 = 0,
287 RTW89_TXCH_ACH1 = 1,
288 RTW89_TXCH_ACH2 = 2,
289 RTW89_TXCH_ACH3 = 3,
290 RTW89_TXCH_ACH4 = 4,
291 RTW89_TXCH_ACH5 = 5,
292 RTW89_TXCH_ACH6 = 6,
293 RTW89_TXCH_ACH7 = 7,
294 RTW89_TXCH_CH8 = 8, /* MGMT Band 0 */
295 RTW89_TXCH_CH9 = 9, /* HI Band 0 */
296 RTW89_TXCH_CH10 = 10, /* MGMT Band 1 */
297 RTW89_TXCH_CH11 = 11, /* HI Band 1 */
298 RTW89_TXCH_CH12 = 12, /* FW CMD */
299
300 /* keep last */
301 RTW89_TXCH_NUM,
302 RTW89_TXCH_MAX = RTW89_TXCH_NUM - 1
303 };
304
305 enum rtw89_rx_channel {
306 RTW89_RXCH_RXQ = 0,
307 RTW89_RXCH_RPQ = 1,
308
309 /* keep last */
310 RTW89_RXCH_NUM,
311 RTW89_RXCH_MAX = RTW89_RXCH_NUM - 1
312 };
313
314 enum rtw89_tx_qsel {
315 RTW89_TX_QSEL_BE_0 = 0x00,
316 RTW89_TX_QSEL_BK_0 = 0x01,
317 RTW89_TX_QSEL_VI_0 = 0x02,
318 RTW89_TX_QSEL_VO_0 = 0x03,
319 RTW89_TX_QSEL_BE_1 = 0x04,
320 RTW89_TX_QSEL_BK_1 = 0x05,
321 RTW89_TX_QSEL_VI_1 = 0x06,
322 RTW89_TX_QSEL_VO_1 = 0x07,
323 RTW89_TX_QSEL_BE_2 = 0x08,
324 RTW89_TX_QSEL_BK_2 = 0x09,
325 RTW89_TX_QSEL_VI_2 = 0x0a,
326 RTW89_TX_QSEL_VO_2 = 0x0b,
327 RTW89_TX_QSEL_BE_3 = 0x0c,
328 RTW89_TX_QSEL_BK_3 = 0x0d,
329 RTW89_TX_QSEL_VI_3 = 0x0e,
330 RTW89_TX_QSEL_VO_3 = 0x0f,
331 RTW89_TX_QSEL_B0_BCN = 0x10,
332 RTW89_TX_QSEL_B0_HI = 0x11,
333 RTW89_TX_QSEL_B0_MGMT = 0x12,
334 RTW89_TX_QSEL_B0_NOPS = 0x13,
335 RTW89_TX_QSEL_B0_MGMT_FAST = 0x14,
336 /* reserved */
337 /* reserved */
338 /* reserved */
339 RTW89_TX_QSEL_B1_BCN = 0x18,
340 RTW89_TX_QSEL_B1_HI = 0x19,
341 RTW89_TX_QSEL_B1_MGMT = 0x1a,
342 RTW89_TX_QSEL_B1_NOPS = 0x1b,
343 RTW89_TX_QSEL_B1_MGMT_FAST = 0x1c,
344 /* reserved */
345 /* reserved */
346 /* reserved */
347 };
348
rtw89_core_get_qsel(struct rtw89_dev * rtwdev,u8 tid)349 static inline u8 rtw89_core_get_qsel(struct rtw89_dev *rtwdev, u8 tid)
350 {
351 switch (tid) {
352 default:
353 rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid);
354 fallthrough;
355 case 0:
356 case 3:
357 return RTW89_TX_QSEL_BE_0;
358 case 1:
359 case 2:
360 return RTW89_TX_QSEL_BK_0;
361 case 4:
362 case 5:
363 return RTW89_TX_QSEL_VI_0;
364 case 6:
365 case 7:
366 return RTW89_TX_QSEL_VO_0;
367 }
368 }
369
rtw89_core_get_ch_dma(struct rtw89_dev * rtwdev,u8 qsel)370 static inline u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel)
371 {
372 switch (qsel) {
373 default:
374 rtw89_warn(rtwdev, "Cannot map qsel to dma: %d\n", qsel);
375 fallthrough;
376 case RTW89_TX_QSEL_BE_0:
377 return RTW89_TXCH_ACH0;
378 case RTW89_TX_QSEL_BK_0:
379 return RTW89_TXCH_ACH1;
380 case RTW89_TX_QSEL_VI_0:
381 return RTW89_TXCH_ACH2;
382 case RTW89_TX_QSEL_VO_0:
383 return RTW89_TXCH_ACH3;
384 case RTW89_TX_QSEL_B0_MGMT:
385 return RTW89_TXCH_CH8;
386 case RTW89_TX_QSEL_B0_HI:
387 return RTW89_TXCH_CH9;
388 case RTW89_TX_QSEL_B1_MGMT:
389 return RTW89_TXCH_CH10;
390 case RTW89_TX_QSEL_B1_HI:
391 return RTW89_TXCH_CH11;
392 }
393 }
394
rtw89_core_get_tid_indicate(struct rtw89_dev * rtwdev,u8 tid)395 static inline u8 rtw89_core_get_tid_indicate(struct rtw89_dev *rtwdev, u8 tid)
396 {
397 switch (tid) {
398 case 3:
399 case 2:
400 case 5:
401 case 7:
402 return 1;
403 default:
404 rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid);
405 fallthrough;
406 case 0:
407 case 1:
408 case 4:
409 case 6:
410 return 0;
411 }
412 }
413
414 #endif
415