1 /* 2 * Copyright © 2012-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DPLL_MGR_H_ 26 #define _INTEL_DPLL_MGR_H_ 27 28 #include <linux/types.h> 29 30 #include "intel_wakeref.h" 31 32 enum tc_port; 33 struct drm_i915_private; 34 struct intel_atomic_state; 35 struct intel_crtc; 36 struct intel_crtc_state; 37 struct intel_encoder; 38 struct intel_shared_dpll; 39 struct intel_shared_dpll_funcs; 40 41 /** 42 * enum intel_dpll_id - possible DPLL ids 43 * 44 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0. 45 */ 46 enum intel_dpll_id { 47 /** 48 * @DPLL_ID_PRIVATE: non-shared dpll in use 49 */ 50 DPLL_ID_PRIVATE = -1, 51 52 /** 53 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB 54 */ 55 DPLL_ID_PCH_PLL_A = 0, 56 /** 57 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB 58 */ 59 DPLL_ID_PCH_PLL_B = 1, 60 61 62 /** 63 * @DPLL_ID_WRPLL1: HSW and BDW WRPLL1 64 */ 65 DPLL_ID_WRPLL1 = 0, 66 /** 67 * @DPLL_ID_WRPLL2: HSW and BDW WRPLL2 68 */ 69 DPLL_ID_WRPLL2 = 1, 70 /** 71 * @DPLL_ID_SPLL: HSW and BDW SPLL 72 */ 73 DPLL_ID_SPLL = 2, 74 /** 75 * @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL 76 */ 77 DPLL_ID_LCPLL_810 = 3, 78 /** 79 * @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL 80 */ 81 DPLL_ID_LCPLL_1350 = 4, 82 /** 83 * @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL 84 */ 85 DPLL_ID_LCPLL_2700 = 5, 86 87 88 /** 89 * @DPLL_ID_SKL_DPLL0: SKL and later DPLL0 90 */ 91 DPLL_ID_SKL_DPLL0 = 0, 92 /** 93 * @DPLL_ID_SKL_DPLL1: SKL and later DPLL1 94 */ 95 DPLL_ID_SKL_DPLL1 = 1, 96 /** 97 * @DPLL_ID_SKL_DPLL2: SKL and later DPLL2 98 */ 99 DPLL_ID_SKL_DPLL2 = 2, 100 /** 101 * @DPLL_ID_SKL_DPLL3: SKL and later DPLL3 102 */ 103 DPLL_ID_SKL_DPLL3 = 3, 104 105 106 /** 107 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0 108 */ 109 DPLL_ID_ICL_DPLL0 = 0, 110 /** 111 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1 112 */ 113 DPLL_ID_ICL_DPLL1 = 1, 114 /** 115 * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4 116 */ 117 DPLL_ID_EHL_DPLL4 = 2, 118 /** 119 * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL 120 */ 121 DPLL_ID_ICL_TBTPLL = 2, 122 /** 123 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C), 124 * TGL TC PLL 1 port 1 (TC1) 125 */ 126 DPLL_ID_ICL_MGPLL1 = 3, 127 /** 128 * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D) 129 * TGL TC PLL 1 port 2 (TC2) 130 */ 131 DPLL_ID_ICL_MGPLL2 = 4, 132 /** 133 * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E) 134 * TGL TC PLL 1 port 3 (TC3) 135 */ 136 DPLL_ID_ICL_MGPLL3 = 5, 137 /** 138 * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F) 139 * TGL TC PLL 1 port 4 (TC4) 140 */ 141 DPLL_ID_ICL_MGPLL4 = 6, 142 /** 143 * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5) 144 */ 145 DPLL_ID_TGL_MGPLL5 = 7, 146 /** 147 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6) 148 */ 149 DPLL_ID_TGL_MGPLL6 = 8, 150 151 /** 152 * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0 153 */ 154 DPLL_ID_DG1_DPLL0 = 0, 155 /** 156 * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1 157 */ 158 DPLL_ID_DG1_DPLL1 = 1, 159 /** 160 * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2 161 */ 162 DPLL_ID_DG1_DPLL2 = 2, 163 /** 164 * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3 165 */ 166 DPLL_ID_DG1_DPLL3 = 3, 167 }; 168 169 #define I915_NUM_PLLS 9 170 171 enum icl_port_dpll_id { 172 ICL_PORT_DPLL_DEFAULT, 173 ICL_PORT_DPLL_MG_PHY, 174 175 ICL_PORT_DPLL_COUNT, 176 }; 177 178 struct intel_dpll_hw_state { 179 /* i9xx, pch plls */ 180 u32 dpll; 181 u32 dpll_md; 182 u32 fp0; 183 u32 fp1; 184 185 /* hsw, bdw */ 186 u32 wrpll; 187 u32 spll; 188 189 /* skl */ 190 /* 191 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in 192 * lower part of ctrl1 and they get shifted into position when writing 193 * the register. This allows us to easily compare the state to share 194 * the DPLL. 195 */ 196 u32 ctrl1; 197 /* HDMI only, 0 when used for DP */ 198 u32 cfgcr1, cfgcr2; 199 200 /* icl */ 201 u32 cfgcr0; 202 203 /* tgl */ 204 u32 div0; 205 206 /* bxt */ 207 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; 208 209 /* 210 * ICL uses the following, already defined: 211 * u32 cfgcr0, cfgcr1; 212 */ 213 u32 mg_refclkin_ctl; 214 u32 mg_clktop2_coreclkctl1; 215 u32 mg_clktop2_hsclkctl; 216 u32 mg_pll_div0; 217 u32 mg_pll_div1; 218 u32 mg_pll_lf; 219 u32 mg_pll_frac_lock; 220 u32 mg_pll_ssc; 221 u32 mg_pll_bias; 222 u32 mg_pll_tdc_coldst_bias; 223 u32 mg_pll_bias_mask; 224 u32 mg_pll_tdc_coldst_bias_mask; 225 }; 226 227 /** 228 * struct intel_shared_dpll_state - hold the DPLL atomic state 229 * 230 * This structure holds an atomic state for the DPLL, that can represent 231 * either its current state (in struct &intel_shared_dpll) or a desired 232 * future state which would be applied by an atomic mode set (stored in 233 * a struct &intel_atomic_state). 234 * 235 * See also intel_reserve_shared_dplls() and intel_release_shared_dplls(). 236 */ 237 struct intel_shared_dpll_state { 238 /** 239 * @pipe_mask: mask of pipes using this DPLL, active or not 240 */ 241 u8 pipe_mask; 242 243 /** 244 * @hw_state: hardware configuration for the DPLL stored in 245 * struct &intel_dpll_hw_state. 246 */ 247 struct intel_dpll_hw_state hw_state; 248 }; 249 250 /** 251 * struct dpll_info - display PLL platform specific info 252 */ 253 struct dpll_info { 254 /** 255 * @name: DPLL name; used for logging 256 */ 257 const char *name; 258 259 /** 260 * @funcs: platform specific hooks 261 */ 262 const struct intel_shared_dpll_funcs *funcs; 263 264 /** 265 * @id: unique indentifier for this DPLL; should match the index in the 266 * dev_priv->shared_dplls array 267 */ 268 enum intel_dpll_id id; 269 270 #define INTEL_DPLL_ALWAYS_ON (1 << 0) 271 /** 272 * @flags: 273 * 274 * INTEL_DPLL_ALWAYS_ON 275 * Inform the state checker that the DPLL is kept enabled even if 276 * not in use by any CRTC. 277 */ 278 u32 flags; 279 }; 280 281 /** 282 * struct intel_shared_dpll - display PLL with tracked state and users 283 */ 284 struct intel_shared_dpll { 285 /** 286 * @state: 287 * 288 * Store the state for the pll, including its hw state 289 * and CRTCs using it. 290 */ 291 struct intel_shared_dpll_state state; 292 293 /** 294 * @active_mask: mask of active pipes (i.e. DPMS on) using this DPLL 295 */ 296 u8 active_mask; 297 298 /** 299 * @on: is the PLL actually active? Disabled during modeset 300 */ 301 bool on; 302 303 /** 304 * @info: platform specific info 305 */ 306 const struct dpll_info *info; 307 308 /** 309 * @wakeref: In some platforms a device-level runtime pm reference may 310 * need to be grabbed to disable DC states while this DPLL is enabled 311 */ 312 intel_wakeref_t wakeref; 313 }; 314 315 #define SKL_DPLL0 0 316 #define SKL_DPLL1 1 317 #define SKL_DPLL2 2 318 #define SKL_DPLL3 3 319 320 /* shared dpll functions */ 321 struct intel_shared_dpll * 322 intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, 323 enum intel_dpll_id id); 324 void assert_shared_dpll(struct drm_i915_private *dev_priv, 325 struct intel_shared_dpll *pll, 326 bool state); 327 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) 328 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) 329 int intel_compute_shared_dplls(struct intel_atomic_state *state, 330 struct intel_crtc *crtc, 331 struct intel_encoder *encoder); 332 int intel_reserve_shared_dplls(struct intel_atomic_state *state, 333 struct intel_crtc *crtc, 334 struct intel_encoder *encoder); 335 void intel_release_shared_dplls(struct intel_atomic_state *state, 336 struct intel_crtc *crtc); 337 void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc, 338 const struct intel_shared_dpll *pll, 339 struct intel_shared_dpll_state *shared_dpll_state); 340 void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, 341 enum icl_port_dpll_id port_dpll_id); 342 void intel_update_active_dpll(struct intel_atomic_state *state, 343 struct intel_crtc *crtc, 344 struct intel_encoder *encoder); 345 int intel_dpll_get_freq(struct drm_i915_private *i915, 346 const struct intel_shared_dpll *pll, 347 const struct intel_dpll_hw_state *pll_state); 348 bool intel_dpll_get_hw_state(struct drm_i915_private *i915, 349 struct intel_shared_dpll *pll, 350 struct intel_dpll_hw_state *hw_state); 351 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state); 352 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state); 353 void intel_shared_dpll_swap_state(struct intel_atomic_state *state); 354 void intel_shared_dpll_init(struct drm_i915_private *dev_priv); 355 void intel_dpll_update_ref_clks(struct drm_i915_private *dev_priv); 356 void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv); 357 void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv); 358 359 void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, 360 const struct intel_dpll_hw_state *hw_state); 361 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port); 362 bool intel_dpll_is_combophy(enum intel_dpll_id id); 363 364 void intel_shared_dpll_state_verify(struct intel_crtc *crtc, 365 struct intel_crtc_state *old_crtc_state, 366 struct intel_crtc_state *new_crtc_state); 367 void intel_shared_dpll_verify_disabled(struct drm_i915_private *i915); 368 369 #endif /* _INTEL_DPLL_MGR_H_ */ 370