1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */
3
4 #ifndef _WX_TYPE_H_
5 #define _WX_TYPE_H_
6
7 #include <linux/bitfield.h>
8 #include <linux/netdevice.h>
9 #include <linux/if_vlan.h>
10 #include <net/ip.h>
11
12 #define WX_NCSI_SUP 0x8000
13 #define WX_NCSI_MASK 0x8000
14 #define WX_WOL_SUP 0x4000
15 #define WX_WOL_MASK 0x4000
16
17 /* MSI-X capability fields masks */
18 #define WX_PCIE_MSIX_TBL_SZ_MASK 0x7FF
19 #define WX_PCI_LINK_STATUS 0xB2
20
21 /**************** Global Registers ****************************/
22 /* chip control Registers */
23 #define WX_MIS_PWR 0x10000
24 #define WX_MIS_RST 0x1000C
25 #define WX_MIS_RST_LAN_RST(_i) BIT((_i) + 1)
26 #define WX_MIS_RST_SW_RST BIT(0)
27 #define WX_MIS_ST 0x10028
28 #define WX_MIS_ST_MNG_INIT_DN BIT(0)
29 #define WX_MIS_SWSM 0x1002C
30 #define WX_MIS_SWSM_SMBI BIT(0)
31 #define WX_MIS_RST_ST 0x10030
32 #define WX_MIS_RST_ST_RST_INI_SHIFT 8
33 #define WX_MIS_RST_ST_RST_INIT (0xFF << WX_MIS_RST_ST_RST_INI_SHIFT)
34
35 /* FMGR Registers */
36 #define WX_SPI_CMD 0x10104
37 #define WX_SPI_CMD_READ_DWORD 0x1
38 #define WX_SPI_CLK_DIV 0x3
39 #define WX_SPI_CMD_CMD(_v) FIELD_PREP(GENMASK(30, 28), _v)
40 #define WX_SPI_CMD_CLK(_v) FIELD_PREP(GENMASK(27, 25), _v)
41 #define WX_SPI_CMD_ADDR(_v) FIELD_PREP(GENMASK(23, 0), _v)
42 #define WX_SPI_DATA 0x10108
43 #define WX_SPI_DATA_BYPASS BIT(31)
44 #define WX_SPI_DATA_OP_DONE BIT(0)
45 #define WX_SPI_STATUS 0x1010C
46 #define WX_SPI_STATUS_OPDONE BIT(0)
47 #define WX_SPI_STATUS_FLASH_BYPASS BIT(31)
48 #define WX_SPI_ILDR_STATUS 0x10120
49
50 /* Sensors for PVT(Process Voltage Temperature) */
51 #define WX_TS_EN 0x10304
52 #define WX_TS_EN_ENA BIT(0)
53 #define WX_TS_ALARM_THRE 0x1030C
54 #define WX_TS_DALARM_THRE 0x10310
55 #define WX_TS_INT_EN 0x10314
56 #define WX_TS_INT_EN_DALARM_INT_EN BIT(1)
57 #define WX_TS_INT_EN_ALARM_INT_EN BIT(0)
58 #define WX_TS_ALARM_ST 0x10318
59 #define WX_TS_ALARM_ST_DALARM BIT(1)
60 #define WX_TS_ALARM_ST_ALARM BIT(0)
61
62 /************************* Port Registers ************************************/
63 /* port cfg Registers */
64 #define WX_CFG_PORT_CTL 0x14400
65 #define WX_CFG_PORT_CTL_DRV_LOAD BIT(3)
66 #define WX_CFG_PORT_CTL_QINQ BIT(2)
67 #define WX_CFG_PORT_CTL_D_VLAN BIT(0) /* double vlan*/
68 #define WX_CFG_TAG_TPID(_i) (0x14430 + ((_i) * 4))
69 #define WX_CFG_PORT_CTL_NUM_VT_MASK GENMASK(13, 12) /* number of TVs */
70
71
72 /* GPIO Registers */
73 #define WX_GPIO_DR 0x14800
74 #define WX_GPIO_DR_0 BIT(0) /* SDP0 Data Value */
75 #define WX_GPIO_DR_1 BIT(1) /* SDP1 Data Value */
76 #define WX_GPIO_DDR 0x14804
77 #define WX_GPIO_DDR_0 BIT(0) /* SDP0 IO direction */
78 #define WX_GPIO_DDR_1 BIT(1) /* SDP1 IO direction */
79 #define WX_GPIO_CTL 0x14808
80 #define WX_GPIO_INTEN 0x14830
81 #define WX_GPIO_INTEN_0 BIT(0)
82 #define WX_GPIO_INTEN_1 BIT(1)
83 #define WX_GPIO_INTMASK 0x14834
84 #define WX_GPIO_INTTYPE_LEVEL 0x14838
85 #define WX_GPIO_POLARITY 0x1483C
86 #define WX_GPIO_INTSTATUS 0x14844
87 #define WX_GPIO_EOI 0x1484C
88 #define WX_GPIO_EXT 0x14850
89
90 /*********************** Transmit DMA registers **************************/
91 /* transmit global control */
92 #define WX_TDM_CTL 0x18000
93 /* TDM CTL BIT */
94 #define WX_TDM_CTL_TE BIT(0) /* Transmit Enable */
95 #define WX_TDM_PB_THRE(_i) (0x18020 + ((_i) * 4))
96 #define WX_TDM_RP_IDX 0x1820C
97 #define WX_TDM_RP_RATE 0x18404
98
99 /***************************** RDB registers *********************************/
100 /* receive packet buffer */
101 #define WX_RDB_PB_CTL 0x19000
102 #define WX_RDB_PB_CTL_RXEN BIT(31) /* Enable Receiver */
103 #define WX_RDB_PB_CTL_DISABLED BIT(0)
104 #define WX_RDB_PB_SZ(_i) (0x19020 + ((_i) * 4))
105 #define WX_RDB_PB_SZ_SHIFT 10
106 /* statistic */
107 #define WX_RDB_PFCMACDAL 0x19210
108 #define WX_RDB_PFCMACDAH 0x19214
109 /* ring assignment */
110 #define WX_RDB_PL_CFG(_i) (0x19300 + ((_i) * 4))
111 #define WX_RDB_PL_CFG_L4HDR BIT(1)
112 #define WX_RDB_PL_CFG_L3HDR BIT(2)
113 #define WX_RDB_PL_CFG_L2HDR BIT(3)
114 #define WX_RDB_PL_CFG_TUN_TUNHDR BIT(4)
115 #define WX_RDB_PL_CFG_TUN_OUTL2HDR BIT(5)
116 #define WX_RDB_RA_CTL 0x194F4
117 #define WX_RDB_RA_CTL_RSS_EN BIT(2) /* RSS Enable */
118
119 /******************************* PSR Registers *******************************/
120 /* psr control */
121 #define WX_PSR_CTL 0x15000
122 /* Header split receive */
123 #define WX_PSR_CTL_SW_EN BIT(18)
124 #define WX_PSR_CTL_RSC_ACK BIT(17)
125 #define WX_PSR_CTL_RSC_DIS BIT(16)
126 #define WX_PSR_CTL_PCSD BIT(13)
127 #define WX_PSR_CTL_IPPCSE BIT(12)
128 #define WX_PSR_CTL_BAM BIT(10)
129 #define WX_PSR_CTL_UPE BIT(9)
130 #define WX_PSR_CTL_MPE BIT(8)
131 #define WX_PSR_CTL_MFE BIT(7)
132 #define WX_PSR_CTL_MO_SHIFT 5
133 #define WX_PSR_CTL_MO (0x3 << WX_PSR_CTL_MO_SHIFT)
134 #define WX_PSR_CTL_TPE BIT(4)
135 #define WX_PSR_MAX_SZ 0x15020
136 #define WX_PSR_VLAN_CTL 0x15088
137 #define WX_PSR_VLAN_CTL_CFIEN BIT(29) /* bit 29 */
138 #define WX_PSR_VLAN_CTL_VFE BIT(30) /* bit 30 */
139 /* mcasst/ucast overflow tbl */
140 #define WX_PSR_MC_TBL(_i) (0x15200 + ((_i) * 4))
141 #define WX_PSR_UC_TBL(_i) (0x15400 + ((_i) * 4))
142
143 /* VM L2 contorl */
144 #define WX_PSR_VM_L2CTL(_i) (0x15600 + ((_i) * 4))
145 #define WX_PSR_VM_L2CTL_UPE BIT(4) /* unicast promiscuous */
146 #define WX_PSR_VM_L2CTL_VACC BIT(6) /* accept nomatched vlan */
147 #define WX_PSR_VM_L2CTL_AUPE BIT(8) /* accept untagged packets */
148 #define WX_PSR_VM_L2CTL_ROMPE BIT(9) /* accept packets in MTA tbl */
149 #define WX_PSR_VM_L2CTL_ROPE BIT(10) /* accept packets in UC tbl */
150 #define WX_PSR_VM_L2CTL_BAM BIT(11) /* accept broadcast packets */
151 #define WX_PSR_VM_L2CTL_MPE BIT(12) /* multicast promiscuous */
152
153 /* Management */
154 #define WX_PSR_MNG_FLEX_SEL 0x1582C
155 #define WX_PSR_MNG_FLEX_DW_L(_i) (0x15A00 + ((_i) * 16))
156 #define WX_PSR_MNG_FLEX_DW_H(_i) (0x15A04 + ((_i) * 16))
157 #define WX_PSR_MNG_FLEX_MSK(_i) (0x15A08 + ((_i) * 16))
158 #define WX_PSR_LAN_FLEX_SEL 0x15B8C
159 #define WX_PSR_LAN_FLEX_DW_L(_i) (0x15C00 + ((_i) * 16))
160 #define WX_PSR_LAN_FLEX_DW_H(_i) (0x15C04 + ((_i) * 16))
161 #define WX_PSR_LAN_FLEX_MSK(_i) (0x15C08 + ((_i) * 16))
162
163 #define WX_PSR_WKUP_CTL 0x15B80
164 /* Wake Up Filter Control Bit */
165 #define WX_PSR_WKUP_CTL_MAG BIT(1) /* Magic Packet Wakeup Enable */
166
167 /* vlan tbl */
168 #define WX_PSR_VLAN_TBL(_i) (0x16000 + ((_i) * 4))
169
170 /* mac switcher */
171 #define WX_PSR_MAC_SWC_AD_L 0x16200
172 #define WX_PSR_MAC_SWC_AD_H 0x16204
173 #define WX_PSR_MAC_SWC_AD_H_AD(v) FIELD_PREP(U16_MAX, v)
174 #define WX_PSR_MAC_SWC_AD_H_ADTYPE(v) FIELD_PREP(BIT(30), v)
175 #define WX_PSR_MAC_SWC_AD_H_AV BIT(31)
176 #define WX_PSR_MAC_SWC_VM_L 0x16208
177 #define WX_PSR_MAC_SWC_VM_H 0x1620C
178 #define WX_PSR_MAC_SWC_IDX 0x16210
179 #define WX_CLEAR_VMDQ_ALL 0xFFFFFFFFU
180
181 /* vlan switch */
182 #define WX_PSR_VLAN_SWC 0x16220
183 #define WX_PSR_VLAN_SWC_VM_L 0x16224
184 #define WX_PSR_VLAN_SWC_VM_H 0x16228
185 #define WX_PSR_VLAN_SWC_IDX 0x16230 /* 64 vlan entries */
186 /* VLAN pool filtering masks */
187 #define WX_PSR_VLAN_SWC_VIEN BIT(31) /* filter is valid */
188 #define WX_PSR_VLAN_SWC_ENTRIES 64
189
190 /********************************* RSEC **************************************/
191 /* general rsec */
192 #define WX_RSC_CTL 0x17000
193 #define WX_RSC_CTL_SAVE_MAC_ERR BIT(6)
194 #define WX_RSC_CTL_CRC_STRIP BIT(2)
195 #define WX_RSC_CTL_RX_DIS BIT(1)
196 #define WX_RSC_ST 0x17004
197 #define WX_RSC_ST_RSEC_RDY BIT(0)
198
199 /****************************** TDB ******************************************/
200 #define WX_TDB_PB_SZ(_i) (0x1CC00 + ((_i) * 4))
201 #define WX_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */
202
203 /****************************** TSEC *****************************************/
204 /* Security Control Registers */
205 #define WX_TSC_CTL 0x1D000
206 #define WX_TSC_CTL_TX_DIS BIT(1)
207 #define WX_TSC_CTL_TSEC_DIS BIT(0)
208 #define WX_TSC_ST 0x1D004
209 #define WX_TSC_ST_SECTX_RDY BIT(0)
210 #define WX_TSC_BUF_AE 0x1D00C
211 #define WX_TSC_BUF_AE_THR GENMASK(9, 0)
212
213 /************************************** MNG ********************************/
214 #define WX_MNG_SWFW_SYNC 0x1E008
215 #define WX_MNG_SWFW_SYNC_SW_MB BIT(2)
216 #define WX_MNG_SWFW_SYNC_SW_FLASH BIT(3)
217 #define WX_MNG_MBOX 0x1E100
218 #define WX_MNG_MBOX_CTL 0x1E044
219 #define WX_MNG_MBOX_CTL_SWRDY BIT(0)
220 #define WX_MNG_MBOX_CTL_FWRDY BIT(2)
221
222 /************************************* ETH MAC *****************************/
223 #define WX_MAC_TX_CFG 0x11000
224 #define WX_MAC_TX_CFG_TE BIT(0)
225 #define WX_MAC_TX_CFG_SPEED_MASK GENMASK(30, 29)
226 #define WX_MAC_TX_CFG_SPEED_10G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 0)
227 #define WX_MAC_TX_CFG_SPEED_1G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 3)
228 #define WX_MAC_RX_CFG 0x11004
229 #define WX_MAC_RX_CFG_RE BIT(0)
230 #define WX_MAC_RX_CFG_JE BIT(8)
231 #define WX_MAC_PKT_FLT 0x11008
232 #define WX_MAC_PKT_FLT_PR BIT(0) /* promiscuous mode */
233 #define WX_MAC_WDG_TIMEOUT 0x1100C
234 #define WX_MAC_RX_FLOW_CTRL 0x11090
235 #define WX_MAC_RX_FLOW_CTRL_RFE BIT(0) /* receive fc enable */
236 /* MDIO Registers */
237 #define WX_MSCA 0x11200
238 #define WX_MSCA_RA(v) FIELD_PREP(U16_MAX, v)
239 #define WX_MSCA_PA(v) FIELD_PREP(GENMASK(20, 16), v)
240 #define WX_MSCA_DA(v) FIELD_PREP(GENMASK(25, 21), v)
241 #define WX_MSCC 0x11204
242 #define WX_MSCC_CMD(v) FIELD_PREP(GENMASK(17, 16), v)
243
244 enum WX_MSCA_CMD_value {
245 WX_MSCA_CMD_RSV = 0,
246 WX_MSCA_CMD_WRITE,
247 WX_MSCA_CMD_POST_READ,
248 WX_MSCA_CMD_READ,
249 };
250
251 #define WX_MSCC_SADDR BIT(18)
252 #define WX_MSCC_BUSY BIT(22)
253 #define WX_MDIO_CLK(v) FIELD_PREP(GENMASK(21, 19), v)
254 #define WX_MMC_CONTROL 0x11800
255 #define WX_MMC_CONTROL_RSTONRD BIT(2) /* reset on read */
256
257 /********************************* BAR registers ***************************/
258 /* Interrupt Registers */
259 #define WX_BME_CTL 0x12020
260 #define WX_PX_MISC_IC 0x100
261 #define WX_PX_MISC_ICS 0x104
262 #define WX_PX_MISC_IEN 0x108
263 #define WX_PX_INTA 0x110
264 #define WX_PX_GPIE 0x118
265 #define WX_PX_GPIE_MODEL BIT(0)
266 #define WX_PX_IC(_i) (0x120 + (_i) * 4)
267 #define WX_PX_IMS(_i) (0x140 + (_i) * 4)
268 #define WX_PX_IMC(_i) (0x150 + (_i) * 4)
269 #define WX_PX_ISB_ADDR_L 0x160
270 #define WX_PX_ISB_ADDR_H 0x164
271 #define WX_PX_TRANSACTION_PENDING 0x168
272 #define WX_PX_ITRSEL 0x180
273 #define WX_PX_ITR(_i) (0x200 + (_i) * 4)
274 #define WX_PX_ITR_CNT_WDIS BIT(31)
275 #define WX_PX_MISC_IVAR 0x4FC
276 #define WX_PX_IVAR(_i) (0x500 + (_i) * 4)
277
278 #define WX_PX_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
279 #define WX_7K_ITR 595
280 #define WX_12K_ITR 336
281 #define WX_SP_MAX_EITR 0x00000FF8U
282 #define WX_EM_MAX_EITR 0x00007FFCU
283
284 /* transmit DMA Registers */
285 #define WX_PX_TR_BAL(_i) (0x03000 + ((_i) * 0x40))
286 #define WX_PX_TR_BAH(_i) (0x03004 + ((_i) * 0x40))
287 #define WX_PX_TR_WP(_i) (0x03008 + ((_i) * 0x40))
288 #define WX_PX_TR_RP(_i) (0x0300C + ((_i) * 0x40))
289 #define WX_PX_TR_CFG(_i) (0x03010 + ((_i) * 0x40))
290 /* Transmit Config masks */
291 #define WX_PX_TR_CFG_ENABLE BIT(0) /* Ena specific Tx Queue */
292 #define WX_PX_TR_CFG_TR_SIZE_SHIFT 1 /* tx desc number per ring */
293 #define WX_PX_TR_CFG_SWFLSH BIT(26) /* Tx Desc. wr-bk flushing */
294 #define WX_PX_TR_CFG_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */
295 #define WX_PX_TR_CFG_THRE_SHIFT 8
296
297 /* Receive DMA Registers */
298 #define WX_PX_RR_BAL(_i) (0x01000 + ((_i) * 0x40))
299 #define WX_PX_RR_BAH(_i) (0x01004 + ((_i) * 0x40))
300 #define WX_PX_RR_WP(_i) (0x01008 + ((_i) * 0x40))
301 #define WX_PX_RR_RP(_i) (0x0100C + ((_i) * 0x40))
302 #define WX_PX_RR_CFG(_i) (0x01010 + ((_i) * 0x40))
303 /* PX_RR_CFG bit definitions */
304 #define WX_PX_RR_CFG_VLAN BIT(31)
305 #define WX_PX_RR_CFG_SPLIT_MODE BIT(26)
306 #define WX_PX_RR_CFG_RR_THER_SHIFT 16
307 #define WX_PX_RR_CFG_RR_HDR_SZ GENMASK(15, 12)
308 #define WX_PX_RR_CFG_RR_BUF_SZ GENMASK(11, 8)
309 #define WX_PX_RR_CFG_BHDRSIZE_SHIFT 6 /* 64byte resolution (>> 6)
310 * + at bit 8 offset (<< 12)
311 * = (<< 6)
312 */
313 #define WX_PX_RR_CFG_BSIZEPKT_SHIFT 2 /* so many KBs */
314 #define WX_PX_RR_CFG_RR_SIZE_SHIFT 1
315 #define WX_PX_RR_CFG_RR_EN BIT(0)
316
317 /* Number of 80 microseconds we wait for PCI Express master disable */
318 #define WX_PCI_MASTER_DISABLE_TIMEOUT 80000
319
320 /****************** Manageablility Host Interface defines ********************/
321 #define WX_HI_MAX_BLOCK_BYTE_LENGTH 256 /* Num of bytes in range */
322 #define WX_HI_COMMAND_TIMEOUT 1000 /* Process HI command limit */
323
324 #define FW_READ_SHADOW_RAM_CMD 0x31
325 #define FW_READ_SHADOW_RAM_LEN 0x6
326 #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */
327 #define FW_NVM_DATA_OFFSET 3
328 #define FW_MAX_READ_BUFFER_SIZE 244
329 #define FW_RESET_CMD 0xDF
330 #define FW_RESET_LEN 0x2
331 #define FW_CEM_HDR_LEN 0x4
332 #define FW_CEM_CMD_RESERVED 0X0
333 #define FW_CEM_MAX_RETRIES 3
334 #define FW_CEM_RESP_STATUS_SUCCESS 0x1
335
336 #define WX_SW_REGION_PTR 0x1C
337
338 #define WX_MAC_STATE_DEFAULT 0x1
339 #define WX_MAC_STATE_MODIFIED 0x2
340 #define WX_MAC_STATE_IN_USE 0x4
341
342 #define WX_MAX_RXD 8192
343 #define WX_MAX_TXD 8192
344
345 #define WX_MAX_JUMBO_FRAME_SIZE 9432 /* max payload 9414 */
346 #define VMDQ_P(p) p
347
348 /* Supported Rx Buffer Sizes */
349 #define WX_RXBUFFER_256 256 /* Used for skb receive header */
350 #define WX_RXBUFFER_2K 2048
351 #define WX_MAX_RXBUFFER 16384 /* largest size for single descriptor */
352
353 #if MAX_SKB_FRAGS < 8
354 #define WX_RX_BUFSZ ALIGN(WX_MAX_RXBUFFER / MAX_SKB_FRAGS, 1024)
355 #else
356 #define WX_RX_BUFSZ WX_RXBUFFER_2K
357 #endif
358
359 #define WX_RX_BUFFER_WRITE 16 /* Must be power of 2 */
360
361 #define WX_MAX_DATA_PER_TXD BIT(14)
362 /* Tx Descriptors needed, worst case */
363 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), WX_MAX_DATA_PER_TXD)
364 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
365
366 #define WX_CFG_PORT_ST 0x14404
367
368 /******************* Receive Descriptor bit definitions **********************/
369 #define WX_RXD_STAT_DD BIT(0) /* Done */
370 #define WX_RXD_STAT_EOP BIT(1) /* End of Packet */
371 #define WX_RXD_STAT_VP BIT(5) /* IEEE VLAN Pkt */
372 #define WX_RXD_STAT_L4CS BIT(7) /* L4 xsum calculated */
373 #define WX_RXD_STAT_IPCS BIT(8) /* IP xsum calculated */
374 #define WX_RXD_STAT_OUTERIPCS BIT(10) /* Cloud IP xsum calculated*/
375
376 #define WX_RXD_ERR_OUTERIPER BIT(26) /* CRC IP Header error */
377 #define WX_RXD_ERR_RXE BIT(29) /* Any MAC Error */
378 #define WX_RXD_ERR_TCPE BIT(30) /* TCP/UDP Checksum Error */
379 #define WX_RXD_ERR_IPE BIT(31) /* IP Checksum Error */
380
381 /* RSS Hash results */
382 #define WX_RXD_RSSTYPE_MASK GENMASK(3, 0)
383 #define WX_RXD_RSSTYPE_IPV4_TCP 0x00000001U
384 #define WX_RXD_RSSTYPE_IPV6_TCP 0x00000003U
385 #define WX_RXD_RSSTYPE_IPV4_SCTP 0x00000004U
386 #define WX_RXD_RSSTYPE_IPV6_SCTP 0x00000006U
387 #define WX_RXD_RSSTYPE_IPV4_UDP 0x00000007U
388 #define WX_RXD_RSSTYPE_IPV6_UDP 0x00000008U
389
390 #define WX_RSS_L4_TYPES_MASK \
391 ((1ul << WX_RXD_RSSTYPE_IPV4_TCP) | \
392 (1ul << WX_RXD_RSSTYPE_IPV4_UDP) | \
393 (1ul << WX_RXD_RSSTYPE_IPV4_SCTP) | \
394 (1ul << WX_RXD_RSSTYPE_IPV6_TCP) | \
395 (1ul << WX_RXD_RSSTYPE_IPV6_UDP) | \
396 (1ul << WX_RXD_RSSTYPE_IPV6_SCTP))
397 /* TUN */
398 #define WX_PTYPE_TUN_IPV4 0x80
399 #define WX_PTYPE_TUN_IPV6 0xC0
400
401 /* PKT for TUN */
402 #define WX_PTYPE_PKT_IPIP 0x00 /* IP+IP */
403 #define WX_PTYPE_PKT_IG 0x10 /* IP+GRE */
404 #define WX_PTYPE_PKT_IGM 0x20 /* IP+GRE+MAC */
405 #define WX_PTYPE_PKT_IGMV 0x30 /* IP+GRE+MAC+VLAN */
406 /* PKT for !TUN */
407 #define WX_PTYPE_PKT_MAC 0x10
408 #define WX_PTYPE_PKT_IP 0x20
409
410 /* TYP for PKT=mac */
411 #define WX_PTYPE_TYP_MAC 0x01
412 /* TYP for PKT=ip */
413 #define WX_PTYPE_PKT_IPV6 0x08
414 #define WX_PTYPE_TYP_IPFRAG 0x01
415 #define WX_PTYPE_TYP_IP 0x02
416 #define WX_PTYPE_TYP_UDP 0x03
417 #define WX_PTYPE_TYP_TCP 0x04
418 #define WX_PTYPE_TYP_SCTP 0x05
419
420 #define WX_RXD_PKTTYPE(_rxd) \
421 ((le32_to_cpu((_rxd)->wb.lower.lo_dword.data) >> 9) & 0xFF)
422 #define WX_RXD_IPV6EX(_rxd) \
423 ((le32_to_cpu((_rxd)->wb.lower.lo_dword.data) >> 6) & 0x1)
424 /*********************** Transmit Descriptor Config Masks ****************/
425 #define WX_TXD_STAT_DD BIT(0) /* Descriptor Done */
426 #define WX_TXD_DTYP_DATA 0 /* Adv Data Descriptor */
427 #define WX_TXD_PAYLEN_SHIFT 13 /* Desc PAYLEN shift */
428 #define WX_TXD_EOP BIT(24) /* End of Packet */
429 #define WX_TXD_IFCS BIT(25) /* Insert FCS */
430 #define WX_TXD_RS BIT(27) /* Report Status */
431
432 /*********************** Adv Transmit Descriptor Config Masks ****************/
433 #define WX_TXD_MAC_TSTAMP BIT(19) /* IEEE1588 time stamp */
434 #define WX_TXD_DTYP_CTXT BIT(20) /* Adv Context Desc */
435 #define WX_TXD_LINKSEC BIT(26) /* enable linksec */
436 #define WX_TXD_VLE BIT(30) /* VLAN pkt enable */
437 #define WX_TXD_TSE BIT(31) /* TCP Seg enable */
438 #define WX_TXD_CC BIT(7) /* Check Context */
439 #define WX_TXD_IPSEC BIT(8) /* enable ipsec esp */
440 #define WX_TXD_L4CS BIT(9)
441 #define WX_TXD_IIPCS BIT(10)
442 #define WX_TXD_EIPCS BIT(11)
443 #define WX_TXD_PAYLEN_SHIFT 13 /* Adv desc PAYLEN shift */
444 #define WX_TXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
445 #define WX_TXD_TAG_TPID_SEL_SHIFT 11
446
447 #define WX_TXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
448 #define WX_TXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
449
450 #define WX_TXD_OUTER_IPLEN_SHIFT 12 /* Adv ctxt OUTERIPLEN shift */
451 #define WX_TXD_TUNNEL_LEN_SHIFT 21 /* Adv ctxt TUNNELLEN shift */
452 #define WX_TXD_TUNNEL_TYPE_SHIFT 11 /* Adv Tx Desc Tunnel Type shift */
453 #define WX_TXD_TUNNEL_UDP FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 0)
454 #define WX_TXD_TUNNEL_GRE FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 1)
455
456 enum wx_tx_flags {
457 /* cmd_type flags */
458 WX_TX_FLAGS_HW_VLAN = 0x01,
459 WX_TX_FLAGS_TSO = 0x02,
460 WX_TX_FLAGS_TSTAMP = 0x04,
461
462 /* olinfo flags */
463 WX_TX_FLAGS_CC = 0x08,
464 WX_TX_FLAGS_IPV4 = 0x10,
465 WX_TX_FLAGS_CSUM = 0x20,
466 WX_TX_FLAGS_OUTER_IPV4 = 0x100,
467 WX_TX_FLAGS_LINKSEC = 0x200,
468 WX_TX_FLAGS_IPSEC = 0x400,
469 };
470
471 /* VLAN info */
472 #define WX_TX_FLAGS_VLAN_MASK GENMASK(31, 16)
473 #define WX_TX_FLAGS_VLAN_SHIFT 16
474
475 /* wx_dec_ptype.mac: outer mac */
476 enum wx_dec_ptype_mac {
477 WX_DEC_PTYPE_MAC_IP = 0,
478 WX_DEC_PTYPE_MAC_L2 = 2,
479 WX_DEC_PTYPE_MAC_FCOE = 3,
480 };
481
482 /* wx_dec_ptype.[e]ip: outer&encaped ip */
483 #define WX_DEC_PTYPE_IP_FRAG 0x4
484 enum wx_dec_ptype_ip {
485 WX_DEC_PTYPE_IP_NONE = 0,
486 WX_DEC_PTYPE_IP_IPV4 = 1,
487 WX_DEC_PTYPE_IP_IPV6 = 2,
488 WX_DEC_PTYPE_IP_FGV4 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV4,
489 WX_DEC_PTYPE_IP_FGV6 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV6,
490 };
491
492 /* wx_dec_ptype.etype: encaped type */
493 enum wx_dec_ptype_etype {
494 WX_DEC_PTYPE_ETYPE_NONE = 0,
495 WX_DEC_PTYPE_ETYPE_IPIP = 1, /* IP+IP */
496 WX_DEC_PTYPE_ETYPE_IG = 2, /* IP+GRE */
497 WX_DEC_PTYPE_ETYPE_IGM = 3, /* IP+GRE+MAC */
498 WX_DEC_PTYPE_ETYPE_IGMV = 4, /* IP+GRE+MAC+VLAN */
499 };
500
501 /* wx_dec_ptype.proto: payload proto */
502 enum wx_dec_ptype_prot {
503 WX_DEC_PTYPE_PROT_NONE = 0,
504 WX_DEC_PTYPE_PROT_UDP = 1,
505 WX_DEC_PTYPE_PROT_TCP = 2,
506 WX_DEC_PTYPE_PROT_SCTP = 3,
507 WX_DEC_PTYPE_PROT_ICMP = 4,
508 WX_DEC_PTYPE_PROT_TS = 5, /* time sync */
509 };
510
511 /* wx_dec_ptype.layer: payload layer */
512 enum wx_dec_ptype_layer {
513 WX_DEC_PTYPE_LAYER_NONE = 0,
514 WX_DEC_PTYPE_LAYER_PAY2 = 1,
515 WX_DEC_PTYPE_LAYER_PAY3 = 2,
516 WX_DEC_PTYPE_LAYER_PAY4 = 3,
517 };
518
519 struct wx_dec_ptype {
520 u32 known:1;
521 u32 mac:2; /* outer mac */
522 u32 ip:3; /* outer ip*/
523 u32 etype:3; /* encaped type */
524 u32 eip:3; /* encaped ip */
525 u32 prot:4; /* payload proto */
526 u32 layer:3; /* payload layer */
527 };
528
529 /* macro to make the table lines short */
530 #define WX_PTT(mac, ip, etype, eip, proto, layer)\
531 {1, \
532 WX_DEC_PTYPE_MAC_##mac, /* mac */\
533 WX_DEC_PTYPE_IP_##ip, /* ip */ \
534 WX_DEC_PTYPE_ETYPE_##etype, /* etype */\
535 WX_DEC_PTYPE_IP_##eip, /* eip */\
536 WX_DEC_PTYPE_PROT_##proto, /* proto */\
537 WX_DEC_PTYPE_LAYER_##layer /* layer */}
538
539 /* Host Interface Command Structures */
540 struct wx_hic_hdr {
541 u8 cmd;
542 u8 buf_len;
543 union {
544 u8 cmd_resv;
545 u8 ret_status;
546 } cmd_or_resp;
547 u8 checksum;
548 };
549
550 struct wx_hic_hdr2_req {
551 u8 cmd;
552 u8 buf_lenh;
553 u8 buf_lenl;
554 u8 checksum;
555 };
556
557 struct wx_hic_hdr2_rsp {
558 u8 cmd;
559 u8 buf_lenl;
560 u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */
561 u8 checksum;
562 };
563
564 union wx_hic_hdr2 {
565 struct wx_hic_hdr2_req req;
566 struct wx_hic_hdr2_rsp rsp;
567 };
568
569 /* These need to be dword aligned */
570 struct wx_hic_read_shadow_ram {
571 union wx_hic_hdr2 hdr;
572 u32 address;
573 u16 length;
574 u16 pad2;
575 u16 data;
576 u16 pad3;
577 };
578
579 struct wx_hic_reset {
580 struct wx_hic_hdr hdr;
581 u16 lan_id;
582 u16 reset_type;
583 };
584
585 /* Bus parameters */
586 struct wx_bus_info {
587 u8 func;
588 u16 device;
589 };
590
591 struct wx_thermal_sensor_data {
592 s16 temp;
593 s16 alarm_thresh;
594 s16 dalarm_thresh;
595 };
596
597 enum wx_mac_type {
598 wx_mac_unknown = 0,
599 wx_mac_sp,
600 wx_mac_em
601 };
602
603 enum sp_media_type {
604 sp_media_unknown = 0,
605 sp_media_fiber,
606 sp_media_copper,
607 sp_media_backplane
608 };
609
610 enum em_mac_type {
611 em_mac_type_unknown = 0,
612 em_mac_type_mdi,
613 em_mac_type_rgmii
614 };
615
616 struct wx_mac_info {
617 enum wx_mac_type type;
618 bool set_lben;
619 u8 addr[ETH_ALEN];
620 u8 perm_addr[ETH_ALEN];
621 u32 mta_shadow[128];
622 s32 mc_filter_type;
623 u32 mcft_size;
624 u32 vft_shadow[128];
625 u32 vft_size;
626 u32 num_rar_entries;
627 u32 rx_pb_size;
628 u32 tx_pb_size;
629 u32 max_tx_queues;
630 u32 max_rx_queues;
631
632 u16 max_msix_vectors;
633 struct wx_thermal_sensor_data sensor;
634 };
635
636 enum wx_eeprom_type {
637 wx_eeprom_uninitialized = 0,
638 wx_eeprom_spi,
639 wx_flash,
640 wx_eeprom_none /* No NVM support */
641 };
642
643 struct wx_eeprom_info {
644 enum wx_eeprom_type type;
645 u32 semaphore_delay;
646 u16 word_size;
647 u16 sw_region_offset;
648 };
649
650 struct wx_addr_filter_info {
651 u32 num_mc_addrs;
652 u32 mta_in_use;
653 bool user_set_promisc;
654 };
655
656 struct wx_mac_addr {
657 u8 addr[ETH_ALEN];
658 u16 state; /* bitmask */
659 u64 pools;
660 };
661
662 enum wx_reset_type {
663 WX_LAN_RESET = 0,
664 WX_SW_RESET,
665 WX_GLOBAL_RESET
666 };
667
668 struct wx_cb {
669 dma_addr_t dma;
670 u16 append_cnt; /* number of skb's appended */
671 bool page_released;
672 bool dma_released;
673 };
674
675 #define WX_CB(skb) ((struct wx_cb *)(skb)->cb)
676
677 /* Transmit Descriptor */
678 union wx_tx_desc {
679 struct {
680 __le64 buffer_addr; /* Address of descriptor's data buf */
681 __le32 cmd_type_len;
682 __le32 olinfo_status;
683 } read;
684 struct {
685 __le64 rsvd; /* Reserved */
686 __le32 nxtseq_seed;
687 __le32 status;
688 } wb;
689 };
690
691 /* Receive Descriptor */
692 union wx_rx_desc {
693 struct {
694 __le64 pkt_addr; /* Packet buffer address */
695 __le64 hdr_addr; /* Header buffer address */
696 } read;
697 struct {
698 struct {
699 union {
700 __le32 data;
701 struct {
702 __le16 pkt_info; /* RSS, Pkt type */
703 __le16 hdr_info; /* Splithdr, hdrlen */
704 } hs_rss;
705 } lo_dword;
706 union {
707 __le32 rss; /* RSS Hash */
708 struct {
709 __le16 ip_id; /* IP id */
710 __le16 csum; /* Packet Checksum */
711 } csum_ip;
712 } hi_dword;
713 } lower;
714 struct {
715 __le32 status_error; /* ext status/error */
716 __le16 length; /* Packet length */
717 __le16 vlan; /* VLAN tag */
718 } upper;
719 } wb; /* writeback */
720 };
721
722 struct wx_tx_context_desc {
723 __le32 vlan_macip_lens;
724 __le32 seqnum_seed;
725 __le32 type_tucmd_mlhl;
726 __le32 mss_l4len_idx;
727 };
728
729 /* if _flag is in _input, return _result */
730 #define WX_SET_FLAG(_input, _flag, _result) \
731 (((_flag) <= (_result)) ? \
732 ((u32)((_input) & (_flag)) * ((_result) / (_flag))) : \
733 ((u32)((_input) & (_flag)) / ((_flag) / (_result))))
734
735 #define WX_RX_DESC(R, i) \
736 (&(((union wx_rx_desc *)((R)->desc))[i]))
737 #define WX_TX_DESC(R, i) \
738 (&(((union wx_tx_desc *)((R)->desc))[i]))
739 #define WX_TX_CTXTDESC(R, i) \
740 (&(((struct wx_tx_context_desc *)((R)->desc))[i]))
741
742 /* wrapper around a pointer to a socket buffer,
743 * so a DMA handle can be stored along with the buffer
744 */
745 struct wx_tx_buffer {
746 union wx_tx_desc *next_to_watch;
747 struct sk_buff *skb;
748 unsigned int bytecount;
749 unsigned short gso_segs;
750 DEFINE_DMA_UNMAP_ADDR(dma);
751 DEFINE_DMA_UNMAP_LEN(len);
752 __be16 protocol;
753 u32 tx_flags;
754 };
755
756 struct wx_rx_buffer {
757 struct sk_buff *skb;
758 dma_addr_t dma;
759 dma_addr_t page_dma;
760 struct page *page;
761 unsigned int page_offset;
762 };
763
764 struct wx_queue_stats {
765 u64 packets;
766 u64 bytes;
767 };
768
769 struct wx_rx_queue_stats {
770 u64 csum_good_cnt;
771 u64 csum_err;
772 };
773
774 /* iterator for handling rings in ring container */
775 #define wx_for_each_ring(posm, headm) \
776 for (posm = (headm).ring; posm; posm = posm->next)
777
778 struct wx_ring_container {
779 struct wx_ring *ring; /* pointer to linked list of rings */
780 unsigned int total_bytes; /* total bytes processed this int */
781 unsigned int total_packets; /* total packets processed this int */
782 u8 count; /* total number of rings in vector */
783 u8 itr; /* current ITR setting for ring */
784 };
785 struct wx_ring {
786 struct wx_ring *next; /* pointer to next ring in q_vector */
787 struct wx_q_vector *q_vector; /* backpointer to host q_vector */
788 struct net_device *netdev; /* netdev ring belongs to */
789 struct device *dev; /* device for DMA mapping */
790 struct page_pool *page_pool;
791 void *desc; /* descriptor ring memory */
792 union {
793 struct wx_tx_buffer *tx_buffer_info;
794 struct wx_rx_buffer *rx_buffer_info;
795 };
796 u8 __iomem *tail;
797 dma_addr_t dma; /* phys. address of descriptor ring */
798 unsigned int size; /* length in bytes */
799
800 u16 count; /* amount of descriptors */
801
802 u8 queue_index; /* needed for multiqueue queue management */
803 u8 reg_idx; /* holds the special value that gets
804 * the hardware register offset
805 * associated with this ring, which is
806 * different for DCB and RSS modes
807 */
808 u16 next_to_use;
809 u16 next_to_clean;
810 u16 next_to_alloc;
811
812 struct wx_queue_stats stats;
813 struct u64_stats_sync syncp;
814 union {
815 struct wx_rx_queue_stats rx_stats;
816 };
817 } ____cacheline_internodealigned_in_smp;
818
819 struct wx_q_vector {
820 struct wx *wx;
821 int cpu; /* CPU for DCA */
822 int numa_node;
823 u16 v_idx; /* index of q_vector within array, also used for
824 * finding the bit in EICR and friends that
825 * represents the vector for this ring
826 */
827 u16 itr; /* Interrupt throttle rate written to EITR */
828 struct wx_ring_container rx, tx;
829 struct napi_struct napi;
830 struct rcu_head rcu; /* to avoid race with update stats on free */
831
832 char name[IFNAMSIZ + 17];
833
834 /* for dynamic allocation of rings associated with this q_vector */
835 struct wx_ring ring[] ____cacheline_internodealigned_in_smp;
836 };
837
838 enum wx_isb_idx {
839 WX_ISB_HEADER,
840 WX_ISB_MISC,
841 WX_ISB_VEC0,
842 WX_ISB_VEC1,
843 WX_ISB_MAX
844 };
845
846 struct wx {
847 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
848
849 void *priv;
850 u8 __iomem *hw_addr;
851 struct pci_dev *pdev;
852 struct net_device *netdev;
853 struct wx_bus_info bus;
854 struct wx_mac_info mac;
855 enum em_mac_type mac_type;
856 enum sp_media_type media_type;
857 struct wx_eeprom_info eeprom;
858 struct wx_addr_filter_info addr_ctrl;
859 struct wx_mac_addr *mac_table;
860 u16 device_id;
861 u16 vendor_id;
862 u16 subsystem_device_id;
863 u16 subsystem_vendor_id;
864 u8 revision_id;
865 u16 oem_ssid;
866 u16 oem_svid;
867 u16 msg_enable;
868 bool adapter_stopped;
869 u16 tpid[8];
870 char eeprom_id[32];
871 char *driver_name;
872 enum wx_reset_type reset_type;
873
874 /* PHY stuff */
875 unsigned int link;
876 int speed;
877 int duplex;
878 struct phy_device *phydev;
879
880 bool wol_hw_supported;
881 bool ncsi_enabled;
882 bool gpio_ctrl;
883 raw_spinlock_t gpio_lock;
884
885 /* Tx fast path data */
886 int num_tx_queues;
887 u16 tx_itr_setting;
888 u16 tx_work_limit;
889
890 /* Rx fast path data */
891 int num_rx_queues;
892 u16 rx_itr_setting;
893 u16 rx_work_limit;
894
895 int num_q_vectors; /* current number of q_vectors for device */
896 int max_q_vectors; /* upper limit of q_vectors for device */
897
898 u32 tx_ring_count;
899 u32 rx_ring_count;
900
901 struct wx_ring *tx_ring[64] ____cacheline_aligned_in_smp;
902 struct wx_ring *rx_ring[64];
903 struct wx_q_vector *q_vector[64];
904
905 unsigned int queues_per_pool;
906 struct msix_entry *msix_entries;
907
908 /* misc interrupt status block */
909 dma_addr_t isb_dma;
910 u32 *isb_mem;
911 u32 isb_tag[WX_ISB_MAX];
912
913 #define WX_MAX_RETA_ENTRIES 128
914 u8 rss_indir_tbl[WX_MAX_RETA_ENTRIES];
915
916 #define WX_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */
917 u32 *rss_key;
918 u32 wol;
919
920 u16 bd_number;
921 };
922
923 #define WX_INTR_ALL (~0ULL)
924 #define WX_INTR_Q(i) BIT(i)
925
926 /* register operations */
927 #define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
928 #define rd32(a, reg) readl((a)->hw_addr + (reg))
929 #define rd32a(a, reg, offset) ( \
930 rd32((a), (reg) + ((offset) << 2)))
931 #define wr32a(a, reg, off, val) \
932 wr32((a), (reg) + ((off) << 2), (val))
933
934 static inline u32
rd32m(struct wx * wx,u32 reg,u32 mask)935 rd32m(struct wx *wx, u32 reg, u32 mask)
936 {
937 u32 val;
938
939 val = rd32(wx, reg);
940 return val & mask;
941 }
942
943 static inline void
wr32m(struct wx * wx,u32 reg,u32 mask,u32 field)944 wr32m(struct wx *wx, u32 reg, u32 mask, u32 field)
945 {
946 u32 val;
947
948 val = rd32(wx, reg);
949 val = ((val & ~mask) | (field & mask));
950
951 wr32(wx, reg, val);
952 }
953
954 /* On some domestic CPU platforms, sometimes IO is not synchronized with
955 * flushing memory, here use readl() to flush PCI read and write.
956 */
957 #define WX_WRITE_FLUSH(H) rd32(H, WX_MIS_PWR)
958
959 #define wx_err(wx, fmt, arg...) \
960 dev_err(&(wx)->pdev->dev, fmt, ##arg)
961
962 #define wx_dbg(wx, fmt, arg...) \
963 dev_dbg(&(wx)->pdev->dev, fmt, ##arg)
964
965 #endif /* _WX_TYPE_H_ */
966