1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <crypto/hash.h>
8 #include "core.h"
9 #include "dp_tx.h"
10 #include "hal_tx.h"
11 #include "hif.h"
12 #include "debug.h"
13 #include "dp_rx.h"
14 #include "peer.h"
15 #include "dp_mon.h"
16
ath12k_dp_htt_htc_tx_complete(struct ath12k_base * ab,struct sk_buff * skb)17 static void ath12k_dp_htt_htc_tx_complete(struct ath12k_base *ab,
18 struct sk_buff *skb)
19 {
20 dev_kfree_skb_any(skb);
21 }
22
ath12k_dp_peer_cleanup(struct ath12k * ar,int vdev_id,const u8 * addr)23 void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr)
24 {
25 struct ath12k_base *ab = ar->ab;
26 struct ath12k_peer *peer;
27
28 /* TODO: Any other peer specific DP cleanup */
29
30 spin_lock_bh(&ab->base_lock);
31 peer = ath12k_peer_find(ab, vdev_id, addr);
32 if (!peer) {
33 ath12k_warn(ab, "failed to lookup peer %pM on vdev %d\n",
34 addr, vdev_id);
35 spin_unlock_bh(&ab->base_lock);
36 return;
37 }
38
39 ath12k_dp_rx_peer_tid_cleanup(ar, peer);
40 crypto_free_shash(peer->tfm_mmic);
41 peer->dp_setup_done = false;
42 spin_unlock_bh(&ab->base_lock);
43 }
44
ath12k_dp_peer_setup(struct ath12k * ar,int vdev_id,const u8 * addr)45 int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr)
46 {
47 struct ath12k_base *ab = ar->ab;
48 struct ath12k_peer *peer;
49 u32 reo_dest;
50 int ret = 0, tid;
51
52 /* NOTE: reo_dest ring id starts from 1 unlike mac_id which starts from 0 */
53 reo_dest = ar->dp.mac_id + 1;
54 ret = ath12k_wmi_set_peer_param(ar, addr, vdev_id,
55 WMI_PEER_SET_DEFAULT_ROUTING,
56 DP_RX_HASH_ENABLE | (reo_dest << 1));
57
58 if (ret) {
59 ath12k_warn(ab, "failed to set default routing %d peer :%pM vdev_id :%d\n",
60 ret, addr, vdev_id);
61 return ret;
62 }
63
64 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
65 ret = ath12k_dp_rx_peer_tid_setup(ar, addr, vdev_id, tid, 1, 0,
66 HAL_PN_TYPE_NONE);
67 if (ret) {
68 ath12k_warn(ab, "failed to setup rxd tid queue for tid %d: %d\n",
69 tid, ret);
70 goto peer_clean;
71 }
72 }
73
74 ret = ath12k_dp_rx_peer_frag_setup(ar, addr, vdev_id);
75 if (ret) {
76 ath12k_warn(ab, "failed to setup rx defrag context\n");
77 goto peer_clean;
78 }
79
80 /* TODO: Setup other peer specific resource used in data path */
81
82 return 0;
83
84 peer_clean:
85 spin_lock_bh(&ab->base_lock);
86
87 peer = ath12k_peer_find(ab, vdev_id, addr);
88 if (!peer) {
89 ath12k_warn(ab, "failed to find the peer to del rx tid\n");
90 spin_unlock_bh(&ab->base_lock);
91 return -ENOENT;
92 }
93
94 for (; tid >= 0; tid--)
95 ath12k_dp_rx_peer_tid_delete(ar, peer, tid);
96
97 spin_unlock_bh(&ab->base_lock);
98
99 return ret;
100 }
101
ath12k_dp_srng_cleanup(struct ath12k_base * ab,struct dp_srng * ring)102 void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring)
103 {
104 if (!ring->vaddr_unaligned)
105 return;
106
107 dma_free_coherent(ab->dev, ring->size, ring->vaddr_unaligned,
108 ring->paddr_unaligned);
109
110 ring->vaddr_unaligned = NULL;
111 }
112
ath12k_dp_srng_find_ring_in_mask(int ring_num,const u8 * grp_mask)113 static int ath12k_dp_srng_find_ring_in_mask(int ring_num, const u8 *grp_mask)
114 {
115 int ext_group_num;
116 u8 mask = 1 << ring_num;
117
118 for (ext_group_num = 0; ext_group_num < ATH12K_EXT_IRQ_GRP_NUM_MAX;
119 ext_group_num++) {
120 if (mask & grp_mask[ext_group_num])
121 return ext_group_num;
122 }
123
124 return -ENOENT;
125 }
126
ath12k_dp_srng_calculate_msi_group(struct ath12k_base * ab,enum hal_ring_type type,int ring_num)127 static int ath12k_dp_srng_calculate_msi_group(struct ath12k_base *ab,
128 enum hal_ring_type type, int ring_num)
129 {
130 const struct ath12k_hal_tcl_to_wbm_rbm_map *map;
131 const u8 *grp_mask;
132 int i;
133
134 switch (type) {
135 case HAL_WBM2SW_RELEASE:
136 if (ring_num == HAL_WBM2SW_REL_ERR_RING_NUM) {
137 grp_mask = &ab->hw_params->ring_mask->rx_wbm_rel[0];
138 ring_num = 0;
139 } else {
140 map = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map;
141 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
142 if (ring_num == map[i].wbm_ring_num) {
143 ring_num = i;
144 break;
145 }
146 }
147
148 grp_mask = &ab->hw_params->ring_mask->tx[0];
149 }
150 break;
151 case HAL_REO_EXCEPTION:
152 grp_mask = &ab->hw_params->ring_mask->rx_err[0];
153 break;
154 case HAL_REO_DST:
155 grp_mask = &ab->hw_params->ring_mask->rx[0];
156 break;
157 case HAL_REO_STATUS:
158 grp_mask = &ab->hw_params->ring_mask->reo_status[0];
159 break;
160 case HAL_RXDMA_MONITOR_STATUS:
161 case HAL_RXDMA_MONITOR_DST:
162 grp_mask = &ab->hw_params->ring_mask->rx_mon_dest[0];
163 break;
164 case HAL_TX_MONITOR_DST:
165 grp_mask = &ab->hw_params->ring_mask->tx_mon_dest[0];
166 break;
167 case HAL_RXDMA_BUF:
168 grp_mask = &ab->hw_params->ring_mask->host2rxdma[0];
169 break;
170 case HAL_RXDMA_MONITOR_BUF:
171 case HAL_TCL_DATA:
172 case HAL_TCL_CMD:
173 case HAL_REO_CMD:
174 case HAL_SW2WBM_RELEASE:
175 case HAL_WBM_IDLE_LINK:
176 case HAL_TCL_STATUS:
177 case HAL_REO_REINJECT:
178 case HAL_CE_SRC:
179 case HAL_CE_DST:
180 case HAL_CE_DST_STATUS:
181 default:
182 return -ENOENT;
183 }
184
185 return ath12k_dp_srng_find_ring_in_mask(ring_num, grp_mask);
186 }
187
ath12k_dp_srng_msi_setup(struct ath12k_base * ab,struct hal_srng_params * ring_params,enum hal_ring_type type,int ring_num)188 static void ath12k_dp_srng_msi_setup(struct ath12k_base *ab,
189 struct hal_srng_params *ring_params,
190 enum hal_ring_type type, int ring_num)
191 {
192 int msi_group_number, msi_data_count;
193 u32 msi_data_start, msi_irq_start, addr_lo, addr_hi;
194 int ret;
195
196 ret = ath12k_hif_get_user_msi_vector(ab, "DP",
197 &msi_data_count, &msi_data_start,
198 &msi_irq_start);
199 if (ret)
200 return;
201
202 msi_group_number = ath12k_dp_srng_calculate_msi_group(ab, type,
203 ring_num);
204 if (msi_group_number < 0) {
205 ath12k_dbg(ab, ATH12K_DBG_PCI,
206 "ring not part of an ext_group; ring_type: %d,ring_num %d",
207 type, ring_num);
208 ring_params->msi_addr = 0;
209 ring_params->msi_data = 0;
210 return;
211 }
212
213 if (msi_group_number > msi_data_count) {
214 ath12k_dbg(ab, ATH12K_DBG_PCI,
215 "multiple msi_groups share one msi, msi_group_num %d",
216 msi_group_number);
217 }
218
219 ath12k_hif_get_msi_address(ab, &addr_lo, &addr_hi);
220
221 ring_params->msi_addr = addr_lo;
222 ring_params->msi_addr |= (dma_addr_t)(((uint64_t)addr_hi) << 32);
223 ring_params->msi_data = (msi_group_number % msi_data_count)
224 + msi_data_start;
225 ring_params->flags |= HAL_SRNG_FLAGS_MSI_INTR;
226 }
227
ath12k_dp_srng_setup(struct ath12k_base * ab,struct dp_srng * ring,enum hal_ring_type type,int ring_num,int mac_id,int num_entries)228 int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring,
229 enum hal_ring_type type, int ring_num,
230 int mac_id, int num_entries)
231 {
232 struct hal_srng_params params = { 0 };
233 int entry_sz = ath12k_hal_srng_get_entrysize(ab, type);
234 int max_entries = ath12k_hal_srng_get_max_entries(ab, type);
235 int ret;
236
237 if (max_entries < 0 || entry_sz < 0)
238 return -EINVAL;
239
240 if (num_entries > max_entries)
241 num_entries = max_entries;
242
243 ring->size = (num_entries * entry_sz) + HAL_RING_BASE_ALIGN - 1;
244 ring->vaddr_unaligned = dma_alloc_coherent(ab->dev, ring->size,
245 &ring->paddr_unaligned,
246 GFP_KERNEL);
247 if (!ring->vaddr_unaligned)
248 return -ENOMEM;
249
250 ring->vaddr = PTR_ALIGN(ring->vaddr_unaligned, HAL_RING_BASE_ALIGN);
251 ring->paddr = ring->paddr_unaligned + ((unsigned long)ring->vaddr -
252 (unsigned long)ring->vaddr_unaligned);
253
254 params.ring_base_vaddr = ring->vaddr;
255 params.ring_base_paddr = ring->paddr;
256 params.num_entries = num_entries;
257 ath12k_dp_srng_msi_setup(ab, ¶ms, type, ring_num + mac_id);
258
259 switch (type) {
260 case HAL_REO_DST:
261 params.intr_batch_cntr_thres_entries =
262 HAL_SRNG_INT_BATCH_THRESHOLD_RX;
263 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX;
264 break;
265 case HAL_RXDMA_BUF:
266 case HAL_RXDMA_MONITOR_BUF:
267 case HAL_RXDMA_MONITOR_STATUS:
268 params.low_threshold = num_entries >> 3;
269 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN;
270 params.intr_batch_cntr_thres_entries = 0;
271 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX;
272 break;
273 case HAL_TX_MONITOR_DST:
274 params.low_threshold = DP_TX_MONITOR_BUF_SIZE_MAX >> 3;
275 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN;
276 params.intr_batch_cntr_thres_entries = 0;
277 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX;
278 break;
279 case HAL_WBM2SW_RELEASE:
280 if (ab->hw_params->hw_ops->dp_srng_is_tx_comp_ring(ring_num)) {
281 params.intr_batch_cntr_thres_entries =
282 HAL_SRNG_INT_BATCH_THRESHOLD_TX;
283 params.intr_timer_thres_us =
284 HAL_SRNG_INT_TIMER_THRESHOLD_TX;
285 break;
286 }
287 /* follow through when ring_num != HAL_WBM2SW_REL_ERR_RING_NUM */
288 fallthrough;
289 case HAL_REO_EXCEPTION:
290 case HAL_REO_REINJECT:
291 case HAL_REO_CMD:
292 case HAL_REO_STATUS:
293 case HAL_TCL_DATA:
294 case HAL_TCL_CMD:
295 case HAL_TCL_STATUS:
296 case HAL_WBM_IDLE_LINK:
297 case HAL_SW2WBM_RELEASE:
298 case HAL_RXDMA_DST:
299 case HAL_RXDMA_MONITOR_DST:
300 case HAL_RXDMA_MONITOR_DESC:
301 params.intr_batch_cntr_thres_entries =
302 HAL_SRNG_INT_BATCH_THRESHOLD_OTHER;
303 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_OTHER;
304 break;
305 case HAL_RXDMA_DIR_BUF:
306 break;
307 default:
308 ath12k_warn(ab, "Not a valid ring type in dp :%d\n", type);
309 return -EINVAL;
310 }
311
312 ret = ath12k_hal_srng_setup(ab, type, ring_num, mac_id, ¶ms);
313 if (ret < 0) {
314 ath12k_warn(ab, "failed to setup srng: %d ring_id %d\n",
315 ret, ring_num);
316 return ret;
317 }
318
319 ring->ring_id = ret;
320
321 return 0;
322 }
323
324 static
ath12k_dp_tx_get_vdev_bank_config(struct ath12k_base * ab,struct ath12k_vif * arvif)325 u32 ath12k_dp_tx_get_vdev_bank_config(struct ath12k_base *ab, struct ath12k_vif *arvif)
326 {
327 u32 bank_config = 0;
328
329 /* Only valid for raw frames with HW crypto enabled.
330 * With SW crypto, mac80211 sets key per packet
331 */
332 if (arvif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW &&
333 test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags))
334 bank_config |=
335 u32_encode_bits(ath12k_dp_tx_get_encrypt_type(arvif->key_cipher),
336 HAL_TX_BANK_CONFIG_ENCRYPT_TYPE);
337
338 bank_config |= u32_encode_bits(arvif->tx_encap_type,
339 HAL_TX_BANK_CONFIG_ENCAP_TYPE);
340 bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_SRC_BUFFER_SWAP) |
341 u32_encode_bits(0, HAL_TX_BANK_CONFIG_LINK_META_SWAP) |
342 u32_encode_bits(0, HAL_TX_BANK_CONFIG_EPD);
343
344 /* only valid if idx_lookup_override is not set in tcl_data_cmd */
345 bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_INDEX_LOOKUP_EN);
346
347 bank_config |= u32_encode_bits(arvif->hal_addr_search_flags & HAL_TX_ADDRX_EN,
348 HAL_TX_BANK_CONFIG_ADDRX_EN) |
349 u32_encode_bits(!!(arvif->hal_addr_search_flags &
350 HAL_TX_ADDRY_EN),
351 HAL_TX_BANK_CONFIG_ADDRY_EN);
352
353 bank_config |= u32_encode_bits(ieee80211_vif_is_mesh(arvif->vif) ? 3 : 0,
354 HAL_TX_BANK_CONFIG_MESH_EN) |
355 u32_encode_bits(arvif->vdev_id_check_en,
356 HAL_TX_BANK_CONFIG_VDEV_ID_CHECK_EN);
357
358 bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_DSCP_TIP_MAP_ID);
359
360 return bank_config;
361 }
362
ath12k_dp_tx_get_bank_profile(struct ath12k_base * ab,struct ath12k_vif * arvif,struct ath12k_dp * dp)363 static int ath12k_dp_tx_get_bank_profile(struct ath12k_base *ab, struct ath12k_vif *arvif,
364 struct ath12k_dp *dp)
365 {
366 int bank_id = DP_INVALID_BANK_ID;
367 int i;
368 u32 bank_config;
369 bool configure_register = false;
370
371 /* convert vdev params into hal_tx_bank_config */
372 bank_config = ath12k_dp_tx_get_vdev_bank_config(ab, arvif);
373
374 spin_lock_bh(&dp->tx_bank_lock);
375 /* TODO: implement using idr kernel framework*/
376 for (i = 0; i < dp->num_bank_profiles; i++) {
377 if (dp->bank_profiles[i].is_configured &&
378 (dp->bank_profiles[i].bank_config ^ bank_config) == 0) {
379 bank_id = i;
380 goto inc_ref_and_return;
381 }
382 if (!dp->bank_profiles[i].is_configured ||
383 !dp->bank_profiles[i].num_users) {
384 bank_id = i;
385 goto configure_and_return;
386 }
387 }
388
389 if (bank_id == DP_INVALID_BANK_ID) {
390 spin_unlock_bh(&dp->tx_bank_lock);
391 ath12k_err(ab, "unable to find TX bank!");
392 return bank_id;
393 }
394
395 configure_and_return:
396 dp->bank_profiles[bank_id].is_configured = true;
397 dp->bank_profiles[bank_id].bank_config = bank_config;
398 configure_register = true;
399 inc_ref_and_return:
400 dp->bank_profiles[bank_id].num_users++;
401 spin_unlock_bh(&dp->tx_bank_lock);
402
403 if (configure_register)
404 ath12k_hal_tx_configure_bank_register(ab, bank_config, bank_id);
405
406 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt tcl bank_id %d input 0x%x match 0x%x num_users %u",
407 bank_id, bank_config, dp->bank_profiles[bank_id].bank_config,
408 dp->bank_profiles[bank_id].num_users);
409
410 return bank_id;
411 }
412
ath12k_dp_tx_put_bank_profile(struct ath12k_dp * dp,u8 bank_id)413 void ath12k_dp_tx_put_bank_profile(struct ath12k_dp *dp, u8 bank_id)
414 {
415 spin_lock_bh(&dp->tx_bank_lock);
416 dp->bank_profiles[bank_id].num_users--;
417 spin_unlock_bh(&dp->tx_bank_lock);
418 }
419
ath12k_dp_deinit_bank_profiles(struct ath12k_base * ab)420 static void ath12k_dp_deinit_bank_profiles(struct ath12k_base *ab)
421 {
422 struct ath12k_dp *dp = &ab->dp;
423
424 kfree(dp->bank_profiles);
425 dp->bank_profiles = NULL;
426 }
427
ath12k_dp_init_bank_profiles(struct ath12k_base * ab)428 static int ath12k_dp_init_bank_profiles(struct ath12k_base *ab)
429 {
430 struct ath12k_dp *dp = &ab->dp;
431 u32 num_tcl_banks = ab->hw_params->num_tcl_banks;
432 int i;
433
434 dp->num_bank_profiles = num_tcl_banks;
435 dp->bank_profiles = kmalloc_array(num_tcl_banks,
436 sizeof(struct ath12k_dp_tx_bank_profile),
437 GFP_KERNEL);
438 if (!dp->bank_profiles)
439 return -ENOMEM;
440
441 spin_lock_init(&dp->tx_bank_lock);
442
443 for (i = 0; i < num_tcl_banks; i++) {
444 dp->bank_profiles[i].is_configured = false;
445 dp->bank_profiles[i].num_users = 0;
446 }
447
448 return 0;
449 }
450
ath12k_dp_srng_common_cleanup(struct ath12k_base * ab)451 static void ath12k_dp_srng_common_cleanup(struct ath12k_base *ab)
452 {
453 struct ath12k_dp *dp = &ab->dp;
454 int i;
455
456 ath12k_dp_srng_cleanup(ab, &dp->reo_status_ring);
457 ath12k_dp_srng_cleanup(ab, &dp->reo_cmd_ring);
458 ath12k_dp_srng_cleanup(ab, &dp->reo_except_ring);
459 ath12k_dp_srng_cleanup(ab, &dp->rx_rel_ring);
460 ath12k_dp_srng_cleanup(ab, &dp->reo_reinject_ring);
461 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
462 ath12k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_comp_ring);
463 ath12k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_data_ring);
464 }
465 ath12k_dp_srng_cleanup(ab, &dp->tcl_status_ring);
466 ath12k_dp_srng_cleanup(ab, &dp->tcl_cmd_ring);
467 ath12k_dp_srng_cleanup(ab, &dp->wbm_desc_rel_ring);
468 }
469
ath12k_dp_srng_common_setup(struct ath12k_base * ab)470 static int ath12k_dp_srng_common_setup(struct ath12k_base *ab)
471 {
472 struct ath12k_dp *dp = &ab->dp;
473 const struct ath12k_hal_tcl_to_wbm_rbm_map *map;
474 struct hal_srng *srng;
475 int i, ret, tx_comp_ring_num;
476 u32 ring_hash_map;
477
478 ret = ath12k_dp_srng_setup(ab, &dp->wbm_desc_rel_ring,
479 HAL_SW2WBM_RELEASE, 0, 0,
480 DP_WBM_RELEASE_RING_SIZE);
481 if (ret) {
482 ath12k_warn(ab, "failed to set up wbm2sw_release ring :%d\n",
483 ret);
484 goto err;
485 }
486
487 ret = ath12k_dp_srng_setup(ab, &dp->tcl_cmd_ring, HAL_TCL_CMD, 0, 0,
488 DP_TCL_CMD_RING_SIZE);
489 if (ret) {
490 ath12k_warn(ab, "failed to set up tcl_cmd ring :%d\n", ret);
491 goto err;
492 }
493
494 ret = ath12k_dp_srng_setup(ab, &dp->tcl_status_ring, HAL_TCL_STATUS,
495 0, 0, DP_TCL_STATUS_RING_SIZE);
496 if (ret) {
497 ath12k_warn(ab, "failed to set up tcl_status ring :%d\n", ret);
498 goto err;
499 }
500
501 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
502 map = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map;
503 tx_comp_ring_num = map[i].wbm_ring_num;
504
505 ret = ath12k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_data_ring,
506 HAL_TCL_DATA, i, 0,
507 DP_TCL_DATA_RING_SIZE);
508 if (ret) {
509 ath12k_warn(ab, "failed to set up tcl_data ring (%d) :%d\n",
510 i, ret);
511 goto err;
512 }
513
514 ret = ath12k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_comp_ring,
515 HAL_WBM2SW_RELEASE, tx_comp_ring_num, 0,
516 DP_TX_COMP_RING_SIZE);
517 if (ret) {
518 ath12k_warn(ab, "failed to set up tcl_comp ring (%d) :%d\n",
519 tx_comp_ring_num, ret);
520 goto err;
521 }
522 }
523
524 ret = ath12k_dp_srng_setup(ab, &dp->reo_reinject_ring, HAL_REO_REINJECT,
525 0, 0, DP_REO_REINJECT_RING_SIZE);
526 if (ret) {
527 ath12k_warn(ab, "failed to set up reo_reinject ring :%d\n",
528 ret);
529 goto err;
530 }
531
532 ret = ath12k_dp_srng_setup(ab, &dp->rx_rel_ring, HAL_WBM2SW_RELEASE,
533 HAL_WBM2SW_REL_ERR_RING_NUM, 0,
534 DP_RX_RELEASE_RING_SIZE);
535 if (ret) {
536 ath12k_warn(ab, "failed to set up rx_rel ring :%d\n", ret);
537 goto err;
538 }
539
540 ret = ath12k_dp_srng_setup(ab, &dp->reo_except_ring, HAL_REO_EXCEPTION,
541 0, 0, DP_REO_EXCEPTION_RING_SIZE);
542 if (ret) {
543 ath12k_warn(ab, "failed to set up reo_exception ring :%d\n",
544 ret);
545 goto err;
546 }
547
548 ret = ath12k_dp_srng_setup(ab, &dp->reo_cmd_ring, HAL_REO_CMD,
549 0, 0, DP_REO_CMD_RING_SIZE);
550 if (ret) {
551 ath12k_warn(ab, "failed to set up reo_cmd ring :%d\n", ret);
552 goto err;
553 }
554
555 srng = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id];
556 ath12k_hal_reo_init_cmd_ring(ab, srng);
557
558 ret = ath12k_dp_srng_setup(ab, &dp->reo_status_ring, HAL_REO_STATUS,
559 0, 0, DP_REO_STATUS_RING_SIZE);
560 if (ret) {
561 ath12k_warn(ab, "failed to set up reo_status ring :%d\n", ret);
562 goto err;
563 }
564
565 /* When hash based routing of rx packet is enabled, 32 entries to map
566 * the hash values to the ring will be configured. Each hash entry uses
567 * four bits to map to a particular ring. The ring mapping will be
568 * 0:TCL, 1:SW1, 2:SW2, 3:SW3, 4:SW4, 5:Release, 6:FW and 7:SW5
569 * 8:SW6, 9:SW7, 10:SW8, 11:Not used.
570 */
571 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 |
572 HAL_HASH_ROUTING_RING_SW2 << 4 |
573 HAL_HASH_ROUTING_RING_SW3 << 8 |
574 HAL_HASH_ROUTING_RING_SW4 << 12 |
575 HAL_HASH_ROUTING_RING_SW1 << 16 |
576 HAL_HASH_ROUTING_RING_SW2 << 20 |
577 HAL_HASH_ROUTING_RING_SW3 << 24 |
578 HAL_HASH_ROUTING_RING_SW4 << 28;
579
580 ath12k_hal_reo_hw_setup(ab, ring_hash_map);
581
582 return 0;
583
584 err:
585 ath12k_dp_srng_common_cleanup(ab);
586
587 return ret;
588 }
589
ath12k_dp_scatter_idle_link_desc_cleanup(struct ath12k_base * ab)590 static void ath12k_dp_scatter_idle_link_desc_cleanup(struct ath12k_base *ab)
591 {
592 struct ath12k_dp *dp = &ab->dp;
593 struct hal_wbm_idle_scatter_list *slist = dp->scatter_list;
594 int i;
595
596 for (i = 0; i < DP_IDLE_SCATTER_BUFS_MAX; i++) {
597 if (!slist[i].vaddr)
598 continue;
599
600 dma_free_coherent(ab->dev, HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX,
601 slist[i].vaddr, slist[i].paddr);
602 slist[i].vaddr = NULL;
603 }
604 }
605
ath12k_dp_scatter_idle_link_desc_setup(struct ath12k_base * ab,int size,u32 n_link_desc_bank,u32 n_link_desc,u32 last_bank_sz)606 static int ath12k_dp_scatter_idle_link_desc_setup(struct ath12k_base *ab,
607 int size,
608 u32 n_link_desc_bank,
609 u32 n_link_desc,
610 u32 last_bank_sz)
611 {
612 struct ath12k_dp *dp = &ab->dp;
613 struct dp_link_desc_bank *link_desc_banks = dp->link_desc_banks;
614 struct hal_wbm_idle_scatter_list *slist = dp->scatter_list;
615 u32 n_entries_per_buf;
616 int num_scatter_buf, scatter_idx;
617 struct hal_wbm_link_desc *scatter_buf;
618 int align_bytes, n_entries;
619 dma_addr_t paddr;
620 int rem_entries;
621 int i;
622 int ret = 0;
623 u32 end_offset, cookie;
624
625 n_entries_per_buf = HAL_WBM_IDLE_SCATTER_BUF_SIZE /
626 ath12k_hal_srng_get_entrysize(ab, HAL_WBM_IDLE_LINK);
627 num_scatter_buf = DIV_ROUND_UP(size, HAL_WBM_IDLE_SCATTER_BUF_SIZE);
628
629 if (num_scatter_buf > DP_IDLE_SCATTER_BUFS_MAX)
630 return -EINVAL;
631
632 for (i = 0; i < num_scatter_buf; i++) {
633 slist[i].vaddr = dma_alloc_coherent(ab->dev,
634 HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX,
635 &slist[i].paddr, GFP_KERNEL);
636 if (!slist[i].vaddr) {
637 ret = -ENOMEM;
638 goto err;
639 }
640 }
641
642 scatter_idx = 0;
643 scatter_buf = slist[scatter_idx].vaddr;
644 rem_entries = n_entries_per_buf;
645
646 for (i = 0; i < n_link_desc_bank; i++) {
647 align_bytes = link_desc_banks[i].vaddr -
648 link_desc_banks[i].vaddr_unaligned;
649 n_entries = (DP_LINK_DESC_ALLOC_SIZE_THRESH - align_bytes) /
650 HAL_LINK_DESC_SIZE;
651 paddr = link_desc_banks[i].paddr;
652 while (n_entries) {
653 cookie = DP_LINK_DESC_COOKIE_SET(n_entries, i);
654 ath12k_hal_set_link_desc_addr(scatter_buf, cookie, paddr);
655 n_entries--;
656 paddr += HAL_LINK_DESC_SIZE;
657 if (rem_entries) {
658 rem_entries--;
659 scatter_buf++;
660 continue;
661 }
662
663 rem_entries = n_entries_per_buf;
664 scatter_idx++;
665 scatter_buf = slist[scatter_idx].vaddr;
666 }
667 }
668
669 end_offset = (scatter_buf - slist[scatter_idx].vaddr) *
670 sizeof(struct hal_wbm_link_desc);
671 ath12k_hal_setup_link_idle_list(ab, slist, num_scatter_buf,
672 n_link_desc, end_offset);
673
674 return 0;
675
676 err:
677 ath12k_dp_scatter_idle_link_desc_cleanup(ab);
678
679 return ret;
680 }
681
682 static void
ath12k_dp_link_desc_bank_free(struct ath12k_base * ab,struct dp_link_desc_bank * link_desc_banks)683 ath12k_dp_link_desc_bank_free(struct ath12k_base *ab,
684 struct dp_link_desc_bank *link_desc_banks)
685 {
686 int i;
687
688 for (i = 0; i < DP_LINK_DESC_BANKS_MAX; i++) {
689 if (link_desc_banks[i].vaddr_unaligned) {
690 dma_free_coherent(ab->dev,
691 link_desc_banks[i].size,
692 link_desc_banks[i].vaddr_unaligned,
693 link_desc_banks[i].paddr_unaligned);
694 link_desc_banks[i].vaddr_unaligned = NULL;
695 }
696 }
697 }
698
ath12k_dp_link_desc_bank_alloc(struct ath12k_base * ab,struct dp_link_desc_bank * desc_bank,int n_link_desc_bank,int last_bank_sz)699 static int ath12k_dp_link_desc_bank_alloc(struct ath12k_base *ab,
700 struct dp_link_desc_bank *desc_bank,
701 int n_link_desc_bank,
702 int last_bank_sz)
703 {
704 struct ath12k_dp *dp = &ab->dp;
705 int i;
706 int ret = 0;
707 int desc_sz = DP_LINK_DESC_ALLOC_SIZE_THRESH;
708
709 for (i = 0; i < n_link_desc_bank; i++) {
710 if (i == (n_link_desc_bank - 1) && last_bank_sz)
711 desc_sz = last_bank_sz;
712
713 desc_bank[i].vaddr_unaligned =
714 dma_alloc_coherent(ab->dev, desc_sz,
715 &desc_bank[i].paddr_unaligned,
716 GFP_KERNEL);
717 if (!desc_bank[i].vaddr_unaligned) {
718 ret = -ENOMEM;
719 goto err;
720 }
721
722 desc_bank[i].vaddr = PTR_ALIGN(desc_bank[i].vaddr_unaligned,
723 HAL_LINK_DESC_ALIGN);
724 desc_bank[i].paddr = desc_bank[i].paddr_unaligned +
725 ((unsigned long)desc_bank[i].vaddr -
726 (unsigned long)desc_bank[i].vaddr_unaligned);
727 desc_bank[i].size = desc_sz;
728 }
729
730 return 0;
731
732 err:
733 ath12k_dp_link_desc_bank_free(ab, dp->link_desc_banks);
734
735 return ret;
736 }
737
ath12k_dp_link_desc_cleanup(struct ath12k_base * ab,struct dp_link_desc_bank * desc_bank,u32 ring_type,struct dp_srng * ring)738 void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab,
739 struct dp_link_desc_bank *desc_bank,
740 u32 ring_type, struct dp_srng *ring)
741 {
742 ath12k_dp_link_desc_bank_free(ab, desc_bank);
743
744 if (ring_type != HAL_RXDMA_MONITOR_DESC) {
745 ath12k_dp_srng_cleanup(ab, ring);
746 ath12k_dp_scatter_idle_link_desc_cleanup(ab);
747 }
748 }
749
ath12k_wbm_idle_ring_setup(struct ath12k_base * ab,u32 * n_link_desc)750 static int ath12k_wbm_idle_ring_setup(struct ath12k_base *ab, u32 *n_link_desc)
751 {
752 struct ath12k_dp *dp = &ab->dp;
753 u32 n_mpdu_link_desc, n_mpdu_queue_desc;
754 u32 n_tx_msdu_link_desc, n_rx_msdu_link_desc;
755 int ret = 0;
756
757 n_mpdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_MPDUS_PER_TID_MAX) /
758 HAL_NUM_MPDUS_PER_LINK_DESC;
759
760 n_mpdu_queue_desc = n_mpdu_link_desc /
761 HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC;
762
763 n_tx_msdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_FLOWS_PER_TID *
764 DP_AVG_MSDUS_PER_FLOW) /
765 HAL_NUM_TX_MSDUS_PER_LINK_DESC;
766
767 n_rx_msdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_MPDUS_PER_TID_MAX *
768 DP_AVG_MSDUS_PER_MPDU) /
769 HAL_NUM_RX_MSDUS_PER_LINK_DESC;
770
771 *n_link_desc = n_mpdu_link_desc + n_mpdu_queue_desc +
772 n_tx_msdu_link_desc + n_rx_msdu_link_desc;
773
774 if (*n_link_desc & (*n_link_desc - 1))
775 *n_link_desc = 1 << fls(*n_link_desc);
776
777 ret = ath12k_dp_srng_setup(ab, &dp->wbm_idle_ring,
778 HAL_WBM_IDLE_LINK, 0, 0, *n_link_desc);
779 if (ret) {
780 ath12k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret);
781 return ret;
782 }
783 return ret;
784 }
785
ath12k_dp_link_desc_setup(struct ath12k_base * ab,struct dp_link_desc_bank * link_desc_banks,u32 ring_type,struct hal_srng * srng,u32 n_link_desc)786 int ath12k_dp_link_desc_setup(struct ath12k_base *ab,
787 struct dp_link_desc_bank *link_desc_banks,
788 u32 ring_type, struct hal_srng *srng,
789 u32 n_link_desc)
790 {
791 u32 tot_mem_sz;
792 u32 n_link_desc_bank, last_bank_sz;
793 u32 entry_sz, align_bytes, n_entries;
794 struct hal_wbm_link_desc *desc;
795 u32 paddr;
796 int i, ret;
797 u32 cookie;
798
799 tot_mem_sz = n_link_desc * HAL_LINK_DESC_SIZE;
800 tot_mem_sz += HAL_LINK_DESC_ALIGN;
801
802 if (tot_mem_sz <= DP_LINK_DESC_ALLOC_SIZE_THRESH) {
803 n_link_desc_bank = 1;
804 last_bank_sz = tot_mem_sz;
805 } else {
806 n_link_desc_bank = tot_mem_sz /
807 (DP_LINK_DESC_ALLOC_SIZE_THRESH -
808 HAL_LINK_DESC_ALIGN);
809 last_bank_sz = tot_mem_sz %
810 (DP_LINK_DESC_ALLOC_SIZE_THRESH -
811 HAL_LINK_DESC_ALIGN);
812
813 if (last_bank_sz)
814 n_link_desc_bank += 1;
815 }
816
817 if (n_link_desc_bank > DP_LINK_DESC_BANKS_MAX)
818 return -EINVAL;
819
820 ret = ath12k_dp_link_desc_bank_alloc(ab, link_desc_banks,
821 n_link_desc_bank, last_bank_sz);
822 if (ret)
823 return ret;
824
825 /* Setup link desc idle list for HW internal usage */
826 entry_sz = ath12k_hal_srng_get_entrysize(ab, ring_type);
827 tot_mem_sz = entry_sz * n_link_desc;
828
829 /* Setup scatter desc list when the total memory requirement is more */
830 if (tot_mem_sz > DP_LINK_DESC_ALLOC_SIZE_THRESH &&
831 ring_type != HAL_RXDMA_MONITOR_DESC) {
832 ret = ath12k_dp_scatter_idle_link_desc_setup(ab, tot_mem_sz,
833 n_link_desc_bank,
834 n_link_desc,
835 last_bank_sz);
836 if (ret) {
837 ath12k_warn(ab, "failed to setup scatting idle list descriptor :%d\n",
838 ret);
839 goto fail_desc_bank_free;
840 }
841
842 return 0;
843 }
844
845 spin_lock_bh(&srng->lock);
846
847 ath12k_hal_srng_access_begin(ab, srng);
848
849 for (i = 0; i < n_link_desc_bank; i++) {
850 align_bytes = link_desc_banks[i].vaddr -
851 link_desc_banks[i].vaddr_unaligned;
852 n_entries = (link_desc_banks[i].size - align_bytes) /
853 HAL_LINK_DESC_SIZE;
854 paddr = link_desc_banks[i].paddr;
855 while (n_entries &&
856 (desc = ath12k_hal_srng_src_get_next_entry(ab, srng))) {
857 cookie = DP_LINK_DESC_COOKIE_SET(n_entries, i);
858 ath12k_hal_set_link_desc_addr(desc,
859 cookie, paddr);
860 n_entries--;
861 paddr += HAL_LINK_DESC_SIZE;
862 }
863 }
864
865 ath12k_hal_srng_access_end(ab, srng);
866
867 spin_unlock_bh(&srng->lock);
868
869 return 0;
870
871 fail_desc_bank_free:
872 ath12k_dp_link_desc_bank_free(ab, link_desc_banks);
873
874 return ret;
875 }
876
ath12k_dp_service_srng(struct ath12k_base * ab,struct ath12k_ext_irq_grp * irq_grp,int budget)877 int ath12k_dp_service_srng(struct ath12k_base *ab,
878 struct ath12k_ext_irq_grp *irq_grp,
879 int budget)
880 {
881 struct napi_struct *napi = &irq_grp->napi;
882 int grp_id = irq_grp->grp_id;
883 int work_done = 0;
884 int i = 0, j;
885 int tot_work_done = 0;
886 enum dp_monitor_mode monitor_mode;
887 u8 ring_mask;
888
889 if (ab->hw_params->ring_mask->tx[grp_id]) {
890 i = fls(ab->hw_params->ring_mask->tx[grp_id]) - 1;
891 ath12k_dp_tx_completion_handler(ab, i);
892 }
893
894 if (ab->hw_params->ring_mask->rx_err[grp_id]) {
895 work_done = ath12k_dp_rx_process_err(ab, napi, budget);
896 budget -= work_done;
897 tot_work_done += work_done;
898 if (budget <= 0)
899 goto done;
900 }
901
902 if (ab->hw_params->ring_mask->rx_wbm_rel[grp_id]) {
903 work_done = ath12k_dp_rx_process_wbm_err(ab,
904 napi,
905 budget);
906 budget -= work_done;
907 tot_work_done += work_done;
908
909 if (budget <= 0)
910 goto done;
911 }
912
913 if (ab->hw_params->ring_mask->rx[grp_id]) {
914 i = fls(ab->hw_params->ring_mask->rx[grp_id]) - 1;
915 work_done = ath12k_dp_rx_process(ab, i, napi,
916 budget);
917 budget -= work_done;
918 tot_work_done += work_done;
919 if (budget <= 0)
920 goto done;
921 }
922
923 if (ab->hw_params->ring_mask->rx_mon_dest[grp_id]) {
924 monitor_mode = ATH12K_DP_RX_MONITOR_MODE;
925 ring_mask = ab->hw_params->ring_mask->rx_mon_dest[grp_id];
926 for (i = 0; i < ab->num_radios; i++) {
927 for (j = 0; j < ab->hw_params->num_rxmda_per_pdev; j++) {
928 int id = i * ab->hw_params->num_rxmda_per_pdev + j;
929
930 if (ring_mask & BIT(id)) {
931 work_done =
932 ath12k_dp_mon_process_ring(ab, id, napi, budget,
933 monitor_mode);
934 budget -= work_done;
935 tot_work_done += work_done;
936
937 if (budget <= 0)
938 goto done;
939 }
940 }
941 }
942 }
943
944 if (ab->hw_params->ring_mask->tx_mon_dest[grp_id]) {
945 monitor_mode = ATH12K_DP_TX_MONITOR_MODE;
946 ring_mask = ab->hw_params->ring_mask->tx_mon_dest[grp_id];
947 for (i = 0; i < ab->num_radios; i++) {
948 for (j = 0; j < ab->hw_params->num_rxmda_per_pdev; j++) {
949 int id = i * ab->hw_params->num_rxmda_per_pdev + j;
950
951 if (ring_mask & BIT(id)) {
952 work_done =
953 ath12k_dp_mon_process_ring(ab, id, napi, budget,
954 monitor_mode);
955 budget -= work_done;
956 tot_work_done += work_done;
957
958 if (budget <= 0)
959 goto done;
960 }
961 }
962 }
963 }
964
965 if (ab->hw_params->ring_mask->reo_status[grp_id])
966 ath12k_dp_rx_process_reo_status(ab);
967
968 if (ab->hw_params->ring_mask->host2rxdma[grp_id]) {
969 struct ath12k_dp *dp = &ab->dp;
970 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
971
972 ath12k_dp_rx_bufs_replenish(ab, 0, rx_ring, 0,
973 ab->hw_params->hal_params->rx_buf_rbm,
974 true);
975 }
976
977 /* TODO: Implement handler for other interrupts */
978
979 done:
980 return tot_work_done;
981 }
982
ath12k_dp_pdev_free(struct ath12k_base * ab)983 void ath12k_dp_pdev_free(struct ath12k_base *ab)
984 {
985 int i;
986
987 del_timer_sync(&ab->mon_reap_timer);
988
989 for (i = 0; i < ab->num_radios; i++)
990 ath12k_dp_rx_pdev_free(ab, i);
991 }
992
ath12k_dp_pdev_pre_alloc(struct ath12k_base * ab)993 void ath12k_dp_pdev_pre_alloc(struct ath12k_base *ab)
994 {
995 struct ath12k *ar;
996 struct ath12k_pdev_dp *dp;
997 int i;
998
999 for (i = 0; i < ab->num_radios; i++) {
1000 ar = ab->pdevs[i].ar;
1001 dp = &ar->dp;
1002 dp->mac_id = i;
1003 atomic_set(&dp->num_tx_pending, 0);
1004 init_waitqueue_head(&dp->tx_empty_waitq);
1005
1006 /* TODO: Add any RXDMA setup required per pdev */
1007 }
1008 }
1009
ath12k_dp_service_mon_ring(struct timer_list * t)1010 static void ath12k_dp_service_mon_ring(struct timer_list *t)
1011 {
1012 struct ath12k_base *ab = from_timer(ab, t, mon_reap_timer);
1013 int i;
1014
1015 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++)
1016 ath12k_dp_mon_process_ring(ab, i, NULL, DP_MON_SERVICE_BUDGET,
1017 ATH12K_DP_RX_MONITOR_MODE);
1018
1019 mod_timer(&ab->mon_reap_timer, jiffies +
1020 msecs_to_jiffies(ATH12K_MON_TIMER_INTERVAL));
1021 }
1022
ath12k_dp_mon_reap_timer_init(struct ath12k_base * ab)1023 static void ath12k_dp_mon_reap_timer_init(struct ath12k_base *ab)
1024 {
1025 if (ab->hw_params->rxdma1_enable)
1026 return;
1027
1028 timer_setup(&ab->mon_reap_timer, ath12k_dp_service_mon_ring, 0);
1029 }
1030
ath12k_dp_pdev_alloc(struct ath12k_base * ab)1031 int ath12k_dp_pdev_alloc(struct ath12k_base *ab)
1032 {
1033 struct ath12k *ar;
1034 int ret;
1035 int i;
1036
1037 ret = ath12k_dp_rx_htt_setup(ab);
1038 if (ret)
1039 goto out;
1040
1041 ath12k_dp_mon_reap_timer_init(ab);
1042
1043 /* TODO: Per-pdev rx ring unlike tx ring which is mapped to different AC's */
1044 for (i = 0; i < ab->num_radios; i++) {
1045 ar = ab->pdevs[i].ar;
1046 ret = ath12k_dp_rx_pdev_alloc(ab, i);
1047 if (ret) {
1048 ath12k_warn(ab, "failed to allocate pdev rx for pdev_id :%d\n",
1049 i);
1050 goto err;
1051 }
1052 ret = ath12k_dp_rx_pdev_mon_attach(ar);
1053 if (ret) {
1054 ath12k_warn(ab, "failed to initialize mon pdev %d\n", i);
1055 goto err;
1056 }
1057 }
1058
1059 return 0;
1060 err:
1061 ath12k_dp_pdev_free(ab);
1062 out:
1063 return ret;
1064 }
1065
ath12k_dp_htt_connect(struct ath12k_dp * dp)1066 int ath12k_dp_htt_connect(struct ath12k_dp *dp)
1067 {
1068 struct ath12k_htc_svc_conn_req conn_req = {0};
1069 struct ath12k_htc_svc_conn_resp conn_resp = {0};
1070 int status;
1071
1072 conn_req.ep_ops.ep_tx_complete = ath12k_dp_htt_htc_tx_complete;
1073 conn_req.ep_ops.ep_rx_complete = ath12k_dp_htt_htc_t2h_msg_handler;
1074
1075 /* connect to control service */
1076 conn_req.service_id = ATH12K_HTC_SVC_ID_HTT_DATA_MSG;
1077
1078 status = ath12k_htc_connect_service(&dp->ab->htc, &conn_req,
1079 &conn_resp);
1080
1081 if (status)
1082 return status;
1083
1084 dp->eid = conn_resp.eid;
1085
1086 return 0;
1087 }
1088
ath12k_dp_update_vdev_search(struct ath12k_vif * arvif)1089 static void ath12k_dp_update_vdev_search(struct ath12k_vif *arvif)
1090 {
1091 switch (arvif->vdev_type) {
1092 case WMI_VDEV_TYPE_STA:
1093 /* TODO: Verify the search type and flags since ast hash
1094 * is not part of peer mapv3
1095 */
1096 arvif->hal_addr_search_flags = HAL_TX_ADDRY_EN;
1097 arvif->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
1098 break;
1099 case WMI_VDEV_TYPE_AP:
1100 case WMI_VDEV_TYPE_IBSS:
1101 arvif->hal_addr_search_flags = HAL_TX_ADDRX_EN;
1102 arvif->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
1103 break;
1104 case WMI_VDEV_TYPE_MONITOR:
1105 default:
1106 return;
1107 }
1108 }
1109
ath12k_dp_vdev_tx_attach(struct ath12k * ar,struct ath12k_vif * arvif)1110 void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_vif *arvif)
1111 {
1112 struct ath12k_base *ab = ar->ab;
1113
1114 arvif->tcl_metadata |= u32_encode_bits(1, HTT_TCL_META_DATA_TYPE) |
1115 u32_encode_bits(arvif->vdev_id,
1116 HTT_TCL_META_DATA_VDEV_ID) |
1117 u32_encode_bits(ar->pdev->pdev_id,
1118 HTT_TCL_META_DATA_PDEV_ID);
1119
1120 /* set HTT extension valid bit to 0 by default */
1121 arvif->tcl_metadata &= ~HTT_TCL_META_DATA_VALID_HTT;
1122
1123 ath12k_dp_update_vdev_search(arvif);
1124 arvif->vdev_id_check_en = true;
1125 arvif->bank_id = ath12k_dp_tx_get_bank_profile(ab, arvif, &ab->dp);
1126
1127 /* TODO: error path for bank id failure */
1128 if (arvif->bank_id == DP_INVALID_BANK_ID) {
1129 ath12k_err(ar->ab, "Failed to initialize DP TX Banks");
1130 return;
1131 }
1132 }
1133
ath12k_dp_cc_cleanup(struct ath12k_base * ab)1134 static void ath12k_dp_cc_cleanup(struct ath12k_base *ab)
1135 {
1136 struct ath12k_rx_desc_info *desc_info, *tmp;
1137 struct ath12k_tx_desc_info *tx_desc_info, *tmp1;
1138 struct ath12k_dp *dp = &ab->dp;
1139 struct sk_buff *skb;
1140 int i;
1141 u32 pool_id, tx_spt_page;
1142
1143 if (!dp->spt_info)
1144 return;
1145
1146 /* RX Descriptor cleanup */
1147 spin_lock_bh(&dp->rx_desc_lock);
1148
1149 list_for_each_entry_safe(desc_info, tmp, &dp->rx_desc_used_list, list) {
1150 list_del(&desc_info->list);
1151 skb = desc_info->skb;
1152
1153 if (!skb)
1154 continue;
1155
1156 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr,
1157 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
1158 dev_kfree_skb_any(skb);
1159 }
1160
1161 for (i = 0; i < ATH12K_NUM_RX_SPT_PAGES; i++) {
1162 if (!dp->spt_info->rxbaddr[i])
1163 continue;
1164
1165 kfree(dp->spt_info->rxbaddr[i]);
1166 dp->spt_info->rxbaddr[i] = NULL;
1167 }
1168
1169 spin_unlock_bh(&dp->rx_desc_lock);
1170
1171 /* TX Descriptor cleanup */
1172 for (i = 0; i < ATH12K_HW_MAX_QUEUES; i++) {
1173 spin_lock_bh(&dp->tx_desc_lock[i]);
1174
1175 list_for_each_entry_safe(tx_desc_info, tmp1, &dp->tx_desc_used_list[i],
1176 list) {
1177 list_del(&tx_desc_info->list);
1178 skb = tx_desc_info->skb;
1179
1180 if (!skb)
1181 continue;
1182
1183 dma_unmap_single(ab->dev, ATH12K_SKB_CB(skb)->paddr,
1184 skb->len, DMA_TO_DEVICE);
1185 dev_kfree_skb_any(skb);
1186 }
1187
1188 spin_unlock_bh(&dp->tx_desc_lock[i]);
1189 }
1190
1191 for (pool_id = 0; pool_id < ATH12K_HW_MAX_QUEUES; pool_id++) {
1192 spin_lock_bh(&dp->tx_desc_lock[pool_id]);
1193
1194 for (i = 0; i < ATH12K_TX_SPT_PAGES_PER_POOL; i++) {
1195 tx_spt_page = i + pool_id * ATH12K_TX_SPT_PAGES_PER_POOL;
1196 if (!dp->spt_info->txbaddr[tx_spt_page])
1197 continue;
1198
1199 kfree(dp->spt_info->txbaddr[tx_spt_page]);
1200 dp->spt_info->txbaddr[tx_spt_page] = NULL;
1201 }
1202
1203 spin_unlock_bh(&dp->tx_desc_lock[pool_id]);
1204 }
1205
1206 /* unmap SPT pages */
1207 for (i = 0; i < dp->num_spt_pages; i++) {
1208 if (!dp->spt_info[i].vaddr)
1209 continue;
1210
1211 dma_free_coherent(ab->dev, ATH12K_PAGE_SIZE,
1212 dp->spt_info[i].vaddr, dp->spt_info[i].paddr);
1213 dp->spt_info[i].vaddr = NULL;
1214 }
1215
1216 kfree(dp->spt_info);
1217 }
1218
ath12k_dp_reoq_lut_cleanup(struct ath12k_base * ab)1219 static void ath12k_dp_reoq_lut_cleanup(struct ath12k_base *ab)
1220 {
1221 struct ath12k_dp *dp = &ab->dp;
1222
1223 if (!ab->hw_params->reoq_lut_support)
1224 return;
1225
1226 if (!dp->reoq_lut.vaddr)
1227 return;
1228
1229 dma_free_coherent(ab->dev, DP_REOQ_LUT_SIZE,
1230 dp->reoq_lut.vaddr, dp->reoq_lut.paddr);
1231 dp->reoq_lut.vaddr = NULL;
1232
1233 ath12k_hif_write32(ab,
1234 HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE0(ab), 0);
1235 }
1236
ath12k_dp_free(struct ath12k_base * ab)1237 void ath12k_dp_free(struct ath12k_base *ab)
1238 {
1239 struct ath12k_dp *dp = &ab->dp;
1240 int i;
1241
1242 ath12k_dp_link_desc_cleanup(ab, dp->link_desc_banks,
1243 HAL_WBM_IDLE_LINK, &dp->wbm_idle_ring);
1244
1245 ath12k_dp_cc_cleanup(ab);
1246 ath12k_dp_reoq_lut_cleanup(ab);
1247 ath12k_dp_deinit_bank_profiles(ab);
1248 ath12k_dp_srng_common_cleanup(ab);
1249
1250 ath12k_dp_rx_reo_cmd_list_cleanup(ab);
1251
1252 for (i = 0; i < ab->hw_params->max_tx_ring; i++)
1253 kfree(dp->tx_ring[i].tx_status);
1254
1255 ath12k_dp_rx_free(ab);
1256 /* Deinit any SOC level resource */
1257 }
1258
ath12k_dp_cc_config(struct ath12k_base * ab)1259 void ath12k_dp_cc_config(struct ath12k_base *ab)
1260 {
1261 u32 cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start;
1262 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
1263 u32 wbm_base = HAL_SEQ_WCSS_UMAC_WBM_REG;
1264 u32 val = 0;
1265
1266 ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG0(ab), cmem_base);
1267
1268 val |= u32_encode_bits(ATH12K_CMEM_ADDR_MSB,
1269 HAL_REO1_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB) |
1270 u32_encode_bits(ATH12K_CC_PPT_MSB,
1271 HAL_REO1_SW_COOKIE_CFG_COOKIE_PPT_MSB) |
1272 u32_encode_bits(ATH12K_CC_SPT_MSB,
1273 HAL_REO1_SW_COOKIE_CFG_COOKIE_SPT_MSB) |
1274 u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_ALIGN) |
1275 u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_ENABLE) |
1276 u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_GLOBAL_ENABLE);
1277
1278 ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG1(ab), val);
1279
1280 /* Enable HW CC for WBM */
1281 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG0, cmem_base);
1282
1283 val = u32_encode_bits(ATH12K_CMEM_ADDR_MSB,
1284 HAL_WBM_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB) |
1285 u32_encode_bits(ATH12K_CC_PPT_MSB,
1286 HAL_WBM_SW_COOKIE_CFG_COOKIE_PPT_MSB) |
1287 u32_encode_bits(ATH12K_CC_SPT_MSB,
1288 HAL_WBM_SW_COOKIE_CFG_COOKIE_SPT_MSB) |
1289 u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_ALIGN);
1290
1291 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG1, val);
1292
1293 /* Enable conversion complete indication */
1294 val = ath12k_hif_read32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2);
1295 val |= u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_RELEASE_PATH_EN) |
1296 u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_ERR_PATH_EN) |
1297 u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_CONV_IND_EN);
1298
1299 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2, val);
1300
1301 /* Enable Cookie conversion for WBM2SW Rings */
1302 val = ath12k_hif_read32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG);
1303 val |= u32_encode_bits(1, HAL_WBM_SW_COOKIE_CONV_CFG_GLOBAL_EN) |
1304 ab->hw_params->hal_params->wbm2sw_cc_enable;
1305
1306 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG, val);
1307 }
1308
ath12k_dp_cc_cookie_gen(u16 ppt_idx,u16 spt_idx)1309 static u32 ath12k_dp_cc_cookie_gen(u16 ppt_idx, u16 spt_idx)
1310 {
1311 return (u32)ppt_idx << ATH12K_CC_PPT_SHIFT | spt_idx;
1312 }
1313
ath12k_dp_cc_get_desc_addr_ptr(struct ath12k_base * ab,u16 ppt_idx,u16 spt_idx)1314 static inline void *ath12k_dp_cc_get_desc_addr_ptr(struct ath12k_base *ab,
1315 u16 ppt_idx, u16 spt_idx)
1316 {
1317 struct ath12k_dp *dp = &ab->dp;
1318
1319 return dp->spt_info[ppt_idx].vaddr + spt_idx;
1320 }
1321
ath12k_dp_get_rx_desc(struct ath12k_base * ab,u32 cookie)1322 struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab,
1323 u32 cookie)
1324 {
1325 struct ath12k_rx_desc_info **desc_addr_ptr;
1326 u16 ppt_idx, spt_idx;
1327
1328 ppt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_PPT);
1329 spt_idx = u32_get_bits(cookie, ATH12k_DP_CC_COOKIE_SPT);
1330
1331 if (ppt_idx > ATH12K_NUM_RX_SPT_PAGES ||
1332 spt_idx > ATH12K_MAX_SPT_ENTRIES)
1333 return NULL;
1334
1335 desc_addr_ptr = ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, spt_idx);
1336
1337 return *desc_addr_ptr;
1338 }
1339
ath12k_dp_get_tx_desc(struct ath12k_base * ab,u32 cookie)1340 struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab,
1341 u32 cookie)
1342 {
1343 struct ath12k_tx_desc_info **desc_addr_ptr;
1344 u16 ppt_idx, spt_idx;
1345
1346 ppt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_PPT);
1347 spt_idx = u32_get_bits(cookie, ATH12k_DP_CC_COOKIE_SPT);
1348
1349 if (ppt_idx < ATH12K_NUM_RX_SPT_PAGES ||
1350 ppt_idx > ab->dp.num_spt_pages ||
1351 spt_idx > ATH12K_MAX_SPT_ENTRIES)
1352 return NULL;
1353
1354 desc_addr_ptr = ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, spt_idx);
1355
1356 return *desc_addr_ptr;
1357 }
1358
ath12k_dp_cc_desc_init(struct ath12k_base * ab)1359 static int ath12k_dp_cc_desc_init(struct ath12k_base *ab)
1360 {
1361 struct ath12k_dp *dp = &ab->dp;
1362 struct ath12k_rx_desc_info *rx_descs, **rx_desc_addr;
1363 struct ath12k_tx_desc_info *tx_descs, **tx_desc_addr;
1364 u32 i, j, pool_id, tx_spt_page;
1365 u32 ppt_idx;
1366
1367 spin_lock_bh(&dp->rx_desc_lock);
1368
1369 /* First ATH12K_NUM_RX_SPT_PAGES of allocated SPT pages are used for RX */
1370 for (i = 0; i < ATH12K_NUM_RX_SPT_PAGES; i++) {
1371 rx_descs = kcalloc(ATH12K_MAX_SPT_ENTRIES, sizeof(*rx_descs),
1372 GFP_ATOMIC);
1373
1374 if (!rx_descs) {
1375 spin_unlock_bh(&dp->rx_desc_lock);
1376 return -ENOMEM;
1377 }
1378
1379 dp->spt_info->rxbaddr[i] = &rx_descs[0];
1380
1381 for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) {
1382 rx_descs[j].cookie = ath12k_dp_cc_cookie_gen(i, j);
1383 rx_descs[j].magic = ATH12K_DP_RX_DESC_MAGIC;
1384 list_add_tail(&rx_descs[j].list, &dp->rx_desc_free_list);
1385
1386 /* Update descriptor VA in SPT */
1387 rx_desc_addr = ath12k_dp_cc_get_desc_addr_ptr(ab, i, j);
1388 *rx_desc_addr = &rx_descs[j];
1389 }
1390 }
1391
1392 spin_unlock_bh(&dp->rx_desc_lock);
1393
1394 for (pool_id = 0; pool_id < ATH12K_HW_MAX_QUEUES; pool_id++) {
1395 spin_lock_bh(&dp->tx_desc_lock[pool_id]);
1396 for (i = 0; i < ATH12K_TX_SPT_PAGES_PER_POOL; i++) {
1397 tx_descs = kcalloc(ATH12K_MAX_SPT_ENTRIES, sizeof(*tx_descs),
1398 GFP_ATOMIC);
1399
1400 if (!tx_descs) {
1401 spin_unlock_bh(&dp->tx_desc_lock[pool_id]);
1402 /* Caller takes care of TX pending and RX desc cleanup */
1403 return -ENOMEM;
1404 }
1405
1406 tx_spt_page = i + pool_id * ATH12K_TX_SPT_PAGES_PER_POOL;
1407 dp->spt_info->txbaddr[tx_spt_page] = &tx_descs[0];
1408
1409 for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) {
1410 ppt_idx = ATH12K_NUM_RX_SPT_PAGES + tx_spt_page;
1411 tx_descs[j].desc_id = ath12k_dp_cc_cookie_gen(ppt_idx, j);
1412 tx_descs[j].pool_id = pool_id;
1413 list_add_tail(&tx_descs[j].list,
1414 &dp->tx_desc_free_list[pool_id]);
1415
1416 /* Update descriptor VA in SPT */
1417 tx_desc_addr =
1418 ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, j);
1419 *tx_desc_addr = &tx_descs[j];
1420 }
1421 }
1422 spin_unlock_bh(&dp->tx_desc_lock[pool_id]);
1423 }
1424 return 0;
1425 }
1426
ath12k_dp_cc_init(struct ath12k_base * ab)1427 static int ath12k_dp_cc_init(struct ath12k_base *ab)
1428 {
1429 struct ath12k_dp *dp = &ab->dp;
1430 int i, ret = 0;
1431 u32 cmem_base;
1432
1433 INIT_LIST_HEAD(&dp->rx_desc_free_list);
1434 INIT_LIST_HEAD(&dp->rx_desc_used_list);
1435 spin_lock_init(&dp->rx_desc_lock);
1436
1437 for (i = 0; i < ATH12K_HW_MAX_QUEUES; i++) {
1438 INIT_LIST_HEAD(&dp->tx_desc_free_list[i]);
1439 INIT_LIST_HEAD(&dp->tx_desc_used_list[i]);
1440 spin_lock_init(&dp->tx_desc_lock[i]);
1441 }
1442
1443 dp->num_spt_pages = ATH12K_NUM_SPT_PAGES;
1444 if (dp->num_spt_pages > ATH12K_MAX_PPT_ENTRIES)
1445 dp->num_spt_pages = ATH12K_MAX_PPT_ENTRIES;
1446
1447 dp->spt_info = kcalloc(dp->num_spt_pages, sizeof(struct ath12k_spt_info),
1448 GFP_KERNEL);
1449
1450 if (!dp->spt_info) {
1451 ath12k_warn(ab, "SPT page allocation failure");
1452 return -ENOMEM;
1453 }
1454
1455 cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start;
1456
1457 for (i = 0; i < dp->num_spt_pages; i++) {
1458 dp->spt_info[i].vaddr = dma_alloc_coherent(ab->dev,
1459 ATH12K_PAGE_SIZE,
1460 &dp->spt_info[i].paddr,
1461 GFP_KERNEL);
1462
1463 if (!dp->spt_info[i].vaddr) {
1464 ret = -ENOMEM;
1465 goto free;
1466 }
1467
1468 if (dp->spt_info[i].paddr & ATH12K_SPT_4K_ALIGN_CHECK) {
1469 ath12k_warn(ab, "SPT allocated memory is not 4K aligned");
1470 ret = -EINVAL;
1471 goto free;
1472 }
1473
1474 /* Write to PPT in CMEM */
1475 ath12k_hif_write32(ab, cmem_base + ATH12K_PPT_ADDR_OFFSET(i),
1476 dp->spt_info[i].paddr >> ATH12K_SPT_4K_ALIGN_OFFSET);
1477 }
1478
1479 ret = ath12k_dp_cc_desc_init(ab);
1480 if (ret) {
1481 ath12k_warn(ab, "HW CC desc init failed %d", ret);
1482 goto free;
1483 }
1484
1485 return 0;
1486 free:
1487 ath12k_dp_cc_cleanup(ab);
1488 return ret;
1489 }
1490
ath12k_dp_reoq_lut_setup(struct ath12k_base * ab)1491 static int ath12k_dp_reoq_lut_setup(struct ath12k_base *ab)
1492 {
1493 struct ath12k_dp *dp = &ab->dp;
1494
1495 if (!ab->hw_params->reoq_lut_support)
1496 return 0;
1497
1498 dp->reoq_lut.vaddr = dma_alloc_coherent(ab->dev,
1499 DP_REOQ_LUT_SIZE,
1500 &dp->reoq_lut.paddr,
1501 GFP_KERNEL | __GFP_ZERO);
1502 if (!dp->reoq_lut.vaddr) {
1503 ath12k_warn(ab, "failed to allocate memory for reoq table");
1504 return -ENOMEM;
1505 }
1506
1507 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE0(ab),
1508 dp->reoq_lut.paddr);
1509 return 0;
1510 }
1511
ath12k_dp_alloc(struct ath12k_base * ab)1512 int ath12k_dp_alloc(struct ath12k_base *ab)
1513 {
1514 struct ath12k_dp *dp = &ab->dp;
1515 struct hal_srng *srng = NULL;
1516 size_t size = 0;
1517 u32 n_link_desc = 0;
1518 int ret;
1519 int i;
1520
1521 dp->ab = ab;
1522
1523 INIT_LIST_HEAD(&dp->reo_cmd_list);
1524 INIT_LIST_HEAD(&dp->reo_cmd_cache_flush_list);
1525 spin_lock_init(&dp->reo_cmd_lock);
1526
1527 dp->reo_cmd_cache_flush_count = 0;
1528
1529 ret = ath12k_wbm_idle_ring_setup(ab, &n_link_desc);
1530 if (ret) {
1531 ath12k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret);
1532 return ret;
1533 }
1534
1535 srng = &ab->hal.srng_list[dp->wbm_idle_ring.ring_id];
1536
1537 ret = ath12k_dp_link_desc_setup(ab, dp->link_desc_banks,
1538 HAL_WBM_IDLE_LINK, srng, n_link_desc);
1539 if (ret) {
1540 ath12k_warn(ab, "failed to setup link desc: %d\n", ret);
1541 return ret;
1542 }
1543
1544 ret = ath12k_dp_cc_init(ab);
1545
1546 if (ret) {
1547 ath12k_warn(ab, "failed to setup cookie converter %d\n", ret);
1548 goto fail_link_desc_cleanup;
1549 }
1550 ret = ath12k_dp_init_bank_profiles(ab);
1551 if (ret) {
1552 ath12k_warn(ab, "failed to setup bank profiles %d\n", ret);
1553 goto fail_hw_cc_cleanup;
1554 }
1555
1556 ret = ath12k_dp_srng_common_setup(ab);
1557 if (ret)
1558 goto fail_dp_bank_profiles_cleanup;
1559
1560 size = sizeof(struct hal_wbm_release_ring_tx) * DP_TX_COMP_RING_SIZE;
1561
1562 ret = ath12k_dp_reoq_lut_setup(ab);
1563 if (ret) {
1564 ath12k_warn(ab, "failed to setup reoq table %d\n", ret);
1565 goto fail_cmn_srng_cleanup;
1566 }
1567
1568 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
1569 dp->tx_ring[i].tcl_data_ring_id = i;
1570
1571 dp->tx_ring[i].tx_status_head = 0;
1572 dp->tx_ring[i].tx_status_tail = DP_TX_COMP_RING_SIZE - 1;
1573 dp->tx_ring[i].tx_status = kmalloc(size, GFP_KERNEL);
1574 if (!dp->tx_ring[i].tx_status) {
1575 ret = -ENOMEM;
1576 /* FIXME: The allocated tx status is not freed
1577 * properly here
1578 */
1579 goto fail_cmn_reoq_cleanup;
1580 }
1581 }
1582
1583 for (i = 0; i < HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX; i++)
1584 ath12k_hal_tx_set_dscp_tid_map(ab, i);
1585
1586 ret = ath12k_dp_rx_alloc(ab);
1587 if (ret)
1588 goto fail_dp_rx_free;
1589
1590 /* Init any SOC level resource for DP */
1591
1592 return 0;
1593
1594 fail_dp_rx_free:
1595 ath12k_dp_rx_free(ab);
1596
1597 fail_cmn_reoq_cleanup:
1598 ath12k_dp_reoq_lut_cleanup(ab);
1599
1600 fail_cmn_srng_cleanup:
1601 ath12k_dp_srng_common_cleanup(ab);
1602
1603 fail_dp_bank_profiles_cleanup:
1604 ath12k_dp_deinit_bank_profiles(ab);
1605
1606 fail_hw_cc_cleanup:
1607 ath12k_dp_cc_cleanup(ab);
1608
1609 fail_link_desc_cleanup:
1610 ath12k_dp_link_desc_cleanup(ab, dp->link_desc_banks,
1611 HAL_WBM_IDLE_LINK, &dp->wbm_idle_ring);
1612
1613 return ret;
1614 }
1615