1 /*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/export.h>
22 #include <linux/gpio.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/platform_data/b53.h>
26 #include <linux/phy.h>
27 #include <linux/phylink.h>
28 #include <linux/etherdevice.h>
29 #include <linux/if_bridge.h>
30 #include <net/dsa.h>
31
32 #include "b53_regs.h"
33 #include "b53_priv.h"
34
35 struct b53_mib_desc {
36 u8 size;
37 u8 offset;
38 const char *name;
39 };
40
41 /* BCM5365 MIB counters */
42 static const struct b53_mib_desc b53_mibs_65[] = {
43 { 8, 0x00, "TxOctets" },
44 { 4, 0x08, "TxDropPkts" },
45 { 4, 0x10, "TxBroadcastPkts" },
46 { 4, 0x14, "TxMulticastPkts" },
47 { 4, 0x18, "TxUnicastPkts" },
48 { 4, 0x1c, "TxCollisions" },
49 { 4, 0x20, "TxSingleCollision" },
50 { 4, 0x24, "TxMultipleCollision" },
51 { 4, 0x28, "TxDeferredTransmit" },
52 { 4, 0x2c, "TxLateCollision" },
53 { 4, 0x30, "TxExcessiveCollision" },
54 { 4, 0x38, "TxPausePkts" },
55 { 8, 0x44, "RxOctets" },
56 { 4, 0x4c, "RxUndersizePkts" },
57 { 4, 0x50, "RxPausePkts" },
58 { 4, 0x54, "Pkts64Octets" },
59 { 4, 0x58, "Pkts65to127Octets" },
60 { 4, 0x5c, "Pkts128to255Octets" },
61 { 4, 0x60, "Pkts256to511Octets" },
62 { 4, 0x64, "Pkts512to1023Octets" },
63 { 4, 0x68, "Pkts1024to1522Octets" },
64 { 4, 0x6c, "RxOversizePkts" },
65 { 4, 0x70, "RxJabbers" },
66 { 4, 0x74, "RxAlignmentErrors" },
67 { 4, 0x78, "RxFCSErrors" },
68 { 8, 0x7c, "RxGoodOctets" },
69 { 4, 0x84, "RxDropPkts" },
70 { 4, 0x88, "RxUnicastPkts" },
71 { 4, 0x8c, "RxMulticastPkts" },
72 { 4, 0x90, "RxBroadcastPkts" },
73 { 4, 0x94, "RxSAChanges" },
74 { 4, 0x98, "RxFragments" },
75 };
76
77 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
78
79 /* BCM63xx MIB counters */
80 static const struct b53_mib_desc b53_mibs_63xx[] = {
81 { 8, 0x00, "TxOctets" },
82 { 4, 0x08, "TxDropPkts" },
83 { 4, 0x0c, "TxQoSPkts" },
84 { 4, 0x10, "TxBroadcastPkts" },
85 { 4, 0x14, "TxMulticastPkts" },
86 { 4, 0x18, "TxUnicastPkts" },
87 { 4, 0x1c, "TxCollisions" },
88 { 4, 0x20, "TxSingleCollision" },
89 { 4, 0x24, "TxMultipleCollision" },
90 { 4, 0x28, "TxDeferredTransmit" },
91 { 4, 0x2c, "TxLateCollision" },
92 { 4, 0x30, "TxExcessiveCollision" },
93 { 4, 0x38, "TxPausePkts" },
94 { 8, 0x3c, "TxQoSOctets" },
95 { 8, 0x44, "RxOctets" },
96 { 4, 0x4c, "RxUndersizePkts" },
97 { 4, 0x50, "RxPausePkts" },
98 { 4, 0x54, "Pkts64Octets" },
99 { 4, 0x58, "Pkts65to127Octets" },
100 { 4, 0x5c, "Pkts128to255Octets" },
101 { 4, 0x60, "Pkts256to511Octets" },
102 { 4, 0x64, "Pkts512to1023Octets" },
103 { 4, 0x68, "Pkts1024to1522Octets" },
104 { 4, 0x6c, "RxOversizePkts" },
105 { 4, 0x70, "RxJabbers" },
106 { 4, 0x74, "RxAlignmentErrors" },
107 { 4, 0x78, "RxFCSErrors" },
108 { 8, 0x7c, "RxGoodOctets" },
109 { 4, 0x84, "RxDropPkts" },
110 { 4, 0x88, "RxUnicastPkts" },
111 { 4, 0x8c, "RxMulticastPkts" },
112 { 4, 0x90, "RxBroadcastPkts" },
113 { 4, 0x94, "RxSAChanges" },
114 { 4, 0x98, "RxFragments" },
115 { 4, 0xa0, "RxSymbolErrors" },
116 { 4, 0xa4, "RxQoSPkts" },
117 { 8, 0xa8, "RxQoSOctets" },
118 { 4, 0xb0, "Pkts1523to2047Octets" },
119 { 4, 0xb4, "Pkts2048to4095Octets" },
120 { 4, 0xb8, "Pkts4096to8191Octets" },
121 { 4, 0xbc, "Pkts8192to9728Octets" },
122 { 4, 0xc0, "RxDiscarded" },
123 };
124
125 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
126
127 /* MIB counters */
128 static const struct b53_mib_desc b53_mibs[] = {
129 { 8, 0x00, "TxOctets" },
130 { 4, 0x08, "TxDropPkts" },
131 { 4, 0x10, "TxBroadcastPkts" },
132 { 4, 0x14, "TxMulticastPkts" },
133 { 4, 0x18, "TxUnicastPkts" },
134 { 4, 0x1c, "TxCollisions" },
135 { 4, 0x20, "TxSingleCollision" },
136 { 4, 0x24, "TxMultipleCollision" },
137 { 4, 0x28, "TxDeferredTransmit" },
138 { 4, 0x2c, "TxLateCollision" },
139 { 4, 0x30, "TxExcessiveCollision" },
140 { 4, 0x38, "TxPausePkts" },
141 { 8, 0x50, "RxOctets" },
142 { 4, 0x58, "RxUndersizePkts" },
143 { 4, 0x5c, "RxPausePkts" },
144 { 4, 0x60, "Pkts64Octets" },
145 { 4, 0x64, "Pkts65to127Octets" },
146 { 4, 0x68, "Pkts128to255Octets" },
147 { 4, 0x6c, "Pkts256to511Octets" },
148 { 4, 0x70, "Pkts512to1023Octets" },
149 { 4, 0x74, "Pkts1024to1522Octets" },
150 { 4, 0x78, "RxOversizePkts" },
151 { 4, 0x7c, "RxJabbers" },
152 { 4, 0x80, "RxAlignmentErrors" },
153 { 4, 0x84, "RxFCSErrors" },
154 { 8, 0x88, "RxGoodOctets" },
155 { 4, 0x90, "RxDropPkts" },
156 { 4, 0x94, "RxUnicastPkts" },
157 { 4, 0x98, "RxMulticastPkts" },
158 { 4, 0x9c, "RxBroadcastPkts" },
159 { 4, 0xa0, "RxSAChanges" },
160 { 4, 0xa4, "RxFragments" },
161 { 4, 0xa8, "RxJumboPkts" },
162 { 4, 0xac, "RxSymbolErrors" },
163 { 4, 0xc0, "RxDiscarded" },
164 };
165
166 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
167
168 static const struct b53_mib_desc b53_mibs_58xx[] = {
169 { 8, 0x00, "TxOctets" },
170 { 4, 0x08, "TxDropPkts" },
171 { 4, 0x0c, "TxQPKTQ0" },
172 { 4, 0x10, "TxBroadcastPkts" },
173 { 4, 0x14, "TxMulticastPkts" },
174 { 4, 0x18, "TxUnicastPKts" },
175 { 4, 0x1c, "TxCollisions" },
176 { 4, 0x20, "TxSingleCollision" },
177 { 4, 0x24, "TxMultipleCollision" },
178 { 4, 0x28, "TxDeferredCollision" },
179 { 4, 0x2c, "TxLateCollision" },
180 { 4, 0x30, "TxExcessiveCollision" },
181 { 4, 0x34, "TxFrameInDisc" },
182 { 4, 0x38, "TxPausePkts" },
183 { 4, 0x3c, "TxQPKTQ1" },
184 { 4, 0x40, "TxQPKTQ2" },
185 { 4, 0x44, "TxQPKTQ3" },
186 { 4, 0x48, "TxQPKTQ4" },
187 { 4, 0x4c, "TxQPKTQ5" },
188 { 8, 0x50, "RxOctets" },
189 { 4, 0x58, "RxUndersizePkts" },
190 { 4, 0x5c, "RxPausePkts" },
191 { 4, 0x60, "RxPkts64Octets" },
192 { 4, 0x64, "RxPkts65to127Octets" },
193 { 4, 0x68, "RxPkts128to255Octets" },
194 { 4, 0x6c, "RxPkts256to511Octets" },
195 { 4, 0x70, "RxPkts512to1023Octets" },
196 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
197 { 4, 0x78, "RxOversizePkts" },
198 { 4, 0x7c, "RxJabbers" },
199 { 4, 0x80, "RxAlignmentErrors" },
200 { 4, 0x84, "RxFCSErrors" },
201 { 8, 0x88, "RxGoodOctets" },
202 { 4, 0x90, "RxDropPkts" },
203 { 4, 0x94, "RxUnicastPkts" },
204 { 4, 0x98, "RxMulticastPkts" },
205 { 4, 0x9c, "RxBroadcastPkts" },
206 { 4, 0xa0, "RxSAChanges" },
207 { 4, 0xa4, "RxFragments" },
208 { 4, 0xa8, "RxJumboPkt" },
209 { 4, 0xac, "RxSymblErr" },
210 { 4, 0xb0, "InRangeErrCount" },
211 { 4, 0xb4, "OutRangeErrCount" },
212 { 4, 0xb8, "EEELpiEvent" },
213 { 4, 0xbc, "EEELpiDuration" },
214 { 4, 0xc0, "RxDiscard" },
215 { 4, 0xc8, "TxQPKTQ6" },
216 { 4, 0xcc, "TxQPKTQ7" },
217 { 4, 0xd0, "TxPkts64Octets" },
218 { 4, 0xd4, "TxPkts65to127Octets" },
219 { 4, 0xd8, "TxPkts128to255Octets" },
220 { 4, 0xdc, "TxPkts256to511Ocets" },
221 { 4, 0xe0, "TxPkts512to1023Ocets" },
222 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
223 };
224
225 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
226
b53_do_vlan_op(struct b53_device * dev,u8 op)227 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
228 {
229 unsigned int i;
230
231 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
232
233 for (i = 0; i < 10; i++) {
234 u8 vta;
235
236 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
237 if (!(vta & VTA_START_CMD))
238 return 0;
239
240 usleep_range(100, 200);
241 }
242
243 return -EIO;
244 }
245
b53_set_vlan_entry(struct b53_device * dev,u16 vid,struct b53_vlan * vlan)246 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
247 struct b53_vlan *vlan)
248 {
249 if (is5325(dev)) {
250 u32 entry = 0;
251
252 if (vlan->members) {
253 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
254 VA_UNTAG_S_25) | vlan->members;
255 if (dev->core_rev >= 3)
256 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
257 else
258 entry |= VA_VALID_25;
259 }
260
261 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
262 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
263 VTA_RW_STATE_WR | VTA_RW_OP_EN);
264 } else if (is5365(dev)) {
265 u16 entry = 0;
266
267 if (vlan->members)
268 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
269 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
270
271 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
273 VTA_RW_STATE_WR | VTA_RW_OP_EN);
274 } else {
275 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
276 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
277 (vlan->untag << VTE_UNTAG_S) | vlan->members);
278
279 b53_do_vlan_op(dev, VTA_CMD_WRITE);
280 }
281
282 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
283 vid, vlan->members, vlan->untag);
284 }
285
b53_get_vlan_entry(struct b53_device * dev,u16 vid,struct b53_vlan * vlan)286 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
287 struct b53_vlan *vlan)
288 {
289 if (is5325(dev)) {
290 u32 entry = 0;
291
292 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
293 VTA_RW_STATE_RD | VTA_RW_OP_EN);
294 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
295
296 if (dev->core_rev >= 3)
297 vlan->valid = !!(entry & VA_VALID_25_R4);
298 else
299 vlan->valid = !!(entry & VA_VALID_25);
300 vlan->members = entry & VA_MEMBER_MASK;
301 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
302
303 } else if (is5365(dev)) {
304 u16 entry = 0;
305
306 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
307 VTA_RW_STATE_WR | VTA_RW_OP_EN);
308 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
309
310 vlan->valid = !!(entry & VA_VALID_65);
311 vlan->members = entry & VA_MEMBER_MASK;
312 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
313 } else {
314 u32 entry = 0;
315
316 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
317 b53_do_vlan_op(dev, VTA_CMD_READ);
318 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
319 vlan->members = entry & VTE_MEMBERS;
320 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
321 vlan->valid = true;
322 }
323 }
324
b53_set_forwarding(struct b53_device * dev,int enable)325 static void b53_set_forwarding(struct b53_device *dev, int enable)
326 {
327 u8 mgmt;
328
329 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
330
331 if (enable)
332 mgmt |= SM_SW_FWD_EN;
333 else
334 mgmt &= ~SM_SW_FWD_EN;
335
336 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
337
338 /* Include IMP port in dumb forwarding mode
339 */
340 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
341 mgmt |= B53_MII_DUMB_FWDG_EN;
342 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
343
344 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether
345 * frames should be flooded or not.
346 */
347 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt);
348 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN;
349 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt);
350 }
351
b53_enable_vlan(struct b53_device * dev,int port,bool enable,bool enable_filtering)352 static void b53_enable_vlan(struct b53_device *dev, int port, bool enable,
353 bool enable_filtering)
354 {
355 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
356
357 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
358 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
360
361 if (is5325(dev) || is5365(dev)) {
362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
364 } else if (is63xx(dev)) {
365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
367 } else {
368 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
369 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
370 }
371
372 if (enable) {
373 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
374 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
375 vc4 &= ~VC4_ING_VID_CHECK_MASK;
376 if (enable_filtering) {
377 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
378 vc5 |= VC5_DROP_VTABLE_MISS;
379 } else {
380 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
381 vc5 &= ~VC5_DROP_VTABLE_MISS;
382 }
383
384 if (is5325(dev))
385 vc0 &= ~VC0_RESERVED_1;
386
387 if (is5325(dev) || is5365(dev))
388 vc1 |= VC1_RX_MCST_TAG_EN;
389
390 } else {
391 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
392 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
393 vc4 &= ~VC4_ING_VID_CHECK_MASK;
394 vc5 &= ~VC5_DROP_VTABLE_MISS;
395
396 if (is5325(dev) || is5365(dev))
397 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
398 else
399 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
400
401 if (is5325(dev) || is5365(dev))
402 vc1 &= ~VC1_RX_MCST_TAG_EN;
403 }
404
405 if (!is5325(dev) && !is5365(dev))
406 vc5 &= ~VC5_VID_FFF_EN;
407
408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
410
411 if (is5325(dev) || is5365(dev)) {
412 /* enable the high 8 bit vid check on 5325 */
413 if (is5325(dev) && enable)
414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
415 VC3_HIGH_8BIT_EN);
416 else
417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
418
419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
420 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
421 } else if (is63xx(dev)) {
422 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
424 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
425 } else {
426 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
427 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
428 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
429 }
430
431 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
432
433 dev->vlan_enabled = enable;
434
435 dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n",
436 port, enable, enable_filtering);
437 }
438
b53_set_jumbo(struct b53_device * dev,bool enable,bool allow_10_100)439 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
440 {
441 u32 port_mask = 0;
442 u16 max_size = JMS_MIN_SIZE;
443
444 if (is5325(dev) || is5365(dev))
445 return -EINVAL;
446
447 if (enable) {
448 port_mask = dev->enabled_ports;
449 max_size = JMS_MAX_SIZE;
450 if (allow_10_100)
451 port_mask |= JPM_10_100_JUMBO_EN;
452 }
453
454 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
455 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
456 }
457
b53_flush_arl(struct b53_device * dev,u8 mask)458 static int b53_flush_arl(struct b53_device *dev, u8 mask)
459 {
460 unsigned int i;
461
462 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
463 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
464
465 for (i = 0; i < 10; i++) {
466 u8 fast_age_ctrl;
467
468 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
469 &fast_age_ctrl);
470
471 if (!(fast_age_ctrl & FAST_AGE_DONE))
472 goto out;
473
474 msleep(1);
475 }
476
477 return -ETIMEDOUT;
478 out:
479 /* Only age dynamic entries (default behavior) */
480 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
481 return 0;
482 }
483
b53_fast_age_port(struct b53_device * dev,int port)484 static int b53_fast_age_port(struct b53_device *dev, int port)
485 {
486 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
487
488 return b53_flush_arl(dev, FAST_AGE_PORT);
489 }
490
b53_fast_age_vlan(struct b53_device * dev,u16 vid)491 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
492 {
493 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
494
495 return b53_flush_arl(dev, FAST_AGE_VLAN);
496 }
497
b53_imp_vlan_setup(struct dsa_switch * ds,int cpu_port)498 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
499 {
500 struct b53_device *dev = ds->priv;
501 unsigned int i;
502 u16 pvlan;
503
504 /* Enable the IMP port to be in the same VLAN as the other ports
505 * on a per-port basis such that we only have Port i and IMP in
506 * the same VLAN.
507 */
508 b53_for_each_port(dev, i) {
509 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
510 pvlan |= BIT(cpu_port);
511 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
512 }
513 }
514 EXPORT_SYMBOL(b53_imp_vlan_setup);
515
b53_port_set_ucast_flood(struct b53_device * dev,int port,bool unicast)516 static void b53_port_set_ucast_flood(struct b53_device *dev, int port,
517 bool unicast)
518 {
519 u16 uc;
520
521 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc);
522 if (unicast)
523 uc |= BIT(port);
524 else
525 uc &= ~BIT(port);
526 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc);
527 }
528
b53_port_set_mcast_flood(struct b53_device * dev,int port,bool multicast)529 static void b53_port_set_mcast_flood(struct b53_device *dev, int port,
530 bool multicast)
531 {
532 u16 mc;
533
534 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc);
535 if (multicast)
536 mc |= BIT(port);
537 else
538 mc &= ~BIT(port);
539 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc);
540
541 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc);
542 if (multicast)
543 mc |= BIT(port);
544 else
545 mc &= ~BIT(port);
546 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc);
547 }
548
b53_port_set_learning(struct b53_device * dev,int port,bool learning)549 static void b53_port_set_learning(struct b53_device *dev, int port,
550 bool learning)
551 {
552 u16 reg;
553
554 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, ®);
555 if (learning)
556 reg &= ~BIT(port);
557 else
558 reg |= BIT(port);
559 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg);
560 }
561
b53_enable_port(struct dsa_switch * ds,int port,struct phy_device * phy)562 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
563 {
564 struct b53_device *dev = ds->priv;
565 unsigned int cpu_port;
566 int ret = 0;
567 u16 pvlan;
568
569 if (!dsa_is_user_port(ds, port))
570 return 0;
571
572 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
573
574 b53_port_set_ucast_flood(dev, port, true);
575 b53_port_set_mcast_flood(dev, port, true);
576 b53_port_set_learning(dev, port, false);
577
578 if (dev->ops->irq_enable)
579 ret = dev->ops->irq_enable(dev, port);
580 if (ret)
581 return ret;
582
583 /* Clear the Rx and Tx disable bits and set to no spanning tree */
584 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
585
586 /* Set this port, and only this one to be in the default VLAN,
587 * if member of a bridge, restore its membership prior to
588 * bringing down this port.
589 */
590 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
591 pvlan &= ~0x1ff;
592 pvlan |= BIT(port);
593 pvlan |= dev->ports[port].vlan_ctl_mask;
594 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
595
596 b53_imp_vlan_setup(ds, cpu_port);
597
598 /* If EEE was enabled, restore it */
599 if (dev->ports[port].eee.eee_enabled)
600 b53_eee_enable_set(ds, port, true);
601
602 return 0;
603 }
604 EXPORT_SYMBOL(b53_enable_port);
605
b53_disable_port(struct dsa_switch * ds,int port)606 void b53_disable_port(struct dsa_switch *ds, int port)
607 {
608 struct b53_device *dev = ds->priv;
609 u8 reg;
610
611 /* Disable Tx/Rx for the port */
612 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
613 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
614 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
615
616 if (dev->ops->irq_disable)
617 dev->ops->irq_disable(dev, port);
618 }
619 EXPORT_SYMBOL(b53_disable_port);
620
b53_brcm_hdr_setup(struct dsa_switch * ds,int port)621 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
622 {
623 struct b53_device *dev = ds->priv;
624 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE);
625 u8 hdr_ctl, val;
626 u16 reg;
627
628 /* Resolve which bit controls the Broadcom tag */
629 switch (port) {
630 case 8:
631 val = BRCM_HDR_P8_EN;
632 break;
633 case 7:
634 val = BRCM_HDR_P7_EN;
635 break;
636 case 5:
637 val = BRCM_HDR_P5_EN;
638 break;
639 default:
640 val = 0;
641 break;
642 }
643
644 /* Enable management mode if tagging is requested */
645 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl);
646 if (tag_en)
647 hdr_ctl |= SM_SW_FWD_MODE;
648 else
649 hdr_ctl &= ~SM_SW_FWD_MODE;
650 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl);
651
652 /* Configure the appropriate IMP port */
653 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl);
654 if (port == 8)
655 hdr_ctl |= GC_FRM_MGMT_PORT_MII;
656 else if (port == 5)
657 hdr_ctl |= GC_FRM_MGMT_PORT_M;
658 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl);
659
660 /* Enable Broadcom tags for IMP port */
661 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
662 if (tag_en)
663 hdr_ctl |= val;
664 else
665 hdr_ctl &= ~val;
666 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
667
668 /* Registers below are only accessible on newer devices */
669 if (!is58xx(dev))
670 return;
671
672 /* Enable reception Broadcom tag for CPU TX (switch RX) to
673 * allow us to tag outgoing frames
674 */
675 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®);
676 if (tag_en)
677 reg &= ~BIT(port);
678 else
679 reg |= BIT(port);
680 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
681
682 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
683 * allow delivering frames to the per-port net_devices
684 */
685 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®);
686 if (tag_en)
687 reg &= ~BIT(port);
688 else
689 reg |= BIT(port);
690 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
691 }
692 EXPORT_SYMBOL(b53_brcm_hdr_setup);
693
b53_enable_cpu_port(struct b53_device * dev,int port)694 static void b53_enable_cpu_port(struct b53_device *dev, int port)
695 {
696 u8 port_ctrl;
697
698 /* BCM5325 CPU port is at 8 */
699 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
700 port = B53_CPU_PORT;
701
702 port_ctrl = PORT_CTRL_RX_BCST_EN |
703 PORT_CTRL_RX_MCST_EN |
704 PORT_CTRL_RX_UCST_EN;
705 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
706
707 b53_brcm_hdr_setup(dev->ds, port);
708
709 b53_port_set_ucast_flood(dev, port, true);
710 b53_port_set_mcast_flood(dev, port, true);
711 b53_port_set_learning(dev, port, false);
712 }
713
b53_enable_mib(struct b53_device * dev)714 static void b53_enable_mib(struct b53_device *dev)
715 {
716 u8 gc;
717
718 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
719 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
720 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
721 }
722
b53_default_pvid(struct b53_device * dev)723 static u16 b53_default_pvid(struct b53_device *dev)
724 {
725 if (is5325(dev) || is5365(dev))
726 return 1;
727 else
728 return 0;
729 }
730
b53_vlan_port_needs_forced_tagged(struct dsa_switch * ds,int port)731 static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port)
732 {
733 struct b53_device *dev = ds->priv;
734
735 return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port);
736 }
737
b53_configure_vlan(struct dsa_switch * ds)738 int b53_configure_vlan(struct dsa_switch *ds)
739 {
740 struct b53_device *dev = ds->priv;
741 struct b53_vlan vl = { 0 };
742 struct b53_vlan *v;
743 int i, def_vid;
744 u16 vid;
745
746 def_vid = b53_default_pvid(dev);
747
748 /* clear all vlan entries */
749 if (is5325(dev) || is5365(dev)) {
750 for (i = def_vid; i < dev->num_vlans; i++)
751 b53_set_vlan_entry(dev, i, &vl);
752 } else {
753 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
754 }
755
756 b53_enable_vlan(dev, -1, dev->vlan_enabled, ds->vlan_filtering);
757
758 /* Create an untagged VLAN entry for the default PVID in case
759 * CONFIG_VLAN_8021Q is disabled and there are no calls to
760 * dsa_slave_vlan_rx_add_vid() to create the default VLAN
761 * entry. Do this only when the tagging protocol is not
762 * DSA_TAG_PROTO_NONE
763 */
764 b53_for_each_port(dev, i) {
765 v = &dev->vlans[def_vid];
766 v->members |= BIT(i);
767 if (!b53_vlan_port_needs_forced_tagged(ds, i))
768 v->untag = v->members;
769 b53_write16(dev, B53_VLAN_PAGE,
770 B53_VLAN_PORT_DEF_TAG(i), def_vid);
771 }
772
773 /* Upon initial call we have not set-up any VLANs, but upon
774 * system resume, we need to restore all VLAN entries.
775 */
776 for (vid = def_vid; vid < dev->num_vlans; vid++) {
777 v = &dev->vlans[vid];
778
779 if (!v->members)
780 continue;
781
782 b53_set_vlan_entry(dev, vid, v);
783 b53_fast_age_vlan(dev, vid);
784 }
785
786 return 0;
787 }
788 EXPORT_SYMBOL(b53_configure_vlan);
789
b53_switch_reset_gpio(struct b53_device * dev)790 static void b53_switch_reset_gpio(struct b53_device *dev)
791 {
792 int gpio = dev->reset_gpio;
793
794 if (gpio < 0)
795 return;
796
797 /* Reset sequence: RESET low(50ms)->high(20ms)
798 */
799 gpio_set_value(gpio, 0);
800 mdelay(50);
801
802 gpio_set_value(gpio, 1);
803 mdelay(20);
804
805 dev->current_page = 0xff;
806 }
807
b53_switch_reset(struct b53_device * dev)808 static int b53_switch_reset(struct b53_device *dev)
809 {
810 unsigned int timeout = 1000;
811 u8 mgmt, reg;
812
813 b53_switch_reset_gpio(dev);
814
815 if (is539x(dev)) {
816 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
817 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
818 }
819
820 /* This is specific to 58xx devices here, do not use is58xx() which
821 * covers the larger Starfigther 2 family, including 7445/7278 which
822 * still use this driver as a library and need to perform the reset
823 * earlier.
824 */
825 if (dev->chip_id == BCM58XX_DEVICE_ID ||
826 dev->chip_id == BCM583XX_DEVICE_ID) {
827 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
828 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
829 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
830
831 do {
832 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
833 if (!(reg & SW_RST))
834 break;
835
836 usleep_range(1000, 2000);
837 } while (timeout-- > 0);
838
839 if (timeout == 0) {
840 dev_err(dev->dev,
841 "Timeout waiting for SW_RST to clear!\n");
842 return -ETIMEDOUT;
843 }
844 }
845
846 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
847
848 if (!(mgmt & SM_SW_FWD_EN)) {
849 mgmt &= ~SM_SW_FWD_MODE;
850 mgmt |= SM_SW_FWD_EN;
851
852 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
853 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
854
855 if (!(mgmt & SM_SW_FWD_EN)) {
856 dev_err(dev->dev, "Failed to enable switch!\n");
857 return -EINVAL;
858 }
859 }
860
861 b53_enable_mib(dev);
862
863 return b53_flush_arl(dev, FAST_AGE_STATIC);
864 }
865
b53_phy_read16(struct dsa_switch * ds,int addr,int reg)866 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
867 {
868 struct b53_device *priv = ds->priv;
869 u16 value = 0;
870 int ret;
871
872 if (priv->ops->phy_read16)
873 ret = priv->ops->phy_read16(priv, addr, reg, &value);
874 else
875 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
876 reg * 2, &value);
877
878 return ret ? ret : value;
879 }
880
b53_phy_write16(struct dsa_switch * ds,int addr,int reg,u16 val)881 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
882 {
883 struct b53_device *priv = ds->priv;
884
885 if (priv->ops->phy_write16)
886 return priv->ops->phy_write16(priv, addr, reg, val);
887
888 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
889 }
890
b53_reset_switch(struct b53_device * priv)891 static int b53_reset_switch(struct b53_device *priv)
892 {
893 /* reset vlans */
894 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
895 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
896
897 priv->serdes_lane = B53_INVALID_LANE;
898
899 return b53_switch_reset(priv);
900 }
901
b53_apply_config(struct b53_device * priv)902 static int b53_apply_config(struct b53_device *priv)
903 {
904 /* disable switching */
905 b53_set_forwarding(priv, 0);
906
907 b53_configure_vlan(priv->ds);
908
909 /* enable switching */
910 b53_set_forwarding(priv, 1);
911
912 return 0;
913 }
914
b53_reset_mib(struct b53_device * priv)915 static void b53_reset_mib(struct b53_device *priv)
916 {
917 u8 gc;
918
919 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
920
921 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
922 msleep(1);
923 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
924 msleep(1);
925 }
926
b53_get_mib(struct b53_device * dev)927 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
928 {
929 if (is5365(dev))
930 return b53_mibs_65;
931 else if (is63xx(dev))
932 return b53_mibs_63xx;
933 else if (is58xx(dev))
934 return b53_mibs_58xx;
935 else
936 return b53_mibs;
937 }
938
b53_get_mib_size(struct b53_device * dev)939 static unsigned int b53_get_mib_size(struct b53_device *dev)
940 {
941 if (is5365(dev))
942 return B53_MIBS_65_SIZE;
943 else if (is63xx(dev))
944 return B53_MIBS_63XX_SIZE;
945 else if (is58xx(dev))
946 return B53_MIBS_58XX_SIZE;
947 else
948 return B53_MIBS_SIZE;
949 }
950
b53_get_phy_device(struct dsa_switch * ds,int port)951 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port)
952 {
953 /* These ports typically do not have built-in PHYs */
954 switch (port) {
955 case B53_CPU_PORT_25:
956 case 7:
957 case B53_CPU_PORT:
958 return NULL;
959 }
960
961 return mdiobus_get_phy(ds->slave_mii_bus, port);
962 }
963
b53_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)964 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset,
965 uint8_t *data)
966 {
967 struct b53_device *dev = ds->priv;
968 const struct b53_mib_desc *mibs = b53_get_mib(dev);
969 unsigned int mib_size = b53_get_mib_size(dev);
970 struct phy_device *phydev;
971 unsigned int i;
972
973 if (stringset == ETH_SS_STATS) {
974 for (i = 0; i < mib_size; i++)
975 strscpy(data + i * ETH_GSTRING_LEN,
976 mibs[i].name, ETH_GSTRING_LEN);
977 } else if (stringset == ETH_SS_PHY_STATS) {
978 phydev = b53_get_phy_device(ds, port);
979 if (!phydev)
980 return;
981
982 phy_ethtool_get_strings(phydev, data);
983 }
984 }
985 EXPORT_SYMBOL(b53_get_strings);
986
b53_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)987 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
988 {
989 struct b53_device *dev = ds->priv;
990 const struct b53_mib_desc *mibs = b53_get_mib(dev);
991 unsigned int mib_size = b53_get_mib_size(dev);
992 const struct b53_mib_desc *s;
993 unsigned int i;
994 u64 val = 0;
995
996 if (is5365(dev) && port == 5)
997 port = 8;
998
999 mutex_lock(&dev->stats_mutex);
1000
1001 for (i = 0; i < mib_size; i++) {
1002 s = &mibs[i];
1003
1004 if (s->size == 8) {
1005 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
1006 } else {
1007 u32 val32;
1008
1009 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
1010 &val32);
1011 val = val32;
1012 }
1013 data[i] = (u64)val;
1014 }
1015
1016 mutex_unlock(&dev->stats_mutex);
1017 }
1018 EXPORT_SYMBOL(b53_get_ethtool_stats);
1019
b53_get_ethtool_phy_stats(struct dsa_switch * ds,int port,uint64_t * data)1020 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data)
1021 {
1022 struct phy_device *phydev;
1023
1024 phydev = b53_get_phy_device(ds, port);
1025 if (!phydev)
1026 return;
1027
1028 phy_ethtool_get_stats(phydev, NULL, data);
1029 }
1030 EXPORT_SYMBOL(b53_get_ethtool_phy_stats);
1031
b53_get_sset_count(struct dsa_switch * ds,int port,int sset)1032 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset)
1033 {
1034 struct b53_device *dev = ds->priv;
1035 struct phy_device *phydev;
1036
1037 if (sset == ETH_SS_STATS) {
1038 return b53_get_mib_size(dev);
1039 } else if (sset == ETH_SS_PHY_STATS) {
1040 phydev = b53_get_phy_device(ds, port);
1041 if (!phydev)
1042 return 0;
1043
1044 return phy_ethtool_get_sset_count(phydev);
1045 }
1046
1047 return 0;
1048 }
1049 EXPORT_SYMBOL(b53_get_sset_count);
1050
1051 enum b53_devlink_resource_id {
1052 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1053 };
1054
b53_devlink_vlan_table_get(void * priv)1055 static u64 b53_devlink_vlan_table_get(void *priv)
1056 {
1057 struct b53_device *dev = priv;
1058 struct b53_vlan *vl;
1059 unsigned int i;
1060 u64 count = 0;
1061
1062 for (i = 0; i < dev->num_vlans; i++) {
1063 vl = &dev->vlans[i];
1064 if (vl->members)
1065 count++;
1066 }
1067
1068 return count;
1069 }
1070
b53_setup_devlink_resources(struct dsa_switch * ds)1071 int b53_setup_devlink_resources(struct dsa_switch *ds)
1072 {
1073 struct devlink_resource_size_params size_params;
1074 struct b53_device *dev = ds->priv;
1075 int err;
1076
1077 devlink_resource_size_params_init(&size_params, dev->num_vlans,
1078 dev->num_vlans,
1079 1, DEVLINK_RESOURCE_UNIT_ENTRY);
1080
1081 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans,
1082 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1083 DEVLINK_RESOURCE_ID_PARENT_TOP,
1084 &size_params);
1085 if (err)
1086 goto out;
1087
1088 dsa_devlink_resource_occ_get_register(ds,
1089 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1090 b53_devlink_vlan_table_get, dev);
1091
1092 return 0;
1093 out:
1094 dsa_devlink_resources_unregister(ds);
1095 return err;
1096 }
1097 EXPORT_SYMBOL(b53_setup_devlink_resources);
1098
b53_setup(struct dsa_switch * ds)1099 static int b53_setup(struct dsa_switch *ds)
1100 {
1101 struct b53_device *dev = ds->priv;
1102 unsigned int port;
1103 int ret;
1104
1105 /* Request bridge PVID untagged when DSA_TAG_PROTO_NONE is set
1106 * which forces the CPU port to be tagged in all VLANs.
1107 */
1108 ds->untag_bridge_pvid = dev->tag_protocol == DSA_TAG_PROTO_NONE;
1109
1110 ret = b53_reset_switch(dev);
1111 if (ret) {
1112 dev_err(ds->dev, "failed to reset switch\n");
1113 return ret;
1114 }
1115
1116 b53_reset_mib(dev);
1117
1118 ret = b53_apply_config(dev);
1119 if (ret) {
1120 dev_err(ds->dev, "failed to apply configuration\n");
1121 return ret;
1122 }
1123
1124 /* Configure IMP/CPU port, disable all other ports. Enabled
1125 * ports will be configured with .port_enable
1126 */
1127 for (port = 0; port < dev->num_ports; port++) {
1128 if (dsa_is_cpu_port(ds, port))
1129 b53_enable_cpu_port(dev, port);
1130 else
1131 b53_disable_port(ds, port);
1132 }
1133
1134 return b53_setup_devlink_resources(ds);
1135 }
1136
b53_teardown(struct dsa_switch * ds)1137 static void b53_teardown(struct dsa_switch *ds)
1138 {
1139 dsa_devlink_resources_unregister(ds);
1140 }
1141
b53_force_link(struct b53_device * dev,int port,int link)1142 static void b53_force_link(struct b53_device *dev, int port, int link)
1143 {
1144 u8 reg, val, off;
1145
1146 /* Override the port settings */
1147 if (port == dev->imp_port) {
1148 off = B53_PORT_OVERRIDE_CTRL;
1149 val = PORT_OVERRIDE_EN;
1150 } else {
1151 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1152 val = GMII_PO_EN;
1153 }
1154
1155 b53_read8(dev, B53_CTRL_PAGE, off, ®);
1156 reg |= val;
1157 if (link)
1158 reg |= PORT_OVERRIDE_LINK;
1159 else
1160 reg &= ~PORT_OVERRIDE_LINK;
1161 b53_write8(dev, B53_CTRL_PAGE, off, reg);
1162 }
1163
b53_force_port_config(struct b53_device * dev,int port,int speed,int duplex,bool tx_pause,bool rx_pause)1164 static void b53_force_port_config(struct b53_device *dev, int port,
1165 int speed, int duplex,
1166 bool tx_pause, bool rx_pause)
1167 {
1168 u8 reg, val, off;
1169
1170 /* Override the port settings */
1171 if (port == dev->imp_port) {
1172 off = B53_PORT_OVERRIDE_CTRL;
1173 val = PORT_OVERRIDE_EN;
1174 } else {
1175 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1176 val = GMII_PO_EN;
1177 }
1178
1179 b53_read8(dev, B53_CTRL_PAGE, off, ®);
1180 reg |= val;
1181 if (duplex == DUPLEX_FULL)
1182 reg |= PORT_OVERRIDE_FULL_DUPLEX;
1183 else
1184 reg &= ~PORT_OVERRIDE_FULL_DUPLEX;
1185
1186 switch (speed) {
1187 case 2000:
1188 reg |= PORT_OVERRIDE_SPEED_2000M;
1189 fallthrough;
1190 case SPEED_1000:
1191 reg |= PORT_OVERRIDE_SPEED_1000M;
1192 break;
1193 case SPEED_100:
1194 reg |= PORT_OVERRIDE_SPEED_100M;
1195 break;
1196 case SPEED_10:
1197 reg |= PORT_OVERRIDE_SPEED_10M;
1198 break;
1199 default:
1200 dev_err(dev->dev, "unknown speed: %d\n", speed);
1201 return;
1202 }
1203
1204 if (rx_pause)
1205 reg |= PORT_OVERRIDE_RX_FLOW;
1206 if (tx_pause)
1207 reg |= PORT_OVERRIDE_TX_FLOW;
1208
1209 b53_write8(dev, B53_CTRL_PAGE, off, reg);
1210 }
1211
b53_adjust_63xx_rgmii(struct dsa_switch * ds,int port,phy_interface_t interface)1212 static void b53_adjust_63xx_rgmii(struct dsa_switch *ds, int port,
1213 phy_interface_t interface)
1214 {
1215 struct b53_device *dev = ds->priv;
1216 u8 rgmii_ctrl = 0, off;
1217
1218 if (port == dev->imp_port)
1219 off = B53_RGMII_CTRL_IMP;
1220 else
1221 off = B53_RGMII_CTRL_P(port);
1222
1223 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1224
1225 switch (interface) {
1226 case PHY_INTERFACE_MODE_RGMII_ID:
1227 rgmii_ctrl |= (RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC);
1228 break;
1229 case PHY_INTERFACE_MODE_RGMII_RXID:
1230 rgmii_ctrl &= ~(RGMII_CTRL_DLL_TXC);
1231 rgmii_ctrl |= RGMII_CTRL_DLL_RXC;
1232 break;
1233 case PHY_INTERFACE_MODE_RGMII_TXID:
1234 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC);
1235 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1236 break;
1237 case PHY_INTERFACE_MODE_RGMII:
1238 default:
1239 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC);
1240 break;
1241 }
1242
1243 if (port != dev->imp_port) {
1244 if (is63268(dev))
1245 rgmii_ctrl |= RGMII_CTRL_MII_OVERRIDE;
1246
1247 rgmii_ctrl |= RGMII_CTRL_ENABLE_GMII;
1248 }
1249
1250 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1251
1252 dev_dbg(ds->dev, "Configured port %d for %s\n", port,
1253 phy_modes(interface));
1254 }
1255
b53_adjust_link(struct dsa_switch * ds,int port,struct phy_device * phydev)1256 static void b53_adjust_link(struct dsa_switch *ds, int port,
1257 struct phy_device *phydev)
1258 {
1259 struct b53_device *dev = ds->priv;
1260 struct ethtool_eee *p = &dev->ports[port].eee;
1261 u8 rgmii_ctrl = 0, reg = 0, off;
1262 bool tx_pause = false;
1263 bool rx_pause = false;
1264
1265 if (!phy_is_pseudo_fixed_link(phydev))
1266 return;
1267
1268 /* Enable flow control on BCM5301x's CPU port */
1269 if (is5301x(dev) && dsa_is_cpu_port(ds, port))
1270 tx_pause = rx_pause = true;
1271
1272 if (phydev->pause) {
1273 if (phydev->asym_pause)
1274 tx_pause = true;
1275 rx_pause = true;
1276 }
1277
1278 b53_force_port_config(dev, port, phydev->speed, phydev->duplex,
1279 tx_pause, rx_pause);
1280 b53_force_link(dev, port, phydev->link);
1281
1282 if (is63xx(dev) && port >= B53_63XX_RGMII0)
1283 b53_adjust_63xx_rgmii(ds, port, phydev->interface);
1284
1285 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
1286 if (port == dev->imp_port)
1287 off = B53_RGMII_CTRL_IMP;
1288 else
1289 off = B53_RGMII_CTRL_P(port);
1290
1291 /* Configure the port RGMII clock delay by DLL disabled and
1292 * tx_clk aligned timing (restoring to reset defaults)
1293 */
1294 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1295 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
1296 RGMII_CTRL_TIMING_SEL);
1297
1298 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
1299 * sure that we enable the port TX clock internal delay to
1300 * account for this internal delay that is inserted, otherwise
1301 * the switch won't be able to receive correctly.
1302 *
1303 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
1304 * any delay neither on transmission nor reception, so the
1305 * BCM53125 must also be configured accordingly to account for
1306 * the lack of delay and introduce
1307 *
1308 * The BCM53125 switch has its RX clock and TX clock control
1309 * swapped, hence the reason why we modify the TX clock path in
1310 * the "RGMII" case
1311 */
1312 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1313 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1314 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1315 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
1316 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1317 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1318
1319 dev_info(ds->dev, "Configured port %d for %s\n", port,
1320 phy_modes(phydev->interface));
1321 }
1322
1323 /* configure MII port if necessary */
1324 if (is5325(dev)) {
1325 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1326 ®);
1327
1328 /* reverse mii needs to be enabled */
1329 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1330 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1331 reg | PORT_OVERRIDE_RV_MII_25);
1332 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1333 ®);
1334
1335 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1336 dev_err(ds->dev,
1337 "Failed to enable reverse MII mode\n");
1338 return;
1339 }
1340 }
1341 }
1342
1343 /* Re-negotiate EEE if it was enabled already */
1344 p->eee_enabled = b53_eee_init(ds, port, phydev);
1345 }
1346
b53_port_event(struct dsa_switch * ds,int port)1347 void b53_port_event(struct dsa_switch *ds, int port)
1348 {
1349 struct b53_device *dev = ds->priv;
1350 bool link;
1351 u16 sts;
1352
1353 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts);
1354 link = !!(sts & BIT(port));
1355 dsa_port_phylink_mac_change(ds, port, link);
1356 }
1357 EXPORT_SYMBOL(b53_port_event);
1358
b53_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)1359 static void b53_phylink_get_caps(struct dsa_switch *ds, int port,
1360 struct phylink_config *config)
1361 {
1362 struct b53_device *dev = ds->priv;
1363
1364 /* Internal ports need GMII for PHYLIB */
1365 __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces);
1366
1367 /* These switches appear to support MII and RevMII too, but beyond
1368 * this, the code gives very few clues. FIXME: We probably need more
1369 * interface modes here.
1370 *
1371 * According to b53_srab_mux_init(), ports 3..5 can support:
1372 * SGMII, MII, GMII, RGMII or INTERNAL depending on the MUX setting.
1373 * However, the interface mode read from the MUX configuration is
1374 * not passed back to DSA, so phylink uses NA.
1375 * DT can specify RGMII for ports 0, 1.
1376 * For MDIO, port 8 can be RGMII_TXID.
1377 */
1378 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1379 __set_bit(PHY_INTERFACE_MODE_REVMII, config->supported_interfaces);
1380
1381 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1382 MAC_10 | MAC_100;
1383
1384 /* 5325/5365 are not capable of gigabit speeds, everything else is.
1385 * Note: the original code also exclulded Gigagbit for MII, RevMII
1386 * and 802.3z modes. MII and RevMII are not able to work above 100M,
1387 * so will be excluded by the generic validator implementation.
1388 * However, the exclusion of Gigabit for 802.3z just seems wrong.
1389 */
1390 if (!(is5325(dev) || is5365(dev)))
1391 config->mac_capabilities |= MAC_1000;
1392
1393 /* Get the implementation specific capabilities */
1394 if (dev->ops->phylink_get_caps)
1395 dev->ops->phylink_get_caps(dev, port, config);
1396 }
1397
b53_phylink_mac_select_pcs(struct dsa_switch * ds,int port,phy_interface_t interface)1398 static struct phylink_pcs *b53_phylink_mac_select_pcs(struct dsa_switch *ds,
1399 int port,
1400 phy_interface_t interface)
1401 {
1402 struct b53_device *dev = ds->priv;
1403
1404 if (!dev->ops->phylink_mac_select_pcs)
1405 return NULL;
1406
1407 return dev->ops->phylink_mac_select_pcs(dev, port, interface);
1408 }
1409
b53_phylink_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)1410 void b53_phylink_mac_config(struct dsa_switch *ds, int port,
1411 unsigned int mode,
1412 const struct phylink_link_state *state)
1413 {
1414 }
1415 EXPORT_SYMBOL(b53_phylink_mac_config);
1416
b53_phylink_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)1417 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port,
1418 unsigned int mode,
1419 phy_interface_t interface)
1420 {
1421 struct b53_device *dev = ds->priv;
1422
1423 if (mode == MLO_AN_PHY)
1424 return;
1425
1426 if (mode == MLO_AN_FIXED) {
1427 b53_force_link(dev, port, false);
1428 return;
1429 }
1430
1431 if (phy_interface_mode_is_8023z(interface) &&
1432 dev->ops->serdes_link_set)
1433 dev->ops->serdes_link_set(dev, port, mode, interface, false);
1434 }
1435 EXPORT_SYMBOL(b53_phylink_mac_link_down);
1436
b53_phylink_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)1437 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port,
1438 unsigned int mode,
1439 phy_interface_t interface,
1440 struct phy_device *phydev,
1441 int speed, int duplex,
1442 bool tx_pause, bool rx_pause)
1443 {
1444 struct b53_device *dev = ds->priv;
1445
1446 if (is63xx(dev) && port >= B53_63XX_RGMII0)
1447 b53_adjust_63xx_rgmii(ds, port, interface);
1448
1449 if (mode == MLO_AN_PHY)
1450 return;
1451
1452 if (mode == MLO_AN_FIXED) {
1453 b53_force_port_config(dev, port, speed, duplex,
1454 tx_pause, rx_pause);
1455 b53_force_link(dev, port, true);
1456 return;
1457 }
1458
1459 if (phy_interface_mode_is_8023z(interface) &&
1460 dev->ops->serdes_link_set)
1461 dev->ops->serdes_link_set(dev, port, mode, interface, true);
1462 }
1463 EXPORT_SYMBOL(b53_phylink_mac_link_up);
1464
b53_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)1465 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1466 struct netlink_ext_ack *extack)
1467 {
1468 struct b53_device *dev = ds->priv;
1469
1470 b53_enable_vlan(dev, port, dev->vlan_enabled, vlan_filtering);
1471
1472 return 0;
1473 }
1474 EXPORT_SYMBOL(b53_vlan_filtering);
1475
b53_vlan_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1476 static int b53_vlan_prepare(struct dsa_switch *ds, int port,
1477 const struct switchdev_obj_port_vlan *vlan)
1478 {
1479 struct b53_device *dev = ds->priv;
1480
1481 if ((is5325(dev) || is5365(dev)) && vlan->vid == 0)
1482 return -EOPNOTSUPP;
1483
1484 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of
1485 * receiving VLAN tagged frames at all, we can still allow the port to
1486 * be configured for egress untagged.
1487 */
1488 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 &&
1489 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED))
1490 return -EINVAL;
1491
1492 if (vlan->vid >= dev->num_vlans)
1493 return -ERANGE;
1494
1495 b53_enable_vlan(dev, port, true, ds->vlan_filtering);
1496
1497 return 0;
1498 }
1499
b53_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)1500 int b53_vlan_add(struct dsa_switch *ds, int port,
1501 const struct switchdev_obj_port_vlan *vlan,
1502 struct netlink_ext_ack *extack)
1503 {
1504 struct b53_device *dev = ds->priv;
1505 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1506 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1507 struct b53_vlan *vl;
1508 int err;
1509
1510 err = b53_vlan_prepare(ds, port, vlan);
1511 if (err)
1512 return err;
1513
1514 vl = &dev->vlans[vlan->vid];
1515
1516 b53_get_vlan_entry(dev, vlan->vid, vl);
1517
1518 if (vlan->vid == 0 && vlan->vid == b53_default_pvid(dev))
1519 untagged = true;
1520
1521 vl->members |= BIT(port);
1522 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port))
1523 vl->untag |= BIT(port);
1524 else
1525 vl->untag &= ~BIT(port);
1526
1527 b53_set_vlan_entry(dev, vlan->vid, vl);
1528 b53_fast_age_vlan(dev, vlan->vid);
1529
1530 if (pvid && !dsa_is_cpu_port(ds, port)) {
1531 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1532 vlan->vid);
1533 b53_fast_age_vlan(dev, vlan->vid);
1534 }
1535
1536 return 0;
1537 }
1538 EXPORT_SYMBOL(b53_vlan_add);
1539
b53_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1540 int b53_vlan_del(struct dsa_switch *ds, int port,
1541 const struct switchdev_obj_port_vlan *vlan)
1542 {
1543 struct b53_device *dev = ds->priv;
1544 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1545 struct b53_vlan *vl;
1546 u16 pvid;
1547
1548 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1549
1550 vl = &dev->vlans[vlan->vid];
1551
1552 b53_get_vlan_entry(dev, vlan->vid, vl);
1553
1554 vl->members &= ~BIT(port);
1555
1556 if (pvid == vlan->vid)
1557 pvid = b53_default_pvid(dev);
1558
1559 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port))
1560 vl->untag &= ~(BIT(port));
1561
1562 b53_set_vlan_entry(dev, vlan->vid, vl);
1563 b53_fast_age_vlan(dev, vlan->vid);
1564
1565 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1566 b53_fast_age_vlan(dev, pvid);
1567
1568 return 0;
1569 }
1570 EXPORT_SYMBOL(b53_vlan_del);
1571
1572 /* Address Resolution Logic routines. Caller must hold &dev->arl_mutex. */
b53_arl_op_wait(struct b53_device * dev)1573 static int b53_arl_op_wait(struct b53_device *dev)
1574 {
1575 unsigned int timeout = 10;
1576 u8 reg;
1577
1578 do {
1579 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1580 if (!(reg & ARLTBL_START_DONE))
1581 return 0;
1582
1583 usleep_range(1000, 2000);
1584 } while (timeout--);
1585
1586 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1587
1588 return -ETIMEDOUT;
1589 }
1590
b53_arl_rw_op(struct b53_device * dev,unsigned int op)1591 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1592 {
1593 u8 reg;
1594
1595 if (op > ARLTBL_RW)
1596 return -EINVAL;
1597
1598 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1599 reg |= ARLTBL_START_DONE;
1600 if (op)
1601 reg |= ARLTBL_RW;
1602 else
1603 reg &= ~ARLTBL_RW;
1604 if (dev->vlan_enabled)
1605 reg &= ~ARLTBL_IVL_SVL_SELECT;
1606 else
1607 reg |= ARLTBL_IVL_SVL_SELECT;
1608 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1609
1610 return b53_arl_op_wait(dev);
1611 }
1612
b53_arl_read(struct b53_device * dev,u64 mac,u16 vid,struct b53_arl_entry * ent,u8 * idx)1613 static int b53_arl_read(struct b53_device *dev, u64 mac,
1614 u16 vid, struct b53_arl_entry *ent, u8 *idx)
1615 {
1616 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES);
1617 unsigned int i;
1618 int ret;
1619
1620 ret = b53_arl_op_wait(dev);
1621 if (ret)
1622 return ret;
1623
1624 bitmap_zero(free_bins, dev->num_arl_bins);
1625
1626 /* Read the bins */
1627 for (i = 0; i < dev->num_arl_bins; i++) {
1628 u64 mac_vid;
1629 u32 fwd_entry;
1630
1631 b53_read64(dev, B53_ARLIO_PAGE,
1632 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1633 b53_read32(dev, B53_ARLIO_PAGE,
1634 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1635 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1636
1637 if (!(fwd_entry & ARLTBL_VALID)) {
1638 set_bit(i, free_bins);
1639 continue;
1640 }
1641 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1642 continue;
1643 if (dev->vlan_enabled &&
1644 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid)
1645 continue;
1646 *idx = i;
1647 return 0;
1648 }
1649
1650 *idx = find_first_bit(free_bins, dev->num_arl_bins);
1651 return *idx >= dev->num_arl_bins ? -ENOSPC : -ENOENT;
1652 }
1653
b53_arl_op(struct b53_device * dev,int op,int port,const unsigned char * addr,u16 vid,bool is_valid)1654 static int b53_arl_op(struct b53_device *dev, int op, int port,
1655 const unsigned char *addr, u16 vid, bool is_valid)
1656 {
1657 struct b53_arl_entry ent;
1658 u32 fwd_entry;
1659 u64 mac, mac_vid = 0;
1660 u8 idx = 0;
1661 int ret;
1662
1663 /* Convert the array into a 64-bit MAC */
1664 mac = ether_addr_to_u64(addr);
1665
1666 /* Perform a read for the given MAC and VID */
1667 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1668 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1669
1670 /* Issue a read operation for this MAC */
1671 ret = b53_arl_rw_op(dev, 1);
1672 if (ret)
1673 return ret;
1674
1675 ret = b53_arl_read(dev, mac, vid, &ent, &idx);
1676
1677 /* If this is a read, just finish now */
1678 if (op)
1679 return ret;
1680
1681 switch (ret) {
1682 case -ETIMEDOUT:
1683 return ret;
1684 case -ENOSPC:
1685 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n",
1686 addr, vid);
1687 return is_valid ? ret : 0;
1688 case -ENOENT:
1689 /* We could not find a matching MAC, so reset to a new entry */
1690 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n",
1691 addr, vid, idx);
1692 fwd_entry = 0;
1693 break;
1694 default:
1695 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n",
1696 addr, vid, idx);
1697 break;
1698 }
1699
1700 /* For multicast address, the port is a bitmask and the validity
1701 * is determined by having at least one port being still active
1702 */
1703 if (!is_multicast_ether_addr(addr)) {
1704 ent.port = port;
1705 ent.is_valid = is_valid;
1706 } else {
1707 if (is_valid)
1708 ent.port |= BIT(port);
1709 else
1710 ent.port &= ~BIT(port);
1711
1712 ent.is_valid = !!(ent.port);
1713 }
1714
1715 ent.vid = vid;
1716 ent.is_static = true;
1717 ent.is_age = false;
1718 memcpy(ent.mac, addr, ETH_ALEN);
1719 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1720
1721 b53_write64(dev, B53_ARLIO_PAGE,
1722 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1723 b53_write32(dev, B53_ARLIO_PAGE,
1724 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1725
1726 return b53_arl_rw_op(dev, 0);
1727 }
1728
b53_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1729 int b53_fdb_add(struct dsa_switch *ds, int port,
1730 const unsigned char *addr, u16 vid,
1731 struct dsa_db db)
1732 {
1733 struct b53_device *priv = ds->priv;
1734 int ret;
1735
1736 /* 5325 and 5365 require some more massaging, but could
1737 * be supported eventually
1738 */
1739 if (is5325(priv) || is5365(priv))
1740 return -EOPNOTSUPP;
1741
1742 mutex_lock(&priv->arl_mutex);
1743 ret = b53_arl_op(priv, 0, port, addr, vid, true);
1744 mutex_unlock(&priv->arl_mutex);
1745
1746 return ret;
1747 }
1748 EXPORT_SYMBOL(b53_fdb_add);
1749
b53_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1750 int b53_fdb_del(struct dsa_switch *ds, int port,
1751 const unsigned char *addr, u16 vid,
1752 struct dsa_db db)
1753 {
1754 struct b53_device *priv = ds->priv;
1755 int ret;
1756
1757 mutex_lock(&priv->arl_mutex);
1758 ret = b53_arl_op(priv, 0, port, addr, vid, false);
1759 mutex_unlock(&priv->arl_mutex);
1760
1761 return ret;
1762 }
1763 EXPORT_SYMBOL(b53_fdb_del);
1764
b53_arl_search_wait(struct b53_device * dev)1765 static int b53_arl_search_wait(struct b53_device *dev)
1766 {
1767 unsigned int timeout = 1000;
1768 u8 reg;
1769
1770 do {
1771 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®);
1772 if (!(reg & ARL_SRCH_STDN))
1773 return 0;
1774
1775 if (reg & ARL_SRCH_VLID)
1776 return 0;
1777
1778 usleep_range(1000, 2000);
1779 } while (timeout--);
1780
1781 return -ETIMEDOUT;
1782 }
1783
b53_arl_search_rd(struct b53_device * dev,u8 idx,struct b53_arl_entry * ent)1784 static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1785 struct b53_arl_entry *ent)
1786 {
1787 u64 mac_vid;
1788 u32 fwd_entry;
1789
1790 b53_read64(dev, B53_ARLIO_PAGE,
1791 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1792 b53_read32(dev, B53_ARLIO_PAGE,
1793 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1794 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1795 }
1796
b53_fdb_copy(int port,const struct b53_arl_entry * ent,dsa_fdb_dump_cb_t * cb,void * data)1797 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1798 dsa_fdb_dump_cb_t *cb, void *data)
1799 {
1800 if (!ent->is_valid)
1801 return 0;
1802
1803 if (port != ent->port)
1804 return 0;
1805
1806 return cb(ent->mac, ent->vid, ent->is_static, data);
1807 }
1808
b53_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)1809 int b53_fdb_dump(struct dsa_switch *ds, int port,
1810 dsa_fdb_dump_cb_t *cb, void *data)
1811 {
1812 struct b53_device *priv = ds->priv;
1813 struct b53_arl_entry results[2];
1814 unsigned int count = 0;
1815 int ret;
1816 u8 reg;
1817
1818 mutex_lock(&priv->arl_mutex);
1819
1820 /* Start search operation */
1821 reg = ARL_SRCH_STDN;
1822 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1823
1824 do {
1825 ret = b53_arl_search_wait(priv);
1826 if (ret)
1827 break;
1828
1829 b53_arl_search_rd(priv, 0, &results[0]);
1830 ret = b53_fdb_copy(port, &results[0], cb, data);
1831 if (ret)
1832 break;
1833
1834 if (priv->num_arl_bins > 2) {
1835 b53_arl_search_rd(priv, 1, &results[1]);
1836 ret = b53_fdb_copy(port, &results[1], cb, data);
1837 if (ret)
1838 break;
1839
1840 if (!results[0].is_valid && !results[1].is_valid)
1841 break;
1842 }
1843
1844 } while (count++ < b53_max_arl_entries(priv) / 2);
1845
1846 mutex_unlock(&priv->arl_mutex);
1847
1848 return 0;
1849 }
1850 EXPORT_SYMBOL(b53_fdb_dump);
1851
b53_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)1852 int b53_mdb_add(struct dsa_switch *ds, int port,
1853 const struct switchdev_obj_port_mdb *mdb,
1854 struct dsa_db db)
1855 {
1856 struct b53_device *priv = ds->priv;
1857 int ret;
1858
1859 /* 5325 and 5365 require some more massaging, but could
1860 * be supported eventually
1861 */
1862 if (is5325(priv) || is5365(priv))
1863 return -EOPNOTSUPP;
1864
1865 mutex_lock(&priv->arl_mutex);
1866 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true);
1867 mutex_unlock(&priv->arl_mutex);
1868
1869 return ret;
1870 }
1871 EXPORT_SYMBOL(b53_mdb_add);
1872
b53_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)1873 int b53_mdb_del(struct dsa_switch *ds, int port,
1874 const struct switchdev_obj_port_mdb *mdb,
1875 struct dsa_db db)
1876 {
1877 struct b53_device *priv = ds->priv;
1878 int ret;
1879
1880 mutex_lock(&priv->arl_mutex);
1881 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false);
1882 mutex_unlock(&priv->arl_mutex);
1883 if (ret)
1884 dev_err(ds->dev, "failed to delete MDB entry\n");
1885
1886 return ret;
1887 }
1888 EXPORT_SYMBOL(b53_mdb_del);
1889
b53_br_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)1890 int b53_br_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge,
1891 bool *tx_fwd_offload, struct netlink_ext_ack *extack)
1892 {
1893 struct b53_device *dev = ds->priv;
1894 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1895 u16 pvlan, reg;
1896 unsigned int i;
1897
1898 /* On 7278, port 7 which connects to the ASP should only receive
1899 * traffic from matching CFP rules.
1900 */
1901 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7)
1902 return -EINVAL;
1903
1904 /* Make this port leave the all VLANs join since we will have proper
1905 * VLAN entries from now on
1906 */
1907 if (is58xx(dev)) {
1908 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1909 reg &= ~BIT(port);
1910 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1911 reg &= ~BIT(cpu_port);
1912 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1913 }
1914
1915 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1916
1917 b53_for_each_port(dev, i) {
1918 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1919 continue;
1920
1921 /* Add this local port to the remote port VLAN control
1922 * membership and update the remote port bitmask
1923 */
1924 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1925 reg |= BIT(port);
1926 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1927 dev->ports[i].vlan_ctl_mask = reg;
1928
1929 pvlan |= BIT(i);
1930 }
1931
1932 /* Configure the local port VLAN control membership to include
1933 * remote ports and update the local port bitmask
1934 */
1935 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1936 dev->ports[port].vlan_ctl_mask = pvlan;
1937
1938 return 0;
1939 }
1940 EXPORT_SYMBOL(b53_br_join);
1941
b53_br_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)1942 void b53_br_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge)
1943 {
1944 struct b53_device *dev = ds->priv;
1945 struct b53_vlan *vl = &dev->vlans[0];
1946 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1947 unsigned int i;
1948 u16 pvlan, reg, pvid;
1949
1950 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1951
1952 b53_for_each_port(dev, i) {
1953 /* Don't touch the remaining ports */
1954 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1955 continue;
1956
1957 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1958 reg &= ~BIT(port);
1959 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1960 dev->ports[port].vlan_ctl_mask = reg;
1961
1962 /* Prevent self removal to preserve isolation */
1963 if (port != i)
1964 pvlan &= ~BIT(i);
1965 }
1966
1967 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1968 dev->ports[port].vlan_ctl_mask = pvlan;
1969
1970 pvid = b53_default_pvid(dev);
1971
1972 /* Make this port join all VLANs without VLAN entries */
1973 if (is58xx(dev)) {
1974 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1975 reg |= BIT(port);
1976 if (!(reg & BIT(cpu_port)))
1977 reg |= BIT(cpu_port);
1978 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1979 } else {
1980 b53_get_vlan_entry(dev, pvid, vl);
1981 vl->members |= BIT(port) | BIT(cpu_port);
1982 vl->untag |= BIT(port) | BIT(cpu_port);
1983 b53_set_vlan_entry(dev, pvid, vl);
1984 }
1985 }
1986 EXPORT_SYMBOL(b53_br_leave);
1987
b53_br_set_stp_state(struct dsa_switch * ds,int port,u8 state)1988 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1989 {
1990 struct b53_device *dev = ds->priv;
1991 u8 hw_state;
1992 u8 reg;
1993
1994 switch (state) {
1995 case BR_STATE_DISABLED:
1996 hw_state = PORT_CTRL_DIS_STATE;
1997 break;
1998 case BR_STATE_LISTENING:
1999 hw_state = PORT_CTRL_LISTEN_STATE;
2000 break;
2001 case BR_STATE_LEARNING:
2002 hw_state = PORT_CTRL_LEARN_STATE;
2003 break;
2004 case BR_STATE_FORWARDING:
2005 hw_state = PORT_CTRL_FWD_STATE;
2006 break;
2007 case BR_STATE_BLOCKING:
2008 hw_state = PORT_CTRL_BLOCK_STATE;
2009 break;
2010 default:
2011 dev_err(ds->dev, "invalid STP state: %d\n", state);
2012 return;
2013 }
2014
2015 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
2016 reg &= ~PORT_CTRL_STP_STATE_MASK;
2017 reg |= hw_state;
2018 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
2019 }
2020 EXPORT_SYMBOL(b53_br_set_stp_state);
2021
b53_br_fast_age(struct dsa_switch * ds,int port)2022 void b53_br_fast_age(struct dsa_switch *ds, int port)
2023 {
2024 struct b53_device *dev = ds->priv;
2025
2026 if (b53_fast_age_port(dev, port))
2027 dev_err(ds->dev, "fast ageing failed\n");
2028 }
2029 EXPORT_SYMBOL(b53_br_fast_age);
2030
b53_br_flags_pre(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)2031 int b53_br_flags_pre(struct dsa_switch *ds, int port,
2032 struct switchdev_brport_flags flags,
2033 struct netlink_ext_ack *extack)
2034 {
2035 if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD | BR_LEARNING))
2036 return -EINVAL;
2037
2038 return 0;
2039 }
2040 EXPORT_SYMBOL(b53_br_flags_pre);
2041
b53_br_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)2042 int b53_br_flags(struct dsa_switch *ds, int port,
2043 struct switchdev_brport_flags flags,
2044 struct netlink_ext_ack *extack)
2045 {
2046 if (flags.mask & BR_FLOOD)
2047 b53_port_set_ucast_flood(ds->priv, port,
2048 !!(flags.val & BR_FLOOD));
2049 if (flags.mask & BR_MCAST_FLOOD)
2050 b53_port_set_mcast_flood(ds->priv, port,
2051 !!(flags.val & BR_MCAST_FLOOD));
2052 if (flags.mask & BR_LEARNING)
2053 b53_port_set_learning(ds->priv, port,
2054 !!(flags.val & BR_LEARNING));
2055
2056 return 0;
2057 }
2058 EXPORT_SYMBOL(b53_br_flags);
2059
b53_possible_cpu_port(struct dsa_switch * ds,int port)2060 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port)
2061 {
2062 /* Broadcom switches will accept enabling Broadcom tags on the
2063 * following ports: 5, 7 and 8, any other port is not supported
2064 */
2065 switch (port) {
2066 case B53_CPU_PORT_25:
2067 case 7:
2068 case B53_CPU_PORT:
2069 return true;
2070 }
2071
2072 return false;
2073 }
2074
b53_can_enable_brcm_tags(struct dsa_switch * ds,int port,enum dsa_tag_protocol tag_protocol)2075 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port,
2076 enum dsa_tag_protocol tag_protocol)
2077 {
2078 bool ret = b53_possible_cpu_port(ds, port);
2079
2080 if (!ret) {
2081 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n",
2082 port);
2083 return ret;
2084 }
2085
2086 switch (tag_protocol) {
2087 case DSA_TAG_PROTO_BRCM:
2088 case DSA_TAG_PROTO_BRCM_PREPEND:
2089 dev_warn(ds->dev,
2090 "Port %d is stacked to Broadcom tag switch\n", port);
2091 ret = false;
2092 break;
2093 default:
2094 ret = true;
2095 break;
2096 }
2097
2098 return ret;
2099 }
2100
b53_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mprot)2101 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port,
2102 enum dsa_tag_protocol mprot)
2103 {
2104 struct b53_device *dev = ds->priv;
2105
2106 if (!b53_can_enable_brcm_tags(ds, port, mprot)) {
2107 dev->tag_protocol = DSA_TAG_PROTO_NONE;
2108 goto out;
2109 }
2110
2111 /* Older models require a different 6 byte tag */
2112 if (is5325(dev) || is5365(dev) || is63xx(dev)) {
2113 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY;
2114 goto out;
2115 }
2116
2117 /* Broadcom BCM58xx chips have a flow accelerator on Port 8
2118 * which requires us to use the prepended Broadcom tag type
2119 */
2120 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) {
2121 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND;
2122 goto out;
2123 }
2124
2125 dev->tag_protocol = DSA_TAG_PROTO_BRCM;
2126 out:
2127 return dev->tag_protocol;
2128 }
2129 EXPORT_SYMBOL(b53_get_tag_protocol);
2130
b53_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)2131 int b53_mirror_add(struct dsa_switch *ds, int port,
2132 struct dsa_mall_mirror_tc_entry *mirror, bool ingress,
2133 struct netlink_ext_ack *extack)
2134 {
2135 struct b53_device *dev = ds->priv;
2136 u16 reg, loc;
2137
2138 if (ingress)
2139 loc = B53_IG_MIR_CTL;
2140 else
2141 loc = B53_EG_MIR_CTL;
2142
2143 b53_read16(dev, B53_MGMT_PAGE, loc, ®);
2144 reg |= BIT(port);
2145 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2146
2147 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®);
2148 reg &= ~CAP_PORT_MASK;
2149 reg |= mirror->to_local_port;
2150 reg |= MIRROR_EN;
2151 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2152
2153 return 0;
2154 }
2155 EXPORT_SYMBOL(b53_mirror_add);
2156
b53_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)2157 void b53_mirror_del(struct dsa_switch *ds, int port,
2158 struct dsa_mall_mirror_tc_entry *mirror)
2159 {
2160 struct b53_device *dev = ds->priv;
2161 bool loc_disable = false, other_loc_disable = false;
2162 u16 reg, loc;
2163
2164 if (mirror->ingress)
2165 loc = B53_IG_MIR_CTL;
2166 else
2167 loc = B53_EG_MIR_CTL;
2168
2169 /* Update the desired ingress/egress register */
2170 b53_read16(dev, B53_MGMT_PAGE, loc, ®);
2171 reg &= ~BIT(port);
2172 if (!(reg & MIRROR_MASK))
2173 loc_disable = true;
2174 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2175
2176 /* Now look at the other one to know if we can disable mirroring
2177 * entirely
2178 */
2179 if (mirror->ingress)
2180 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®);
2181 else
2182 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®);
2183 if (!(reg & MIRROR_MASK))
2184 other_loc_disable = true;
2185
2186 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®);
2187 /* Both no longer have ports, let's disable mirroring */
2188 if (loc_disable && other_loc_disable) {
2189 reg &= ~MIRROR_EN;
2190 reg &= ~mirror->to_local_port;
2191 }
2192 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2193 }
2194 EXPORT_SYMBOL(b53_mirror_del);
2195
b53_eee_enable_set(struct dsa_switch * ds,int port,bool enable)2196 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
2197 {
2198 struct b53_device *dev = ds->priv;
2199 u16 reg;
2200
2201 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®);
2202 if (enable)
2203 reg |= BIT(port);
2204 else
2205 reg &= ~BIT(port);
2206 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
2207 }
2208 EXPORT_SYMBOL(b53_eee_enable_set);
2209
2210
2211 /* Returns 0 if EEE was not enabled, or 1 otherwise
2212 */
b53_eee_init(struct dsa_switch * ds,int port,struct phy_device * phy)2213 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
2214 {
2215 int ret;
2216
2217 ret = phy_init_eee(phy, false);
2218 if (ret)
2219 return 0;
2220
2221 b53_eee_enable_set(ds, port, true);
2222
2223 return 1;
2224 }
2225 EXPORT_SYMBOL(b53_eee_init);
2226
b53_get_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)2227 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
2228 {
2229 struct b53_device *dev = ds->priv;
2230 struct ethtool_eee *p = &dev->ports[port].eee;
2231 u16 reg;
2232
2233 if (is5325(dev) || is5365(dev))
2234 return -EOPNOTSUPP;
2235
2236 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®);
2237 e->eee_enabled = p->eee_enabled;
2238 e->eee_active = !!(reg & BIT(port));
2239
2240 return 0;
2241 }
2242 EXPORT_SYMBOL(b53_get_mac_eee);
2243
b53_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)2244 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
2245 {
2246 struct b53_device *dev = ds->priv;
2247 struct ethtool_eee *p = &dev->ports[port].eee;
2248
2249 if (is5325(dev) || is5365(dev))
2250 return -EOPNOTSUPP;
2251
2252 p->eee_enabled = e->eee_enabled;
2253 b53_eee_enable_set(ds, port, e->eee_enabled);
2254
2255 return 0;
2256 }
2257 EXPORT_SYMBOL(b53_set_mac_eee);
2258
b53_change_mtu(struct dsa_switch * ds,int port,int mtu)2259 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu)
2260 {
2261 struct b53_device *dev = ds->priv;
2262 bool enable_jumbo;
2263 bool allow_10_100;
2264
2265 if (is5325(dev) || is5365(dev))
2266 return -EOPNOTSUPP;
2267
2268 if (!dsa_is_cpu_port(ds, port))
2269 return 0;
2270
2271 enable_jumbo = (mtu >= JMS_MIN_SIZE);
2272 allow_10_100 = (dev->chip_id == BCM583XX_DEVICE_ID);
2273
2274 return b53_set_jumbo(dev, enable_jumbo, allow_10_100);
2275 }
2276
b53_get_max_mtu(struct dsa_switch * ds,int port)2277 static int b53_get_max_mtu(struct dsa_switch *ds, int port)
2278 {
2279 return JMS_MAX_SIZE;
2280 }
2281
2282 static const struct dsa_switch_ops b53_switch_ops = {
2283 .get_tag_protocol = b53_get_tag_protocol,
2284 .setup = b53_setup,
2285 .teardown = b53_teardown,
2286 .get_strings = b53_get_strings,
2287 .get_ethtool_stats = b53_get_ethtool_stats,
2288 .get_sset_count = b53_get_sset_count,
2289 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
2290 .phy_read = b53_phy_read16,
2291 .phy_write = b53_phy_write16,
2292 .adjust_link = b53_adjust_link,
2293 .phylink_get_caps = b53_phylink_get_caps,
2294 .phylink_mac_select_pcs = b53_phylink_mac_select_pcs,
2295 .phylink_mac_config = b53_phylink_mac_config,
2296 .phylink_mac_link_down = b53_phylink_mac_link_down,
2297 .phylink_mac_link_up = b53_phylink_mac_link_up,
2298 .port_enable = b53_enable_port,
2299 .port_disable = b53_disable_port,
2300 .get_mac_eee = b53_get_mac_eee,
2301 .set_mac_eee = b53_set_mac_eee,
2302 .port_bridge_join = b53_br_join,
2303 .port_bridge_leave = b53_br_leave,
2304 .port_pre_bridge_flags = b53_br_flags_pre,
2305 .port_bridge_flags = b53_br_flags,
2306 .port_stp_state_set = b53_br_set_stp_state,
2307 .port_fast_age = b53_br_fast_age,
2308 .port_vlan_filtering = b53_vlan_filtering,
2309 .port_vlan_add = b53_vlan_add,
2310 .port_vlan_del = b53_vlan_del,
2311 .port_fdb_dump = b53_fdb_dump,
2312 .port_fdb_add = b53_fdb_add,
2313 .port_fdb_del = b53_fdb_del,
2314 .port_mirror_add = b53_mirror_add,
2315 .port_mirror_del = b53_mirror_del,
2316 .port_mdb_add = b53_mdb_add,
2317 .port_mdb_del = b53_mdb_del,
2318 .port_max_mtu = b53_get_max_mtu,
2319 .port_change_mtu = b53_change_mtu,
2320 };
2321
2322 struct b53_chip_data {
2323 u32 chip_id;
2324 const char *dev_name;
2325 u16 vlans;
2326 u16 enabled_ports;
2327 u8 imp_port;
2328 u8 cpu_port;
2329 u8 vta_regs[3];
2330 u8 arl_bins;
2331 u16 arl_buckets;
2332 u8 duplex_reg;
2333 u8 jumbo_pm_reg;
2334 u8 jumbo_size_reg;
2335 };
2336
2337 #define B53_VTA_REGS \
2338 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
2339 #define B53_VTA_REGS_9798 \
2340 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
2341 #define B53_VTA_REGS_63XX \
2342 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
2343
2344 static const struct b53_chip_data b53_switch_chips[] = {
2345 {
2346 .chip_id = BCM5325_DEVICE_ID,
2347 .dev_name = "BCM5325",
2348 .vlans = 16,
2349 .enabled_ports = 0x3f,
2350 .arl_bins = 2,
2351 .arl_buckets = 1024,
2352 .imp_port = 5,
2353 .duplex_reg = B53_DUPLEX_STAT_FE,
2354 },
2355 {
2356 .chip_id = BCM5365_DEVICE_ID,
2357 .dev_name = "BCM5365",
2358 .vlans = 256,
2359 .enabled_ports = 0x3f,
2360 .arl_bins = 2,
2361 .arl_buckets = 1024,
2362 .imp_port = 5,
2363 .duplex_reg = B53_DUPLEX_STAT_FE,
2364 },
2365 {
2366 .chip_id = BCM5389_DEVICE_ID,
2367 .dev_name = "BCM5389",
2368 .vlans = 4096,
2369 .enabled_ports = 0x11f,
2370 .arl_bins = 4,
2371 .arl_buckets = 1024,
2372 .imp_port = 8,
2373 .vta_regs = B53_VTA_REGS,
2374 .duplex_reg = B53_DUPLEX_STAT_GE,
2375 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2376 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2377 },
2378 {
2379 .chip_id = BCM5395_DEVICE_ID,
2380 .dev_name = "BCM5395",
2381 .vlans = 4096,
2382 .enabled_ports = 0x11f,
2383 .arl_bins = 4,
2384 .arl_buckets = 1024,
2385 .imp_port = 8,
2386 .vta_regs = B53_VTA_REGS,
2387 .duplex_reg = B53_DUPLEX_STAT_GE,
2388 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2389 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2390 },
2391 {
2392 .chip_id = BCM5397_DEVICE_ID,
2393 .dev_name = "BCM5397",
2394 .vlans = 4096,
2395 .enabled_ports = 0x11f,
2396 .arl_bins = 4,
2397 .arl_buckets = 1024,
2398 .imp_port = 8,
2399 .vta_regs = B53_VTA_REGS_9798,
2400 .duplex_reg = B53_DUPLEX_STAT_GE,
2401 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2402 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2403 },
2404 {
2405 .chip_id = BCM5398_DEVICE_ID,
2406 .dev_name = "BCM5398",
2407 .vlans = 4096,
2408 .enabled_ports = 0x17f,
2409 .arl_bins = 4,
2410 .arl_buckets = 1024,
2411 .imp_port = 8,
2412 .vta_regs = B53_VTA_REGS_9798,
2413 .duplex_reg = B53_DUPLEX_STAT_GE,
2414 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2415 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2416 },
2417 {
2418 .chip_id = BCM53115_DEVICE_ID,
2419 .dev_name = "BCM53115",
2420 .vlans = 4096,
2421 .enabled_ports = 0x11f,
2422 .arl_bins = 4,
2423 .arl_buckets = 1024,
2424 .vta_regs = B53_VTA_REGS,
2425 .imp_port = 8,
2426 .duplex_reg = B53_DUPLEX_STAT_GE,
2427 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2428 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2429 },
2430 {
2431 .chip_id = BCM53125_DEVICE_ID,
2432 .dev_name = "BCM53125",
2433 .vlans = 4096,
2434 .enabled_ports = 0x1ff,
2435 .arl_bins = 4,
2436 .arl_buckets = 1024,
2437 .imp_port = 8,
2438 .vta_regs = B53_VTA_REGS,
2439 .duplex_reg = B53_DUPLEX_STAT_GE,
2440 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2441 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2442 },
2443 {
2444 .chip_id = BCM53128_DEVICE_ID,
2445 .dev_name = "BCM53128",
2446 .vlans = 4096,
2447 .enabled_ports = 0x1ff,
2448 .arl_bins = 4,
2449 .arl_buckets = 1024,
2450 .imp_port = 8,
2451 .vta_regs = B53_VTA_REGS,
2452 .duplex_reg = B53_DUPLEX_STAT_GE,
2453 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2454 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2455 },
2456 {
2457 .chip_id = BCM63XX_DEVICE_ID,
2458 .dev_name = "BCM63xx",
2459 .vlans = 4096,
2460 .enabled_ports = 0, /* pdata must provide them */
2461 .arl_bins = 4,
2462 .arl_buckets = 1024,
2463 .imp_port = 8,
2464 .vta_regs = B53_VTA_REGS_63XX,
2465 .duplex_reg = B53_DUPLEX_STAT_63XX,
2466 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2467 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2468 },
2469 {
2470 .chip_id = BCM63268_DEVICE_ID,
2471 .dev_name = "BCM63268",
2472 .vlans = 4096,
2473 .enabled_ports = 0, /* pdata must provide them */
2474 .arl_bins = 4,
2475 .arl_buckets = 1024,
2476 .imp_port = 8,
2477 .vta_regs = B53_VTA_REGS_63XX,
2478 .duplex_reg = B53_DUPLEX_STAT_63XX,
2479 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2480 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2481 },
2482 {
2483 .chip_id = BCM53010_DEVICE_ID,
2484 .dev_name = "BCM53010",
2485 .vlans = 4096,
2486 .enabled_ports = 0x1bf,
2487 .arl_bins = 4,
2488 .arl_buckets = 1024,
2489 .imp_port = 8,
2490 .vta_regs = B53_VTA_REGS,
2491 .duplex_reg = B53_DUPLEX_STAT_GE,
2492 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2493 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2494 },
2495 {
2496 .chip_id = BCM53011_DEVICE_ID,
2497 .dev_name = "BCM53011",
2498 .vlans = 4096,
2499 .enabled_ports = 0x1bf,
2500 .arl_bins = 4,
2501 .arl_buckets = 1024,
2502 .imp_port = 8,
2503 .vta_regs = B53_VTA_REGS,
2504 .duplex_reg = B53_DUPLEX_STAT_GE,
2505 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2506 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2507 },
2508 {
2509 .chip_id = BCM53012_DEVICE_ID,
2510 .dev_name = "BCM53012",
2511 .vlans = 4096,
2512 .enabled_ports = 0x1bf,
2513 .arl_bins = 4,
2514 .arl_buckets = 1024,
2515 .imp_port = 8,
2516 .vta_regs = B53_VTA_REGS,
2517 .duplex_reg = B53_DUPLEX_STAT_GE,
2518 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2519 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2520 },
2521 {
2522 .chip_id = BCM53018_DEVICE_ID,
2523 .dev_name = "BCM53018",
2524 .vlans = 4096,
2525 .enabled_ports = 0x1bf,
2526 .arl_bins = 4,
2527 .arl_buckets = 1024,
2528 .imp_port = 8,
2529 .vta_regs = B53_VTA_REGS,
2530 .duplex_reg = B53_DUPLEX_STAT_GE,
2531 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2532 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2533 },
2534 {
2535 .chip_id = BCM53019_DEVICE_ID,
2536 .dev_name = "BCM53019",
2537 .vlans = 4096,
2538 .enabled_ports = 0x1bf,
2539 .arl_bins = 4,
2540 .arl_buckets = 1024,
2541 .imp_port = 8,
2542 .vta_regs = B53_VTA_REGS,
2543 .duplex_reg = B53_DUPLEX_STAT_GE,
2544 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2545 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2546 },
2547 {
2548 .chip_id = BCM58XX_DEVICE_ID,
2549 .dev_name = "BCM585xx/586xx/88312",
2550 .vlans = 4096,
2551 .enabled_ports = 0x1ff,
2552 .arl_bins = 4,
2553 .arl_buckets = 1024,
2554 .imp_port = 8,
2555 .vta_regs = B53_VTA_REGS,
2556 .duplex_reg = B53_DUPLEX_STAT_GE,
2557 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2558 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2559 },
2560 {
2561 .chip_id = BCM583XX_DEVICE_ID,
2562 .dev_name = "BCM583xx/11360",
2563 .vlans = 4096,
2564 .enabled_ports = 0x103,
2565 .arl_bins = 4,
2566 .arl_buckets = 1024,
2567 .imp_port = 8,
2568 .vta_regs = B53_VTA_REGS,
2569 .duplex_reg = B53_DUPLEX_STAT_GE,
2570 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2571 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2572 },
2573 /* Starfighter 2 */
2574 {
2575 .chip_id = BCM4908_DEVICE_ID,
2576 .dev_name = "BCM4908",
2577 .vlans = 4096,
2578 .enabled_ports = 0x1bf,
2579 .arl_bins = 4,
2580 .arl_buckets = 256,
2581 .imp_port = 8,
2582 .vta_regs = B53_VTA_REGS,
2583 .duplex_reg = B53_DUPLEX_STAT_GE,
2584 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2585 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2586 },
2587 {
2588 .chip_id = BCM7445_DEVICE_ID,
2589 .dev_name = "BCM7445",
2590 .vlans = 4096,
2591 .enabled_ports = 0x1ff,
2592 .arl_bins = 4,
2593 .arl_buckets = 1024,
2594 .imp_port = 8,
2595 .vta_regs = B53_VTA_REGS,
2596 .duplex_reg = B53_DUPLEX_STAT_GE,
2597 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2598 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2599 },
2600 {
2601 .chip_id = BCM7278_DEVICE_ID,
2602 .dev_name = "BCM7278",
2603 .vlans = 4096,
2604 .enabled_ports = 0x1ff,
2605 .arl_bins = 4,
2606 .arl_buckets = 256,
2607 .imp_port = 8,
2608 .vta_regs = B53_VTA_REGS,
2609 .duplex_reg = B53_DUPLEX_STAT_GE,
2610 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2611 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2612 },
2613 {
2614 .chip_id = BCM53134_DEVICE_ID,
2615 .dev_name = "BCM53134",
2616 .vlans = 4096,
2617 .enabled_ports = 0x12f,
2618 .imp_port = 8,
2619 .cpu_port = B53_CPU_PORT,
2620 .vta_regs = B53_VTA_REGS,
2621 .arl_bins = 4,
2622 .arl_buckets = 1024,
2623 .duplex_reg = B53_DUPLEX_STAT_GE,
2624 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2625 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2626 },
2627 };
2628
b53_switch_init(struct b53_device * dev)2629 static int b53_switch_init(struct b53_device *dev)
2630 {
2631 unsigned int i;
2632 int ret;
2633
2634 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
2635 const struct b53_chip_data *chip = &b53_switch_chips[i];
2636
2637 if (chip->chip_id == dev->chip_id) {
2638 if (!dev->enabled_ports)
2639 dev->enabled_ports = chip->enabled_ports;
2640 dev->name = chip->dev_name;
2641 dev->duplex_reg = chip->duplex_reg;
2642 dev->vta_regs[0] = chip->vta_regs[0];
2643 dev->vta_regs[1] = chip->vta_regs[1];
2644 dev->vta_regs[2] = chip->vta_regs[2];
2645 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
2646 dev->imp_port = chip->imp_port;
2647 dev->num_vlans = chip->vlans;
2648 dev->num_arl_bins = chip->arl_bins;
2649 dev->num_arl_buckets = chip->arl_buckets;
2650 break;
2651 }
2652 }
2653
2654 /* check which BCM5325x version we have */
2655 if (is5325(dev)) {
2656 u8 vc4;
2657
2658 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
2659
2660 /* check reserved bits */
2661 switch (vc4 & 3) {
2662 case 1:
2663 /* BCM5325E */
2664 break;
2665 case 3:
2666 /* BCM5325F - do not use port 4 */
2667 dev->enabled_ports &= ~BIT(4);
2668 break;
2669 default:
2670 /* On the BCM47XX SoCs this is the supported internal switch.*/
2671 #ifndef CONFIG_BCM47XX
2672 /* BCM5325M */
2673 return -EINVAL;
2674 #else
2675 break;
2676 #endif
2677 }
2678 }
2679
2680 dev->num_ports = fls(dev->enabled_ports);
2681
2682 dev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS);
2683
2684 /* Include non standard CPU port built-in PHYs to be probed */
2685 if (is539x(dev) || is531x5(dev)) {
2686 for (i = 0; i < dev->num_ports; i++) {
2687 if (!(dev->ds->phys_mii_mask & BIT(i)) &&
2688 !b53_possible_cpu_port(dev->ds, i))
2689 dev->ds->phys_mii_mask |= BIT(i);
2690 }
2691 }
2692
2693 dev->ports = devm_kcalloc(dev->dev,
2694 dev->num_ports, sizeof(struct b53_port),
2695 GFP_KERNEL);
2696 if (!dev->ports)
2697 return -ENOMEM;
2698
2699 dev->vlans = devm_kcalloc(dev->dev,
2700 dev->num_vlans, sizeof(struct b53_vlan),
2701 GFP_KERNEL);
2702 if (!dev->vlans)
2703 return -ENOMEM;
2704
2705 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
2706 if (dev->reset_gpio >= 0) {
2707 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
2708 GPIOF_OUT_INIT_HIGH, "robo_reset");
2709 if (ret)
2710 return ret;
2711 }
2712
2713 return 0;
2714 }
2715
b53_switch_alloc(struct device * base,const struct b53_io_ops * ops,void * priv)2716 struct b53_device *b53_switch_alloc(struct device *base,
2717 const struct b53_io_ops *ops,
2718 void *priv)
2719 {
2720 struct dsa_switch *ds;
2721 struct b53_device *dev;
2722
2723 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
2724 if (!ds)
2725 return NULL;
2726
2727 ds->dev = base;
2728
2729 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2730 if (!dev)
2731 return NULL;
2732
2733 ds->priv = dev;
2734 dev->dev = base;
2735
2736 dev->ds = ds;
2737 dev->priv = priv;
2738 dev->ops = ops;
2739 ds->ops = &b53_switch_ops;
2740 dev->vlan_enabled = true;
2741 /* Let DSA handle the case were multiple bridges span the same switch
2742 * device and different VLAN awareness settings are requested, which
2743 * would be breaking filtering semantics for any of the other bridge
2744 * devices. (not hardware supported)
2745 */
2746 ds->vlan_filtering_is_global = true;
2747
2748 mutex_init(&dev->reg_mutex);
2749 mutex_init(&dev->stats_mutex);
2750 mutex_init(&dev->arl_mutex);
2751
2752 return dev;
2753 }
2754 EXPORT_SYMBOL(b53_switch_alloc);
2755
b53_switch_detect(struct b53_device * dev)2756 int b53_switch_detect(struct b53_device *dev)
2757 {
2758 u32 id32;
2759 u16 tmp;
2760 u8 id8;
2761 int ret;
2762
2763 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2764 if (ret)
2765 return ret;
2766
2767 switch (id8) {
2768 case 0:
2769 /* BCM5325 and BCM5365 do not have this register so reads
2770 * return 0. But the read operation did succeed, so assume this
2771 * is one of them.
2772 *
2773 * Next check if we can write to the 5325's VTA register; for
2774 * 5365 it is read only.
2775 */
2776 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2777 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2778
2779 if (tmp == 0xf)
2780 dev->chip_id = BCM5325_DEVICE_ID;
2781 else
2782 dev->chip_id = BCM5365_DEVICE_ID;
2783 break;
2784 case BCM5389_DEVICE_ID:
2785 case BCM5395_DEVICE_ID:
2786 case BCM5397_DEVICE_ID:
2787 case BCM5398_DEVICE_ID:
2788 dev->chip_id = id8;
2789 break;
2790 default:
2791 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2792 if (ret)
2793 return ret;
2794
2795 switch (id32) {
2796 case BCM53115_DEVICE_ID:
2797 case BCM53125_DEVICE_ID:
2798 case BCM53128_DEVICE_ID:
2799 case BCM53010_DEVICE_ID:
2800 case BCM53011_DEVICE_ID:
2801 case BCM53012_DEVICE_ID:
2802 case BCM53018_DEVICE_ID:
2803 case BCM53019_DEVICE_ID:
2804 case BCM53134_DEVICE_ID:
2805 dev->chip_id = id32;
2806 break;
2807 default:
2808 dev_err(dev->dev,
2809 "unsupported switch detected (BCM53%02x/BCM%x)\n",
2810 id8, id32);
2811 return -ENODEV;
2812 }
2813 }
2814
2815 if (dev->chip_id == BCM5325_DEVICE_ID)
2816 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2817 &dev->core_rev);
2818 else
2819 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2820 &dev->core_rev);
2821 }
2822 EXPORT_SYMBOL(b53_switch_detect);
2823
b53_switch_register(struct b53_device * dev)2824 int b53_switch_register(struct b53_device *dev)
2825 {
2826 int ret;
2827
2828 if (dev->pdata) {
2829 dev->chip_id = dev->pdata->chip_id;
2830 dev->enabled_ports = dev->pdata->enabled_ports;
2831 }
2832
2833 if (!dev->chip_id && b53_switch_detect(dev))
2834 return -EINVAL;
2835
2836 ret = b53_switch_init(dev);
2837 if (ret)
2838 return ret;
2839
2840 dev_info(dev->dev, "found switch: %s, rev %i\n",
2841 dev->name, dev->core_rev);
2842
2843 return dsa_register_switch(dev->ds);
2844 }
2845 EXPORT_SYMBOL(b53_switch_register);
2846
2847 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2848 MODULE_DESCRIPTION("B53 switch library");
2849 MODULE_LICENSE("Dual BSD/GPL");
2850