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/drivers/net/wireless/quantenna/qtnfmac/pcie/
Dpearl_pcie_regs.h8 #define PCIE_HDP_CTRL(base) ((base) + 0x2c00) argument
9 #define PCIE_HDP_AXI_CTRL(base) ((base) + 0x2c04) argument
10 #define PCIE_HDP_HOST_WR_DESC0(base) ((base) + 0x2c10) argument
11 #define PCIE_HDP_HOST_WR_DESC0_H(base) ((base) + 0x2c14) argument
12 #define PCIE_HDP_HOST_WR_DESC1(base) ((base) + 0x2c18) argument
13 #define PCIE_HDP_HOST_WR_DESC1_H(base) ((base) + 0x2c1c) argument
14 #define PCIE_HDP_HOST_WR_DESC2(base) ((base) + 0x2c20) argument
15 #define PCIE_HDP_HOST_WR_DESC2_H(base) ((base) + 0x2c24) argument
16 #define PCIE_HDP_HOST_WR_DESC3(base) ((base) + 0x2c28) argument
17 #define PCIE_HDP_HOST_WR_DESC4_H(base) ((base) + 0x2c2c) argument
[all …]
Dtopaz_pcie_regs.h8 #define PCIE_DMA_WR_INTR_STATUS(base) ((base) + 0x9bc) argument
9 #define PCIE_DMA_WR_INTR_MASK(base) ((base) + 0x9c4) argument
10 #define PCIE_DMA_WR_INTR_CLR(base) ((base) + 0x9c8) argument
11 #define PCIE_DMA_WR_ERR_STATUS(base) ((base) + 0x9cc) argument
12 #define PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(base) ((base) + 0x9D0) argument
13 #define PCIE_DMA_WR_DONE_IMWR_ADDR_HIGH(base) ((base) + 0x9d4) argument
15 #define PCIE_DMA_RD_INTR_STATUS(base) ((base) + 0x310) argument
16 #define PCIE_DMA_RD_INTR_MASK(base) ((base) + 0x319) argument
17 #define PCIE_DMA_RD_INTR_CLR(base) ((base) + 0x31c) argument
18 #define PCIE_DMA_RD_ERR_STATUS_LOW(base) ((base) + 0x324) argument
[all …]
/drivers/gpu/drm/i915/gt/
Dintel_engine_regs.h11 #define RING_EXCC(base) _MMIO((base) + 0x28) argument
12 #define RING_TAIL(base) _MMIO((base) + 0x30) argument
14 #define RING_HEAD(base) _MMIO((base) + 0x34) argument
18 #define RING_START(base) _MMIO((base) + 0x38) argument
19 #define RING_CTL(base) _MMIO((base) + 0x3c) argument
32 #define RING_SYNC_0(base) _MMIO((base) + 0x40) argument
33 #define RING_SYNC_1(base) _MMIO((base) + 0x44) argument
34 #define RING_SYNC_2(base) _MMIO((base) + 0x48) argument
47 #define RING_PSMI_CTL(base) _MMIO((base) + 0x50) argument
55 #define RING_MAX_IDLE(base) _MMIO((base) + 0x54) argument
[all …]
/drivers/gpu/drm/sun4i/
Dsun8i_vi_scaler.h30 #define SUN8I_SCALER_VSU_CTRL(base) ((base) + 0x0) argument
31 #define SUN50I_SCALER_VSU_SCALE_MODE(base) ((base) + 0x10) argument
32 #define SUN50I_SCALER_VSU_DIR_THR(base) ((base) + 0x20) argument
33 #define SUN50I_SCALER_VSU_EDGE_THR(base) ((base) + 0x24) argument
34 #define SUN50I_SCALER_VSU_EDSCL_CTRL(base) ((base) + 0x28) argument
35 #define SUN50I_SCALER_VSU_ANGLE_THR(base) ((base) + 0x2c) argument
36 #define SUN8I_SCALER_VSU_OUTSIZE(base) ((base) + 0x40) argument
37 #define SUN8I_SCALER_VSU_YINSIZE(base) ((base) + 0x80) argument
38 #define SUN8I_SCALER_VSU_YHSTEP(base) ((base) + 0x88) argument
39 #define SUN8I_SCALER_VSU_YVSTEP(base) ((base) + 0x8c) argument
[all …]
Dsun8i_ui_layer.h17 #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR(base, layer) \ argument
19 #define SUN8I_MIXER_CHAN_UI_LAYER_SIZE(base, layer) \ argument
21 #define SUN8I_MIXER_CHAN_UI_LAYER_COORD(base, layer) \ argument
23 #define SUN8I_MIXER_CHAN_UI_LAYER_PITCH(base, layer) \ argument
25 #define SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(base, layer) \ argument
27 #define SUN8I_MIXER_CHAN_UI_LAYER_BOT_LADDR(base, layer) \ argument
29 #define SUN8I_MIXER_CHAN_UI_LAYER_FCOLOR(base, layer) \ argument
31 #define SUN8I_MIXER_CHAN_UI_TOP_HADDR(base) \ argument
33 #define SUN8I_MIXER_CHAN_UI_BOT_HADDR(base) \ argument
35 #define SUN8I_MIXER_CHAN_UI_OVL_SIZE(base) \ argument
Dsun8i_vi_layer.h11 #define SUN8I_MIXER_CHAN_VI_LAYER_ATTR(base, layer) \ argument
13 #define SUN8I_MIXER_CHAN_VI_LAYER_SIZE(base, layer) \ argument
15 #define SUN8I_MIXER_CHAN_VI_LAYER_COORD(base, layer) \ argument
17 #define SUN8I_MIXER_CHAN_VI_LAYER_PITCH(base, layer, plane) \ argument
19 #define SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(base, layer, plane) \ argument
21 #define SUN8I_MIXER_CHAN_VI_OVL_SIZE(base) \ argument
23 #define SUN8I_MIXER_CHAN_VI_HDS_Y(base) \ argument
25 #define SUN8I_MIXER_CHAN_VI_HDS_UV(base) \ argument
27 #define SUN8I_MIXER_CHAN_VI_VDS_Y(base) \ argument
29 #define SUN8I_MIXER_CHAN_VI_VDS_UV(base) \ argument
Dsun8i_ui_scaler.h26 #define SUN8I_SCALER_GSU_CTRL(base) ((base) + 0x0) argument
27 #define SUN8I_SCALER_GSU_OUTSIZE(base) ((base) + 0x40) argument
28 #define SUN8I_SCALER_GSU_INSIZE(base) ((base) + 0x80) argument
29 #define SUN8I_SCALER_GSU_HSTEP(base) ((base) + 0x88) argument
30 #define SUN8I_SCALER_GSU_VSTEP(base) ((base) + 0x8c) argument
31 #define SUN8I_SCALER_GSU_HPHASE(base) ((base) + 0x90) argument
32 #define SUN8I_SCALER_GSU_VPHASE(base) ((base) + 0x98) argument
33 #define SUN8I_SCALER_GSU_HCOEFF(base, index) ((base) + 0x200 + 0x4 * (index)) argument
Dsun8i_mixer.h38 #define SUN8I_MIXER_BLEND_PIPE_CTL(base) ((base) + 0) argument
39 #define SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, x) ((base) + 0x4 + 0x10 * (x)) argument
40 #define SUN8I_MIXER_BLEND_ATTR_INSIZE(base, x) ((base) + 0x8 + 0x10 * (x)) argument
41 #define SUN8I_MIXER_BLEND_ATTR_COORD(base, x) ((base) + 0xc + 0x10 * (x)) argument
42 #define SUN8I_MIXER_BLEND_ROUTE(base) ((base) + 0x80) argument
43 #define SUN8I_MIXER_BLEND_PREMULTIPLY(base) ((base) + 0x84) argument
44 #define SUN8I_MIXER_BLEND_BKCOLOR(base) ((base) + 0x88) argument
45 #define SUN8I_MIXER_BLEND_OUTSIZE(base) ((base) + 0x8c) argument
46 #define SUN8I_MIXER_BLEND_MODE(base, x) ((base) + 0x90 + 0x04 * (x)) argument
47 #define SUN8I_MIXER_BLEND_CK_CTL(base) ((base) + 0xb0) argument
[all …]
/drivers/media/platform/samsung/s5p-jpeg/
Djpeg-hw-exynos4.c16 void exynos4_jpeg_sw_reset(void __iomem *base) in exynos4_jpeg_sw_reset()
32 void exynos4_jpeg_set_enc_dec_mode(void __iomem *base, unsigned int mode) in exynos4_jpeg_set_enc_dec_mode()
52 void __exynos4_jpeg_set_img_fmt(void __iomem *base, unsigned int img_fmt, in __exynos4_jpeg_set_img_fmt()
136 void __exynos4_jpeg_set_enc_out_fmt(void __iomem *base, unsigned int out_fmt, in __exynos4_jpeg_set_enc_out_fmt()
169 void exynos4_jpeg_set_interrupt(void __iomem *base, unsigned int version) in exynos4_jpeg_set_interrupt()
183 unsigned int exynos4_jpeg_get_int_status(void __iomem *base) in exynos4_jpeg_get_int_status()
188 unsigned int exynos4_jpeg_get_fifo_status(void __iomem *base) in exynos4_jpeg_get_fifo_status()
193 void exynos4_jpeg_set_huf_table_enable(void __iomem *base, int value) in exynos4_jpeg_set_huf_table_enable()
207 void exynos4_jpeg_set_sys_int_enable(void __iomem *base, int value) in exynos4_jpeg_set_sys_int_enable()
219 void exynos4_jpeg_set_stream_buf_address(void __iomem *base, in exynos4_jpeg_set_stream_buf_address()
[all …]
/drivers/scsi/
Dnsp32_io.h12 static inline void nsp32_write1(unsigned int base, in nsp32_write1()
19 static inline unsigned char nsp32_read1(unsigned int base, in nsp32_read1()
25 static inline void nsp32_write2(unsigned int base, in nsp32_write2()
32 static inline unsigned short nsp32_read2(unsigned int base, in nsp32_read2()
38 static inline void nsp32_write4(unsigned int base, in nsp32_write4()
45 static inline unsigned long nsp32_read4(unsigned int base, in nsp32_read4()
53 static inline void nsp32_mmio_write1(unsigned long base, in nsp32_mmio_write1()
64 static inline unsigned char nsp32_mmio_read1(unsigned long base, in nsp32_mmio_read1()
74 static inline void nsp32_mmio_write2(unsigned long base, in nsp32_mmio_write2()
85 static inline unsigned short nsp32_mmio_read2(unsigned long base, in nsp32_mmio_read2()
[all …]
Daha1740.h19 #define HID0(base) (base + 0x0) argument
20 #define HID1(base) (base + 0x1) argument
21 #define HID2(base) (base + 0x2) argument
22 #define HID3(base) (base + 0x3) argument
23 #define EBCNTRL(base) (base + 0x4) argument
24 #define PORTADR(base) (base + 0x40) argument
25 #define BIOSADR(base) (base + 0x41) argument
26 #define INTDEF(base) (base + 0x42) argument
27 #define SCSIDEF(base) (base + 0x43) argument
28 #define BUSDEF(base) (base + 0x44) argument
[all …]
Dmyrb.c165 void __iomem *base = cb->io_base; in myrb_qcmd() local
808 void __iomem *base = cb->io_base; in myrb_enable_mmio() local
2517 static inline void DAC960_LA_hw_mbox_new_cmd(void __iomem *base) in DAC960_LA_hw_mbox_new_cmd()
2522 static inline void DAC960_LA_ack_hw_mbox_status(void __iomem *base) in DAC960_LA_ack_hw_mbox_status()
2527 static inline void DAC960_LA_reset_ctrl(void __iomem *base) in DAC960_LA_reset_ctrl()
2532 static inline void DAC960_LA_mem_mbox_new_cmd(void __iomem *base) in DAC960_LA_mem_mbox_new_cmd()
2537 static inline bool DAC960_LA_hw_mbox_is_full(void __iomem *base) in DAC960_LA_hw_mbox_is_full()
2544 static inline bool DAC960_LA_init_in_progress(void __iomem *base) in DAC960_LA_init_in_progress()
2551 static inline void DAC960_LA_ack_hw_mbox_intr(void __iomem *base) in DAC960_LA_ack_hw_mbox_intr()
2556 static inline void DAC960_LA_ack_intr(void __iomem *base) in DAC960_LA_ack_intr()
[all …]
Dmyrs.c106 void __iomem *base = cs->io_base; in myrs_qcmd() local
484 void __iomem *base = cs->io_base; in myrs_enable_mmio_mbox() local
2398 static inline void DAC960_GEM_hw_mbox_new_cmd(void __iomem *base) in DAC960_GEM_hw_mbox_new_cmd()
2405 static inline void DAC960_GEM_ack_hw_mbox_status(void __iomem *base) in DAC960_GEM_ack_hw_mbox_status()
2412 static inline void DAC960_GEM_reset_ctrl(void __iomem *base) in DAC960_GEM_reset_ctrl()
2419 static inline void DAC960_GEM_mem_mbox_new_cmd(void __iomem *base) in DAC960_GEM_mem_mbox_new_cmd()
2426 static inline bool DAC960_GEM_hw_mbox_is_full(void __iomem *base) in DAC960_GEM_hw_mbox_is_full()
2434 static inline bool DAC960_GEM_init_in_progress(void __iomem *base) in DAC960_GEM_init_in_progress()
2442 static inline void DAC960_GEM_ack_hw_mbox_intr(void __iomem *base) in DAC960_GEM_ack_hw_mbox_intr()
2449 static inline void DAC960_GEM_ack_intr(void __iomem *base) in DAC960_GEM_ack_intr()
[all …]
/drivers/gpu/drm/i915/
Dintel_gvt_mmio_table.c61 #define RING_REG(base) _MMIO((base) + 0x28) in iterate_generic_mmio() argument
65 #define RING_REG(base) _MMIO((base) + 0x134) in iterate_generic_mmio() argument
69 #define RING_REG(base) _MMIO((base) + 0x6c) in iterate_generic_mmio() argument
83 #define RING_REG(base) _MMIO((base) + 0x29c) in iterate_generic_mmio() argument
772 #define RING_REG(base) _MMIO((base) + 0xd0) in iterate_bdw_plus_mmio() argument
776 #define RING_REG(base) _MMIO((base) + 0x230) in iterate_bdw_plus_mmio() argument
780 #define RING_REG(base) _MMIO((base) + 0x234) in iterate_bdw_plus_mmio() argument
784 #define RING_REG(base) _MMIO((base) + 0x244) in iterate_bdw_plus_mmio() argument
788 #define RING_REG(base) _MMIO((base) + 0x370) in iterate_bdw_plus_mmio() argument
792 #define RING_REG(base) _MMIO((base) + 0x3a0) in iterate_bdw_plus_mmio() argument
[all …]
Di915_perf_oa_regs.h100 #define GEN12_OACTXCONTROL(base) _MMIO((base) + 0x360) argument
172 #define GEN12_OAM_MMIO_TRG(base) \ argument
175 #define GEN12_OAM_HEAD_POINTER(base) \ argument
177 #define GEN12_OAM_TAIL_POINTER(base) \ argument
179 #define GEN12_OAM_BUFFER(base) \ argument
181 #define GEN12_OAM_CONTEXT_CONTROL(base) \ argument
183 #define GEN12_OAM_CONTROL(base) \ argument
185 #define GEN12_OAM_DEBUG(base) \ argument
187 #define GEN12_OAM_STATUS(base) \ argument
192 #define GEN12_OAM_CEC0_0(base) \ argument
[all …]
/drivers/media/platform/mediatek/jpeg/
Dmtk_jpeg_dec_hw.c217 u32 mtk_jpeg_dec_get_int_status(void __iomem *base) in mtk_jpeg_dec_get_int_status()
246 void mtk_jpeg_dec_start(void __iomem *base) in mtk_jpeg_dec_start()
252 static void mtk_jpeg_dec_soft_reset(void __iomem *base) in mtk_jpeg_dec_soft_reset()
259 static void mtk_jpeg_dec_hard_reset(void __iomem *base) in mtk_jpeg_dec_hard_reset()
265 void mtk_jpeg_dec_reset(void __iomem *base) in mtk_jpeg_dec_reset()
272 static void mtk_jpeg_dec_set_brz_factor(void __iomem *base, u8 yscale_w, in mtk_jpeg_dec_set_brz_factor()
282 static void mtk_jpeg_dec_set_dst_bank0(void __iomem *base, u32 addr_y, in mtk_jpeg_dec_set_dst_bank0()
293 static void mtk_jpeg_dec_set_dst_bank1(void __iomem *base, u32 addr_y, in mtk_jpeg_dec_set_dst_bank1()
301 static void mtk_jpeg_dec_set_mem_stride(void __iomem *base, u32 stride_y, in mtk_jpeg_dec_set_mem_stride()
308 static void mtk_jpeg_dec_set_img_stride(void __iomem *base, u32 stride_y, in mtk_jpeg_dec_set_img_stride()
[all …]
/drivers/scsi/pcmcia/
Dnsp_io.h30 static inline void nsp_write(unsigned int base, in nsp_write()
37 static inline unsigned char nsp_read(unsigned int base, in nsp_read()
75 static inline void nsp_fifo8_read(unsigned int base, in nsp_fifo8_read()
94 static inline void nsp_fifo16_read(unsigned int base, in nsp_fifo16_read()
113 static inline void nsp_fifo32_read(unsigned int base, in nsp_fifo32_read()
132 static inline void nsp_fifo8_write(unsigned int base, in nsp_fifo8_write()
150 static inline void nsp_fifo16_write(unsigned int base, in nsp_fifo16_write()
168 static inline void nsp_fifo32_write(unsigned int base, in nsp_fifo32_write()
178 static inline void nsp_mmio_write(unsigned long base, in nsp_mmio_write()
187 static inline unsigned char nsp_mmio_read(unsigned long base, in nsp_mmio_read()
[all …]
/drivers/i3c/master/mipi-i3c-hci/
Dext_caps.c24 static int hci_extcap_hardware_id(struct i3c_hci *hci, void __iomem *base) in hci_extcap_hardware_id()
45 static int hci_extcap_master_config(struct i3c_hci *hci, void __iomem *base) in hci_extcap_master_config()
59 static int hci_extcap_multi_bus(struct i3c_hci *hci, void __iomem *base) in hci_extcap_multi_bus()
68 static int hci_extcap_xfer_modes(struct i3c_hci *hci, void __iomem *base) in hci_extcap_xfer_modes()
88 static int hci_extcap_xfer_rates(struct i3c_hci *hci, void __iomem *base) in hci_extcap_xfer_rates()
116 static int hci_extcap_auto_command(struct i3c_hci *hci, void __iomem *base) in hci_extcap_auto_command()
130 static int hci_extcap_debug(struct i3c_hci *hci, void __iomem *base) in hci_extcap_debug()
137 static int hci_extcap_scheduled_cmd(struct i3c_hci *hci, void __iomem *base) in hci_extcap_scheduled_cmd()
144 static int hci_extcap_non_curr_master(struct i3c_hci *hci, void __iomem *base) in hci_extcap_non_curr_master()
151 static int hci_extcap_ccc_resp_conf(struct i3c_hci *hci, void __iomem *base) in hci_extcap_ccc_resp_conf()
[all …]
/drivers/s390/block/
Ddasd_ioctl.c47 struct dasd_device *base; in dasd_ioctl_enable() local
68 struct dasd_device *base; in dasd_ioctl_disable() local
100 struct dasd_device *base; in dasd_ioctl_quiesce() local
121 struct dasd_device *base; in dasd_ioctl_resume() local
144 struct dasd_device *base; in dasd_ioctl_abortio() local
179 struct dasd_device *base; in dasd_ioctl_allowio() local
200 struct dasd_device *base; in dasd_format() local
238 struct dasd_device *base; in dasd_check_format() local
258 struct dasd_device *base; in dasd_ioctl_format() local
296 struct dasd_device *base; in dasd_ioctl_check_format() local
[all …]
/drivers/block/
Dswim.c63 #define swim_write(base, reg, v) out_8(&(base)->write_##reg, (v)) argument
64 #define swim_read(base, reg) in_8(&(base)->read_##reg) argument
87 #define iwm_write(base, reg, v) out_8(&(base)->reg, (v)) argument
88 #define iwm_read(base, reg) in_8(&(base)->reg) argument
211 struct swim __iomem *base; member
223 static inline void set_swim_mode(struct swim __iomem *base, int enable) in set_swim_mode()
248 static inline int get_swim_mode(struct swim __iomem *base) in get_swim_mode()
270 static inline void swim_select(struct swim __iomem *base, int sel) in swim_select()
279 static inline void swim_action(struct swim __iomem *base, int action) in swim_action()
295 static inline int swim_readbit(struct swim __iomem *base, int bit) in swim_readbit()
[all …]
/drivers/gpu/drm/hisilicon/kirin/
Dkirin_drm_ade.c43 void __iomem *base; member
94 static void ade_update_reload_bit(void __iomem *base, u32 bit_num, u32 val) in ade_update_reload_bit()
105 static u32 ade_read_reload_bit(void __iomem *base, u32 bit_num) in ade_read_reload_bit()
118 void __iomem *base = ctx->base; in ade_init() local
174 void __iomem *base = ctx->base; in ade_ldi_set_mode() local
248 void __iomem *base = ctx->base; in ade_power_down() local
279 void __iomem *base = ctx->base; in ade_crtc_enable_vblank() local
294 void __iomem *base = ctx->base; in ade_crtc_disable_vblank() local
309 void __iomem *base = ctx->base; in ade_irq_handler() local
327 void __iomem *base = ctx->base; in ade_display_enable() local
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
Dnv50.c32 nv50_bar_flush(struct nvkm_bar *base) in nv50_bar_flush()
47 nv50_bar_bar1_vmm(struct nvkm_bar *base) in nv50_bar_bar1_vmm()
53 nv50_bar_bar1_wait(struct nvkm_bar *base) in nv50_bar_bar1_wait()
65 nv50_bar_bar1_init(struct nvkm_bar *base) in nv50_bar_bar1_init()
73 nv50_bar_bar2_vmm(struct nvkm_bar *base) in nv50_bar_bar2_vmm()
85 nv50_bar_bar2_init(struct nvkm_bar *base) in nv50_bar_bar2_init()
95 nv50_bar_init(struct nvkm_bar *base) in nv50_bar_init()
106 nv50_bar_oneinit(struct nvkm_bar *base) in nv50_bar_oneinit()
204 nv50_bar_dtor(struct nvkm_bar *base) in nv50_bar_dtor()
/drivers/gpio/
Dgpio-winbond.c131 unsigned long base; member
142 static int winbond_sio_enter(unsigned long base) in winbond_sio_enter()
157 static void winbond_sio_select_logical(unsigned long base, u8 dev) in winbond_sio_select_logical()
163 static void winbond_sio_leave(unsigned long base) in winbond_sio_leave()
170 static void winbond_sio_reg_write(unsigned long base, u8 reg, u8 data) in winbond_sio_reg_write()
176 static u8 winbond_sio_reg_read(unsigned long base, u8 reg) in winbond_sio_reg_read()
182 static void winbond_sio_reg_bset(unsigned long base, u8 reg, u8 bit) in winbond_sio_reg_bset()
191 static void winbond_sio_reg_bclear(unsigned long base, u8 reg, u8 bit) in winbond_sio_reg_bclear()
200 static bool winbond_sio_reg_btest(unsigned long base, u8 reg, u8 bit) in winbond_sio_reg_btest()
385 unsigned long *base = gpiochip_get_data(gc); in winbond_gpio_get() local
[all …]
/drivers/fpga/
Ddfl-fme-error.c46 void __iomem *base; in pcie0_errors_show() local
63 void __iomem *base; in pcie0_errors_store() local
91 void __iomem *base; in pcie1_errors_show() local
108 void __iomem *base; in pcie1_errors_store() local
135 void __iomem *base; in nonfatal_errors_show() local
147 void __iomem *base; in catfatal_errors_show() local
160 void __iomem *base; in inject_errors_show() local
178 void __iomem *base; in inject_errors_store() local
205 void __iomem *base; in fme_errors_show() local
222 void __iomem *base; in fme_errors_store() local
[all …]
/drivers/char/hw_random/
Dhistb-rng.c26 void __iomem *base; member
34 static int histb_rng_wait(void __iomem *base) in histb_rng_wait()
42 static void histb_rng_init(void __iomem *base, unsigned int depth) in histb_rng_init()
63 void __iomem *base = priv->base; in histb_rng_read() local
81 static unsigned int histb_rng_get_depth(void __iomem *base) in histb_rng_get_depth()
90 void __iomem *base = priv->base; in depth_show() local
100 void __iomem *base = priv->base; in depth_store() local
123 void __iomem *base; in histb_rng_probe() local

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