1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_CORE_H__ 7 #define __INTEL_DISPLAY_CORE_H__ 8 9 #include <linux/list.h> 10 #include <linux/llist.h> 11 #include <linux/mutex.h> 12 #include <linux/types.h> 13 #include <linux/wait.h> 14 #include <linux/workqueue.h> 15 16 #include <drm/drm_connector.h> 17 #include <drm/drm_modeset_lock.h> 18 19 #include "intel_cdclk.h" 20 #include "intel_display_device.h" 21 #include "intel_display_limits.h" 22 #include "intel_display_power.h" 23 #include "intel_dpll_mgr.h" 24 #include "intel_fbc.h" 25 #include "intel_global_state.h" 26 #include "intel_gmbus.h" 27 #include "intel_opregion.h" 28 #include "intel_wm_types.h" 29 30 struct drm_i915_private; 31 struct drm_property; 32 struct drm_property_blob; 33 struct i915_audio_component; 34 struct i915_hdcp_arbiter; 35 struct intel_atomic_state; 36 struct intel_audio_funcs; 37 struct intel_cdclk_funcs; 38 struct intel_cdclk_vals; 39 struct intel_color_funcs; 40 struct intel_crtc; 41 struct intel_crtc_state; 42 struct intel_dmc; 43 struct intel_dpll_funcs; 44 struct intel_dpll_mgr; 45 struct intel_fbdev; 46 struct intel_fdi_funcs; 47 struct intel_hotplug_funcs; 48 struct intel_initial_plane_config; 49 struct intel_overlay; 50 51 /* Amount of SAGV/QGV points, BSpec precisely defines this */ 52 #define I915_NUM_QGV_POINTS 8 53 54 /* Amount of PSF GV points, BSpec precisely defines this */ 55 #define I915_NUM_PSF_GV_POINTS 3 56 57 struct intel_display_funcs { 58 /* 59 * Returns the active state of the crtc, and if the crtc is active, 60 * fills out the pipe-config with the hw state. 61 */ 62 bool (*get_pipe_config)(struct intel_crtc *, 63 struct intel_crtc_state *); 64 void (*get_initial_plane_config)(struct intel_crtc *, 65 struct intel_initial_plane_config *); 66 void (*crtc_enable)(struct intel_atomic_state *state, 67 struct intel_crtc *crtc); 68 void (*crtc_disable)(struct intel_atomic_state *state, 69 struct intel_crtc *crtc); 70 void (*commit_modeset_enables)(struct intel_atomic_state *state); 71 }; 72 73 /* functions used for watermark calcs for display. */ 74 struct intel_wm_funcs { 75 /* update_wm is for legacy wm management */ 76 void (*update_wm)(struct drm_i915_private *dev_priv); 77 int (*compute_pipe_wm)(struct intel_atomic_state *state, 78 struct intel_crtc *crtc); 79 int (*compute_intermediate_wm)(struct intel_atomic_state *state, 80 struct intel_crtc *crtc); 81 void (*initial_watermarks)(struct intel_atomic_state *state, 82 struct intel_crtc *crtc); 83 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 84 struct intel_crtc *crtc); 85 void (*optimize_watermarks)(struct intel_atomic_state *state, 86 struct intel_crtc *crtc); 87 int (*compute_global_watermarks)(struct intel_atomic_state *state); 88 void (*get_hw_state)(struct drm_i915_private *i915); 89 }; 90 91 struct intel_audio_state { 92 struct intel_encoder *encoder; 93 u8 eld[MAX_ELD_BYTES]; 94 }; 95 96 struct intel_audio { 97 /* hda/i915 audio component */ 98 struct i915_audio_component *component; 99 bool component_registered; 100 /* mutex for audio/video sync */ 101 struct mutex mutex; 102 int power_refcount; 103 u32 freq_cntrl; 104 105 /* current audio state for the audio component hooks */ 106 struct intel_audio_state state[I915_MAX_TRANSCODERS]; 107 108 /* necessary resource sharing with HDMI LPE audio driver. */ 109 struct { 110 struct platform_device *platdev; 111 int irq; 112 } lpe; 113 }; 114 115 /* 116 * dpll and cdclk state is protected by connection_mutex dpll.lock serializes 117 * intel_{prepare,enable,disable}_shared_dpll. Must be global rather than per 118 * dpll, because on some platforms plls share registers. 119 */ 120 struct intel_dpll { 121 struct mutex lock; 122 123 int num_shared_dpll; 124 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 125 const struct intel_dpll_mgr *mgr; 126 127 struct { 128 int nssc; 129 int ssc; 130 } ref_clks; 131 132 /* 133 * Bitmask of PLLs using the PCH SSC, indexed using enum intel_dpll_id. 134 */ 135 u8 pch_ssc_use; 136 }; 137 138 struct intel_frontbuffer_tracking { 139 spinlock_t lock; 140 141 /* 142 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 143 * scheduled flips. 144 */ 145 unsigned busy_bits; 146 unsigned flip_bits; 147 }; 148 149 struct intel_hotplug { 150 struct delayed_work hotplug_work; 151 152 const u32 *hpd, *pch_hpd; 153 154 struct { 155 unsigned long last_jiffies; 156 int count; 157 enum { 158 HPD_ENABLED = 0, 159 HPD_DISABLED = 1, 160 HPD_MARK_DISABLED = 2 161 } state; 162 } stats[HPD_NUM_PINS]; 163 u32 event_bits; 164 u32 retry_bits; 165 struct delayed_work reenable_work; 166 167 u32 long_port_mask; 168 u32 short_port_mask; 169 struct work_struct dig_port_work; 170 171 struct work_struct poll_init_work; 172 bool poll_enabled; 173 174 unsigned int hpd_storm_threshold; 175 /* Whether or not to count short HPD IRQs in HPD storms */ 176 u8 hpd_short_storm_enabled; 177 178 /* 179 * if we get a HPD irq from DP and a HPD irq from non-DP 180 * the non-DP HPD could block the workqueue on a mode config 181 * mutex getting, that userspace may have taken. However 182 * userspace is waiting on the DP workqueue to run which is 183 * blocked behind the non-DP one. 184 */ 185 struct workqueue_struct *dp_wq; 186 187 /* 188 * Flag to track if long HPDs need not to be processed 189 * 190 * Some panels generate long HPDs while keep connected to the port. 191 * This can cause issues with CI tests results. In CI systems we 192 * don't expect to disconnect the panels and could ignore the long 193 * HPDs generated from the faulty panels. This flag can be used as 194 * cue to ignore the long HPDs and can be set / unset using debugfs. 195 */ 196 bool ignore_long_hpd; 197 }; 198 199 struct intel_vbt_data { 200 /* bdb version */ 201 u16 version; 202 203 /* Feature bits */ 204 unsigned int int_tv_support:1; 205 unsigned int int_crt_support:1; 206 unsigned int lvds_use_ssc:1; 207 unsigned int int_lvds_support:1; 208 unsigned int display_clock_mode:1; 209 unsigned int fdi_rx_polarity_inverted:1; 210 int lvds_ssc_freq; 211 enum drm_panel_orientation orientation; 212 213 bool override_afc_startup; 214 u8 override_afc_startup_val; 215 216 int crt_ddc_pin; 217 218 struct list_head display_devices; 219 struct list_head bdb_blocks; 220 221 struct sdvo_device_mapping { 222 u8 initialized; 223 u8 dvo_port; 224 u8 slave_addr; 225 u8 dvo_wiring; 226 u8 i2c_pin; 227 u8 ddc_pin; 228 } sdvo_mappings[2]; 229 }; 230 231 struct intel_wm { 232 /* 233 * Raw watermark latency values: 234 * in 0.1us units for WM0, 235 * in 0.5us units for WM1+. 236 */ 237 /* primary */ 238 u16 pri_latency[5]; 239 /* sprite */ 240 u16 spr_latency[5]; 241 /* cursor */ 242 u16 cur_latency[5]; 243 /* 244 * Raw watermark memory latency values 245 * for SKL for all 8 levels 246 * in 1us units. 247 */ 248 u16 skl_latency[8]; 249 250 /* current hardware state */ 251 union { 252 struct ilk_wm_values hw; 253 struct vlv_wm_values vlv; 254 struct g4x_wm_values g4x; 255 }; 256 257 u8 num_levels; 258 259 /* 260 * Should be held around atomic WM register writing; also 261 * protects * intel_crtc->wm.active and 262 * crtc_state->wm.need_postvbl_update. 263 */ 264 struct mutex wm_mutex; 265 266 bool ipc_enabled; 267 }; 268 269 struct intel_display { 270 /* Display functions */ 271 struct { 272 /* Top level crtc-ish functions */ 273 const struct intel_display_funcs *display; 274 275 /* Display CDCLK functions */ 276 const struct intel_cdclk_funcs *cdclk; 277 278 /* Display pll funcs */ 279 const struct intel_dpll_funcs *dpll; 280 281 /* irq display functions */ 282 const struct intel_hotplug_funcs *hotplug; 283 284 /* pm display functions */ 285 const struct intel_wm_funcs *wm; 286 287 /* fdi display functions */ 288 const struct intel_fdi_funcs *fdi; 289 290 /* Display internal color functions */ 291 const struct intel_color_funcs *color; 292 293 /* Display internal audio functions */ 294 const struct intel_audio_funcs *audio; 295 } funcs; 296 297 /* Grouping using anonymous structs. Keep sorted. */ 298 struct intel_atomic_helper { 299 struct llist_head free_list; 300 struct work_struct free_work; 301 } atomic_helper; 302 303 struct { 304 /* backlight registers and fields in struct intel_panel */ 305 struct mutex lock; 306 } backlight; 307 308 struct { 309 struct intel_global_obj obj; 310 311 struct intel_bw_info { 312 /* for each QGV point */ 313 unsigned int deratedbw[I915_NUM_QGV_POINTS]; 314 /* for each PSF GV point */ 315 unsigned int psf_bw[I915_NUM_PSF_GV_POINTS]; 316 /* Peak BW for each QGV point */ 317 unsigned int peakbw[I915_NUM_QGV_POINTS]; 318 u8 num_qgv_points; 319 u8 num_psf_gv_points; 320 u8 num_planes; 321 } max[6]; 322 } bw; 323 324 struct { 325 /* The current hardware cdclk configuration */ 326 struct intel_cdclk_config hw; 327 328 /* cdclk, divider, and ratio table from bspec */ 329 const struct intel_cdclk_vals *table; 330 331 struct intel_global_obj obj; 332 333 unsigned int max_cdclk_freq; 334 } cdclk; 335 336 struct { 337 struct drm_property_blob *glk_linear_degamma_lut; 338 } color; 339 340 struct { 341 /* The current hardware dbuf configuration */ 342 u8 enabled_slices; 343 344 struct intel_global_obj obj; 345 } dbuf; 346 347 struct { 348 wait_queue_head_t waitqueue; 349 350 /* mutex to protect pmdemand programming sequence */ 351 struct mutex lock; 352 353 struct intel_global_obj obj; 354 } pmdemand; 355 356 struct { 357 /* 358 * dkl.phy_lock protects against concurrent access of the 359 * Dekel TypeC PHYs. 360 */ 361 spinlock_t phy_lock; 362 } dkl; 363 364 struct { 365 struct intel_dmc *dmc; 366 intel_wakeref_t wakeref; 367 } dmc; 368 369 struct { 370 /* VLV/CHV/BXT/GLK DSI MMIO register base address */ 371 u32 mmio_base; 372 } dsi; 373 374 struct { 375 /* list of fbdev register on this device */ 376 struct intel_fbdev *fbdev; 377 struct work_struct suspend_work; 378 } fbdev; 379 380 struct { 381 unsigned int pll_freq; 382 u32 rx_config; 383 } fdi; 384 385 struct { 386 struct list_head obj_list; 387 } global; 388 389 struct { 390 /* 391 * Base address of where the gmbus and gpio blocks are located 392 * (either on PCH or on SoC for platforms without PCH). 393 */ 394 u32 mmio_base; 395 396 /* 397 * gmbus.mutex protects against concurrent usage of the single 398 * hw gmbus controller on different i2c buses. 399 */ 400 struct mutex mutex; 401 402 struct intel_gmbus *bus[GMBUS_NUM_PINS]; 403 404 wait_queue_head_t wait_queue; 405 } gmbus; 406 407 struct { 408 struct i915_hdcp_arbiter *arbiter; 409 bool comp_added; 410 411 /* 412 * HDCP message struct for allocation of memory which can be 413 * reused when sending message to gsc cs. 414 * this is only populated post Meteorlake 415 */ 416 struct intel_hdcp_gsc_message *hdcp_message; 417 /* Mutex to protect the above hdcp related values. */ 418 struct mutex hdcp_mutex; 419 } hdcp; 420 421 struct { 422 /* 423 * HTI (aka HDPORT) state read during initial hw readout. Most 424 * platforms don't have HTI, so this will just stay 0. Those 425 * that do will use this later to figure out which PLLs and PHYs 426 * are unavailable for driver usage. 427 */ 428 u32 state; 429 } hti; 430 431 struct { 432 /* Access with DISPLAY_INFO() */ 433 const struct intel_display_device_info *__device_info; 434 435 /* Access with DISPLAY_RUNTIME_INFO() */ 436 struct intel_display_runtime_info __runtime_info; 437 } info; 438 439 struct { 440 bool false_color; 441 } ips; 442 443 struct { 444 struct i915_power_domains domains; 445 446 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 447 u32 chv_phy_control; 448 449 /* perform PHY state sanity checks? */ 450 bool chv_phy_assert[2]; 451 } power; 452 453 struct { 454 u32 mmio_base; 455 456 /* protects panel power sequencer state */ 457 struct mutex mutex; 458 } pps; 459 460 struct { 461 struct drm_property *broadcast_rgb; 462 struct drm_property *force_audio; 463 } properties; 464 465 struct { 466 unsigned long mask; 467 } quirks; 468 469 struct { 470 /* restore state for suspend/resume and display reset */ 471 struct drm_atomic_state *modeset_state; 472 struct drm_modeset_acquire_ctx reset_ctx; 473 } restore; 474 475 struct { 476 enum { 477 I915_SAGV_UNKNOWN = 0, 478 I915_SAGV_DISABLED, 479 I915_SAGV_ENABLED, 480 I915_SAGV_NOT_CONTROLLED 481 } status; 482 483 u32 block_time_us; 484 } sagv; 485 486 struct { 487 /* 488 * DG2: Mask of PHYs that were not calibrated by the firmware 489 * and should not be used. 490 */ 491 u8 phy_failed_calibration; 492 } snps; 493 494 struct { 495 /* 496 * Shadows for CHV DPLL_MD regs to keep the state 497 * checker somewhat working in the presence hardware 498 * crappiness (can't read out DPLL_MD for pipes B & C). 499 */ 500 u32 chv_dpll_md[I915_MAX_PIPES]; 501 u32 bxt_phy_grc; 502 } state; 503 504 struct { 505 /* ordered wq for modesets */ 506 struct workqueue_struct *modeset; 507 508 /* unbound hipri wq for page flips/plane updates */ 509 struct workqueue_struct *flip; 510 } wq; 511 512 /* Grouping using named structs. Keep sorted. */ 513 struct intel_audio audio; 514 struct intel_dpll dpll; 515 struct intel_fbc *fbc[I915_MAX_FBCS]; 516 struct intel_frontbuffer_tracking fb_tracking; 517 struct intel_hotplug hotplug; 518 struct intel_opregion opregion; 519 struct intel_overlay *overlay; 520 struct intel_vbt_data vbt; 521 struct intel_wm wm; 522 }; 523 524 #endif /* __INTEL_DISPLAY_CORE_H__ */ 525