1 /*
2 * Copyright 2011 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "disp.h"
25 #include "atom.h"
26 #include "core.h"
27 #include "head.h"
28 #include "wndw.h"
29 #include "handles.h"
30
31 #include <linux/dma-mapping.h>
32 #include <linux/hdmi.h>
33 #include <linux/component.h>
34 #include <linux/iopoll.h>
35
36 #include <drm/display/drm_dp_helper.h>
37 #include <drm/display/drm_scdc_helper.h>
38 #include <drm/drm_atomic.h>
39 #include <drm/drm_atomic_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_fb_helper.h>
42 #include <drm/drm_probe_helper.h>
43 #include <drm/drm_vblank.h>
44
45 #include <nvif/push507c.h>
46
47 #include <nvif/class.h>
48 #include <nvif/cl0002.h>
49 #include <nvif/event.h>
50 #include <nvif/if0012.h>
51 #include <nvif/if0014.h>
52 #include <nvif/timer.h>
53
54 #include <nvhw/class/cl507c.h>
55 #include <nvhw/class/cl507d.h>
56 #include <nvhw/class/cl837d.h>
57 #include <nvhw/class/cl887d.h>
58 #include <nvhw/class/cl907d.h>
59 #include <nvhw/class/cl917d.h>
60
61 #include "nouveau_drv.h"
62 #include "nouveau_dma.h"
63 #include "nouveau_gem.h"
64 #include "nouveau_connector.h"
65 #include "nouveau_encoder.h"
66 #include "nouveau_fence.h"
67 #include "nv50_display.h"
68
69 #include <subdev/bios/dp.h>
70
71 /******************************************************************************
72 * EVO channel
73 *****************************************************************************/
74
75 static int
nv50_chan_create(struct nvif_device * device,struct nvif_object * disp,const s32 * oclass,u8 head,void * data,u32 size,struct nv50_chan * chan)76 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
77 const s32 *oclass, u8 head, void *data, u32 size,
78 struct nv50_chan *chan)
79 {
80 struct nvif_sclass *sclass;
81 int ret, i, n;
82
83 chan->device = device;
84
85 ret = n = nvif_object_sclass_get(disp, &sclass);
86 if (ret < 0)
87 return ret;
88
89 while (oclass[0]) {
90 for (i = 0; i < n; i++) {
91 if (sclass[i].oclass == oclass[0]) {
92 ret = nvif_object_ctor(disp, "kmsChan", 0,
93 oclass[0], data, size,
94 &chan->user);
95 if (ret == 0)
96 nvif_object_map(&chan->user, NULL, 0);
97 nvif_object_sclass_put(&sclass);
98 return ret;
99 }
100 }
101 oclass++;
102 }
103
104 nvif_object_sclass_put(&sclass);
105 return -ENOSYS;
106 }
107
108 static void
nv50_chan_destroy(struct nv50_chan * chan)109 nv50_chan_destroy(struct nv50_chan *chan)
110 {
111 nvif_object_dtor(&chan->user);
112 }
113
114 /******************************************************************************
115 * DMA EVO channel
116 *****************************************************************************/
117
118 void
nv50_dmac_destroy(struct nv50_dmac * dmac)119 nv50_dmac_destroy(struct nv50_dmac *dmac)
120 {
121 nvif_object_dtor(&dmac->vram);
122 nvif_object_dtor(&dmac->sync);
123
124 nv50_chan_destroy(&dmac->base);
125
126 nvif_mem_dtor(&dmac->_push.mem);
127 }
128
129 static void
nv50_dmac_kick(struct nvif_push * push)130 nv50_dmac_kick(struct nvif_push *push)
131 {
132 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push);
133
134 dmac->cur = push->cur - (u32 __iomem *)dmac->_push.mem.object.map.ptr;
135 if (dmac->put != dmac->cur) {
136 /* Push buffer fetches are not coherent with BAR1, we need to ensure
137 * writes have been flushed right through to VRAM before writing PUT.
138 */
139 if (dmac->push->mem.type & NVIF_MEM_VRAM) {
140 struct nvif_device *device = dmac->base.device;
141 nvif_wr32(&device->object, 0x070000, 0x00000001);
142 nvif_msec(device, 2000,
143 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
144 break;
145 );
146 }
147
148 NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur);
149 dmac->put = dmac->cur;
150 }
151
152 push->bgn = push->cur;
153 }
154
155 static int
nv50_dmac_free(struct nv50_dmac * dmac)156 nv50_dmac_free(struct nv50_dmac *dmac)
157 {
158 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
159 if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */
160 return get - dmac->cur - 5;
161 return dmac->max - dmac->cur;
162 }
163
164 static int
nv50_dmac_wind(struct nv50_dmac * dmac)165 nv50_dmac_wind(struct nv50_dmac *dmac)
166 {
167 /* Wait for GET to depart from the beginning of the push buffer to
168 * prevent writing PUT == GET, which would be ignored by HW.
169 */
170 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
171 if (get == 0) {
172 /* Corner-case, HW idle, but non-committed work pending. */
173 if (dmac->put == 0)
174 nv50_dmac_kick(dmac->push);
175
176 if (nvif_msec(dmac->base.device, 2000,
177 if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0))
178 break;
179 ) < 0)
180 return -ETIMEDOUT;
181 }
182
183 PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0));
184 dmac->cur = 0;
185 return 0;
186 }
187
188 static int
nv50_dmac_wait(struct nvif_push * push,u32 size)189 nv50_dmac_wait(struct nvif_push *push, u32 size)
190 {
191 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push);
192 int free;
193
194 if (WARN_ON(size > dmac->max))
195 return -EINVAL;
196
197 dmac->cur = push->cur - (u32 __iomem *)dmac->_push.mem.object.map.ptr;
198 if (dmac->cur + size >= dmac->max) {
199 int ret = nv50_dmac_wind(dmac);
200 if (ret)
201 return ret;
202
203 push->cur = dmac->_push.mem.object.map.ptr;
204 push->cur = push->cur + dmac->cur;
205 nv50_dmac_kick(push);
206 }
207
208 if (nvif_msec(dmac->base.device, 2000,
209 if ((free = nv50_dmac_free(dmac)) >= size)
210 break;
211 ) < 0) {
212 WARN_ON(1);
213 return -ETIMEDOUT;
214 }
215
216 push->bgn = dmac->_push.mem.object.map.ptr;
217 push->bgn = push->bgn + dmac->cur;
218 push->cur = push->bgn;
219 push->end = push->cur + free;
220 return 0;
221 }
222
223 MODULE_PARM_DESC(kms_vram_pushbuf, "Place EVO/NVD push buffers in VRAM (default: auto)");
224 static int nv50_dmac_vram_pushbuf = -1;
225 module_param_named(kms_vram_pushbuf, nv50_dmac_vram_pushbuf, int, 0400);
226
227 int
nv50_dmac_create(struct nvif_device * device,struct nvif_object * disp,const s32 * oclass,u8 head,void * data,u32 size,s64 syncbuf,struct nv50_dmac * dmac)228 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
229 const s32 *oclass, u8 head, void *data, u32 size, s64 syncbuf,
230 struct nv50_dmac *dmac)
231 {
232 struct nouveau_cli *cli = (void *)device->object.client;
233 struct nvif_disp_chan_v0 *args = data;
234 u8 type = NVIF_MEM_COHERENT;
235 int ret;
236
237 mutex_init(&dmac->lock);
238
239 /* Pascal added support for 47-bit physical addresses, but some
240 * parts of EVO still only accept 40-bit PAs.
241 *
242 * To avoid issues on systems with large amounts of RAM, and on
243 * systems where an IOMMU maps pages at a high address, we need
244 * to allocate push buffers in VRAM instead.
245 *
246 * This appears to match NVIDIA's behaviour on Pascal.
247 */
248 if ((nv50_dmac_vram_pushbuf > 0) ||
249 (nv50_dmac_vram_pushbuf < 0 && device->info.family == NV_DEVICE_INFO_V0_PASCAL))
250 type |= NVIF_MEM_VRAM;
251
252 ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000,
253 &dmac->_push.mem);
254 if (ret)
255 return ret;
256
257 dmac->ptr = dmac->_push.mem.object.map.ptr;
258 dmac->_push.wait = nv50_dmac_wait;
259 dmac->_push.kick = nv50_dmac_kick;
260 dmac->push = &dmac->_push;
261 dmac->push->bgn = dmac->_push.mem.object.map.ptr;
262 dmac->push->cur = dmac->push->bgn;
263 dmac->push->end = dmac->push->bgn;
264 dmac->max = 0x1000/4 - 1;
265
266 /* EVO channels are affected by a HW bug where the last 12 DWORDs
267 * of the push buffer aren't able to be used safely.
268 */
269 if (disp->oclass < GV100_DISP)
270 dmac->max -= 12;
271
272 args->pushbuf = nvif_handle(&dmac->_push.mem.object);
273
274 ret = nv50_chan_create(device, disp, oclass, head, data, size,
275 &dmac->base);
276 if (ret)
277 return ret;
278
279 if (syncbuf < 0)
280 return 0;
281
282 ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF,
283 NV_DMA_IN_MEMORY,
284 &(struct nv_dma_v0) {
285 .target = NV_DMA_V0_TARGET_VRAM,
286 .access = NV_DMA_V0_ACCESS_RDWR,
287 .start = syncbuf + 0x0000,
288 .limit = syncbuf + 0x0fff,
289 }, sizeof(struct nv_dma_v0),
290 &dmac->sync);
291 if (ret)
292 return ret;
293
294 ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM,
295 NV_DMA_IN_MEMORY,
296 &(struct nv_dma_v0) {
297 .target = NV_DMA_V0_TARGET_VRAM,
298 .access = NV_DMA_V0_ACCESS_RDWR,
299 .start = 0,
300 .limit = device->info.ram_user - 1,
301 }, sizeof(struct nv_dma_v0),
302 &dmac->vram);
303 if (ret)
304 return ret;
305
306 return ret;
307 }
308
309 /******************************************************************************
310 * Output path helpers
311 *****************************************************************************/
312 static void
nv50_outp_dump_caps(struct nouveau_drm * drm,struct nouveau_encoder * outp)313 nv50_outp_dump_caps(struct nouveau_drm *drm,
314 struct nouveau_encoder *outp)
315 {
316 NV_DEBUG(drm, "%s caps: dp_interlace=%d\n",
317 outp->base.base.name, outp->caps.dp_interlace);
318 }
319
320 static int
nv50_outp_atomic_check_view(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,struct drm_display_mode * native_mode)321 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
322 struct drm_crtc_state *crtc_state,
323 struct drm_connector_state *conn_state,
324 struct drm_display_mode *native_mode)
325 {
326 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
327 struct drm_display_mode *mode = &crtc_state->mode;
328 struct drm_connector *connector = conn_state->connector;
329 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
330 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
331
332 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
333 asyc->scaler.full = false;
334 if (!native_mode)
335 return 0;
336
337 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
338 switch (connector->connector_type) {
339 case DRM_MODE_CONNECTOR_LVDS:
340 case DRM_MODE_CONNECTOR_eDP:
341 /* Don't force scaler for EDID modes with
342 * same size as the native one (e.g. different
343 * refresh rate)
344 */
345 if (mode->hdisplay == native_mode->hdisplay &&
346 mode->vdisplay == native_mode->vdisplay &&
347 mode->type & DRM_MODE_TYPE_DRIVER)
348 break;
349 mode = native_mode;
350 asyc->scaler.full = true;
351 break;
352 default:
353 break;
354 }
355 } else {
356 mode = native_mode;
357 }
358
359 if (!drm_mode_equal(adjusted_mode, mode)) {
360 drm_mode_copy(adjusted_mode, mode);
361 crtc_state->mode_changed = true;
362 }
363
364 return 0;
365 }
366
367 static void
nv50_outp_atomic_fix_depth(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state)368 nv50_outp_atomic_fix_depth(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state)
369 {
370 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
371 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
372 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
373 unsigned int max_rate, mode_rate;
374
375 switch (nv_encoder->dcb->type) {
376 case DCB_OUTPUT_DP:
377 max_rate = nv_encoder->dp.link_nr * nv_encoder->dp.link_bw;
378
379 /* we don't support more than 10 anyway */
380 asyh->or.bpc = min_t(u8, asyh->or.bpc, 10);
381
382 /* reduce the bpc until it works out */
383 while (asyh->or.bpc > 6) {
384 mode_rate = DIV_ROUND_UP(mode->clock * asyh->or.bpc * 3, 8);
385 if (mode_rate <= max_rate)
386 break;
387
388 asyh->or.bpc -= 2;
389 }
390 break;
391 default:
392 break;
393 }
394 }
395
396 static int
nv50_outp_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)397 nv50_outp_atomic_check(struct drm_encoder *encoder,
398 struct drm_crtc_state *crtc_state,
399 struct drm_connector_state *conn_state)
400 {
401 struct drm_connector *connector = conn_state->connector;
402 struct nouveau_connector *nv_connector = nouveau_connector(connector);
403 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
404 int ret;
405
406 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
407 nv_connector->native_mode);
408 if (ret)
409 return ret;
410
411 if (crtc_state->mode_changed || crtc_state->connectors_changed)
412 asyh->or.bpc = connector->display_info.bpc;
413
414 /* We might have to reduce the bpc */
415 nv50_outp_atomic_fix_depth(encoder, crtc_state);
416
417 return 0;
418 }
419
420 struct nouveau_connector *
nv50_outp_get_new_connector(struct drm_atomic_state * state,struct nouveau_encoder * outp)421 nv50_outp_get_new_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp)
422 {
423 struct drm_connector *connector;
424 struct drm_connector_state *connector_state;
425 struct drm_encoder *encoder = to_drm_encoder(outp);
426 int i;
427
428 for_each_new_connector_in_state(state, connector, connector_state, i) {
429 if (connector_state->best_encoder == encoder)
430 return nouveau_connector(connector);
431 }
432
433 return NULL;
434 }
435
436 struct nouveau_connector *
nv50_outp_get_old_connector(struct drm_atomic_state * state,struct nouveau_encoder * outp)437 nv50_outp_get_old_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp)
438 {
439 struct drm_connector *connector;
440 struct drm_connector_state *connector_state;
441 struct drm_encoder *encoder = to_drm_encoder(outp);
442 int i;
443
444 for_each_old_connector_in_state(state, connector, connector_state, i) {
445 if (connector_state->best_encoder == encoder)
446 return nouveau_connector(connector);
447 }
448
449 return NULL;
450 }
451
452 static struct nouveau_crtc *
nv50_outp_get_new_crtc(const struct drm_atomic_state * state,const struct nouveau_encoder * outp)453 nv50_outp_get_new_crtc(const struct drm_atomic_state *state, const struct nouveau_encoder *outp)
454 {
455 struct drm_crtc *crtc;
456 struct drm_crtc_state *crtc_state;
457 const u32 mask = drm_encoder_mask(&outp->base.base);
458 int i;
459
460 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
461 if (crtc_state->encoder_mask & mask)
462 return nouveau_crtc(crtc);
463 }
464
465 return NULL;
466 }
467
468 /******************************************************************************
469 * DAC
470 *****************************************************************************/
471 static void
nv50_dac_atomic_disable(struct drm_encoder * encoder,struct drm_atomic_state * state)472 nv50_dac_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
473 {
474 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
475 struct nv50_core *core = nv50_disp(encoder->dev)->core;
476 const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE);
477
478 core->func->dac->ctrl(core, nv_encoder->outp.or.id, ctrl, NULL);
479 nv_encoder->crtc = NULL;
480 nvif_outp_release(&nv_encoder->outp);
481 }
482
483 static void
nv50_dac_atomic_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)484 nv50_dac_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
485 {
486 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
487 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
488 struct nv50_head_atom *asyh =
489 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
490 struct nv50_core *core = nv50_disp(encoder->dev)->core;
491 u32 ctrl = 0;
492
493 switch (nv_crtc->index) {
494 case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break;
495 case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break;
496 case 2: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break;
497 case 3: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break;
498 default:
499 WARN_ON(1);
500 break;
501 }
502
503 ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT);
504
505 nvif_outp_acquire_rgb_crt(&nv_encoder->outp);
506
507 core->func->dac->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh);
508 asyh->or.depth = 0;
509
510 nv_encoder->crtc = &nv_crtc->base;
511 }
512
513 static enum drm_connector_status
nv50_dac_detect(struct drm_encoder * encoder,struct drm_connector * connector)514 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
515 {
516 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
517 u32 loadval;
518 int ret;
519
520 loadval = nouveau_drm(encoder->dev)->vbios.dactestval;
521 if (loadval == 0)
522 loadval = 340;
523
524 ret = nvif_outp_load_detect(&nv_encoder->outp, loadval);
525 if (ret <= 0)
526 return connector_status_disconnected;
527
528 return connector_status_connected;
529 }
530
531 static const struct drm_encoder_helper_funcs
532 nv50_dac_help = {
533 .atomic_check = nv50_outp_atomic_check,
534 .atomic_enable = nv50_dac_atomic_enable,
535 .atomic_disable = nv50_dac_atomic_disable,
536 .detect = nv50_dac_detect
537 };
538
539 static void
nv50_dac_destroy(struct drm_encoder * encoder)540 nv50_dac_destroy(struct drm_encoder *encoder)
541 {
542 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
543
544 nvif_outp_dtor(&nv_encoder->outp);
545
546 drm_encoder_cleanup(encoder);
547 kfree(encoder);
548 }
549
550 static const struct drm_encoder_funcs
551 nv50_dac_func = {
552 .destroy = nv50_dac_destroy,
553 };
554
555 static int
nv50_dac_create(struct drm_connector * connector,struct dcb_output * dcbe)556 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
557 {
558 struct nouveau_drm *drm = nouveau_drm(connector->dev);
559 struct nv50_disp *disp = nv50_disp(connector->dev);
560 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
561 struct nvkm_i2c_bus *bus;
562 struct nouveau_encoder *nv_encoder;
563 struct drm_encoder *encoder;
564 int type = DRM_MODE_ENCODER_DAC;
565
566 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
567 if (!nv_encoder)
568 return -ENOMEM;
569 nv_encoder->dcb = dcbe;
570
571 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
572 if (bus)
573 nv_encoder->i2c = &bus->i2c;
574
575 encoder = to_drm_encoder(nv_encoder);
576 encoder->possible_crtcs = dcbe->heads;
577 encoder->possible_clones = 0;
578 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
579 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
580 drm_encoder_helper_add(encoder, &nv50_dac_help);
581
582 drm_connector_attach_encoder(connector, encoder);
583 return nvif_outp_ctor(disp->disp, nv_encoder->base.base.name, dcbe->id, &nv_encoder->outp);
584 }
585
586 /*
587 * audio component binding for ELD notification
588 */
589 static void
nv50_audio_component_eld_notify(struct drm_audio_component * acomp,int port,int dev_id)590 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port,
591 int dev_id)
592 {
593 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
594 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
595 port, dev_id);
596 }
597
598 static int
nv50_audio_component_get_eld(struct device * kdev,int port,int dev_id,bool * enabled,unsigned char * buf,int max_bytes)599 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id,
600 bool *enabled, unsigned char *buf, int max_bytes)
601 {
602 struct drm_device *drm_dev = dev_get_drvdata(kdev);
603 struct nouveau_drm *drm = nouveau_drm(drm_dev);
604 struct drm_encoder *encoder;
605 struct nouveau_encoder *nv_encoder;
606 struct nouveau_crtc *nv_crtc;
607 int ret = 0;
608
609 *enabled = false;
610
611 mutex_lock(&drm->audio.lock);
612
613 drm_for_each_encoder(encoder, drm->dev) {
614 struct nouveau_connector *nv_connector = NULL;
615
616 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST)
617 continue; /* TODO */
618
619 nv_encoder = nouveau_encoder(encoder);
620 nv_connector = nouveau_connector(nv_encoder->audio.connector);
621 nv_crtc = nouveau_crtc(nv_encoder->crtc);
622
623 if (!nv_crtc || nv_encoder->outp.or.id != port || nv_crtc->index != dev_id)
624 continue;
625
626 *enabled = nv_encoder->audio.enabled;
627 if (*enabled) {
628 ret = drm_eld_size(nv_connector->base.eld);
629 memcpy(buf, nv_connector->base.eld,
630 min(max_bytes, ret));
631 }
632 break;
633 }
634
635 mutex_unlock(&drm->audio.lock);
636
637 return ret;
638 }
639
640 static const struct drm_audio_component_ops nv50_audio_component_ops = {
641 .get_eld = nv50_audio_component_get_eld,
642 };
643
644 static int
nv50_audio_component_bind(struct device * kdev,struct device * hda_kdev,void * data)645 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev,
646 void *data)
647 {
648 struct drm_device *drm_dev = dev_get_drvdata(kdev);
649 struct nouveau_drm *drm = nouveau_drm(drm_dev);
650 struct drm_audio_component *acomp = data;
651
652 if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS)))
653 return -ENOMEM;
654
655 drm_modeset_lock_all(drm_dev);
656 acomp->ops = &nv50_audio_component_ops;
657 acomp->dev = kdev;
658 drm->audio.component = acomp;
659 drm_modeset_unlock_all(drm_dev);
660 return 0;
661 }
662
663 static void
nv50_audio_component_unbind(struct device * kdev,struct device * hda_kdev,void * data)664 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev,
665 void *data)
666 {
667 struct drm_device *drm_dev = dev_get_drvdata(kdev);
668 struct nouveau_drm *drm = nouveau_drm(drm_dev);
669 struct drm_audio_component *acomp = data;
670
671 drm_modeset_lock_all(drm_dev);
672 drm->audio.component = NULL;
673 acomp->ops = NULL;
674 acomp->dev = NULL;
675 drm_modeset_unlock_all(drm_dev);
676 }
677
678 static const struct component_ops nv50_audio_component_bind_ops = {
679 .bind = nv50_audio_component_bind,
680 .unbind = nv50_audio_component_unbind,
681 };
682
683 static void
nv50_audio_component_init(struct nouveau_drm * drm)684 nv50_audio_component_init(struct nouveau_drm *drm)
685 {
686 if (component_add(drm->dev->dev, &nv50_audio_component_bind_ops))
687 return;
688
689 drm->audio.component_registered = true;
690 mutex_init(&drm->audio.lock);
691 }
692
693 static void
nv50_audio_component_fini(struct nouveau_drm * drm)694 nv50_audio_component_fini(struct nouveau_drm *drm)
695 {
696 if (!drm->audio.component_registered)
697 return;
698
699 component_del(drm->dev->dev, &nv50_audio_component_bind_ops);
700 drm->audio.component_registered = false;
701 mutex_destroy(&drm->audio.lock);
702 }
703
704 /******************************************************************************
705 * Audio
706 *****************************************************************************/
707 static bool
nv50_audio_supported(struct drm_encoder * encoder)708 nv50_audio_supported(struct drm_encoder *encoder)
709 {
710 struct nv50_disp *disp = nv50_disp(encoder->dev);
711
712 if (disp->disp->object.oclass <= GT200_DISP ||
713 disp->disp->object.oclass == GT206_DISP)
714 return false;
715
716 return true;
717 }
718
719 static void
nv50_audio_disable(struct drm_encoder * encoder,struct nouveau_crtc * nv_crtc)720 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
721 {
722 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
723 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
724 struct nvif_outp *outp = &nv_encoder->outp;
725
726 if (!nv50_audio_supported(encoder))
727 return;
728
729 mutex_lock(&drm->audio.lock);
730 if (nv_encoder->audio.enabled) {
731 nv_encoder->audio.enabled = false;
732 nv_encoder->audio.connector = NULL;
733 nvif_outp_hda_eld(&nv_encoder->outp, nv_crtc->index, NULL, 0);
734 }
735 mutex_unlock(&drm->audio.lock);
736
737 nv50_audio_component_eld_notify(drm->audio.component, outp->or.id, nv_crtc->index);
738 }
739
740 static void
nv50_audio_enable(struct drm_encoder * encoder,struct nouveau_crtc * nv_crtc,struct nouveau_connector * nv_connector,struct drm_atomic_state * state,struct drm_display_mode * mode)741 nv50_audio_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
742 struct nouveau_connector *nv_connector, struct drm_atomic_state *state,
743 struct drm_display_mode *mode)
744 {
745 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
746 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
747 struct nvif_outp *outp = &nv_encoder->outp;
748
749 if (!nv50_audio_supported(encoder) || !drm_detect_monitor_audio(nv_connector->edid))
750 return;
751
752 mutex_lock(&drm->audio.lock);
753
754 nvif_outp_hda_eld(&nv_encoder->outp, nv_crtc->index, nv_connector->base.eld,
755 drm_eld_size(nv_connector->base.eld));
756 nv_encoder->audio.enabled = true;
757 nv_encoder->audio.connector = &nv_connector->base;
758
759 mutex_unlock(&drm->audio.lock);
760
761 nv50_audio_component_eld_notify(drm->audio.component, outp->or.id, nv_crtc->index);
762 }
763
764 /******************************************************************************
765 * HDMI
766 *****************************************************************************/
767 static void
nv50_hdmi_enable(struct drm_encoder * encoder,struct nouveau_crtc * nv_crtc,struct nouveau_connector * nv_connector,struct drm_atomic_state * state,struct drm_display_mode * mode,bool hda)768 nv50_hdmi_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
769 struct nouveau_connector *nv_connector, struct drm_atomic_state *state,
770 struct drm_display_mode *mode, bool hda)
771 {
772 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
773 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
774 struct drm_hdmi_info *hdmi = &nv_connector->base.display_info.hdmi;
775 union hdmi_infoframe infoframe = { 0 };
776 const u8 rekey = 56; /* binary driver, and tegra, constant */
777 u8 scdc = 0;
778 u32 max_ac_packet;
779 struct {
780 struct nvif_outp_infoframe_v0 infoframe;
781 u8 data[17];
782 } args = { 0 };
783 int ret, size;
784
785 max_ac_packet = mode->htotal - mode->hdisplay;
786 max_ac_packet -= rekey;
787 max_ac_packet -= 18; /* constant from tegra */
788 max_ac_packet /= 32;
789
790 if (hdmi->scdc.scrambling.supported) {
791 const bool high_tmds_clock_ratio = mode->clock > 340000;
792
793 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &scdc);
794 if (ret < 0) {
795 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
796 return;
797 }
798
799 scdc &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
800 if (high_tmds_clock_ratio || hdmi->scdc.scrambling.low_rates)
801 scdc |= SCDC_SCRAMBLING_ENABLE;
802 if (high_tmds_clock_ratio)
803 scdc |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
804
805 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, scdc);
806 if (ret < 0)
807 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
808 scdc, ret);
809 }
810
811 ret = nvif_outp_acquire_tmds(&nv_encoder->outp, nv_crtc->index, true,
812 max_ac_packet, rekey, scdc, hda);
813 if (ret)
814 return;
815
816 /* AVI InfoFrame. */
817 args.infoframe.version = 0;
818 args.infoframe.head = nv_crtc->index;
819
820 if (!drm_hdmi_avi_infoframe_from_display_mode(&infoframe.avi, &nv_connector->base, mode)) {
821 drm_hdmi_avi_infoframe_quant_range(&infoframe.avi, &nv_connector->base, mode,
822 HDMI_QUANTIZATION_RANGE_FULL);
823
824 size = hdmi_infoframe_pack(&infoframe, args.data, ARRAY_SIZE(args.data));
825 } else {
826 size = 0;
827 }
828
829 nvif_outp_infoframe(&nv_encoder->outp, NVIF_OUTP_INFOFRAME_V0_AVI, &args.infoframe, size);
830
831 /* Vendor InfoFrame. */
832 memset(&args.data, 0, sizeof(args.data));
833 if (!drm_hdmi_vendor_infoframe_from_display_mode(&infoframe.vendor.hdmi,
834 &nv_connector->base, mode))
835 size = hdmi_infoframe_pack(&infoframe, args.data, ARRAY_SIZE(args.data));
836 else
837 size = 0;
838
839 nvif_outp_infoframe(&nv_encoder->outp, NVIF_OUTP_INFOFRAME_V0_VSI, &args.infoframe, size);
840
841 nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode);
842 }
843
844 /******************************************************************************
845 * MST
846 *****************************************************************************/
847 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
848 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
849 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
850
851 struct nv50_mstc {
852 struct nv50_mstm *mstm;
853 struct drm_dp_mst_port *port;
854 struct drm_connector connector;
855
856 struct drm_display_mode *native;
857 struct edid *edid;
858 };
859
860 struct nv50_msto {
861 struct drm_encoder encoder;
862
863 /* head is statically assigned on msto creation */
864 struct nv50_head *head;
865 struct nv50_mstc *mstc;
866 bool disabled;
867 bool enabled;
868 };
869
nv50_real_outp(struct drm_encoder * encoder)870 struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder)
871 {
872 struct nv50_msto *msto;
873
874 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
875 return nouveau_encoder(encoder);
876
877 msto = nv50_msto(encoder);
878 if (!msto->mstc)
879 return NULL;
880 return msto->mstc->mstm->outp;
881 }
882
883 static void
nv50_msto_cleanup(struct drm_atomic_state * state,struct drm_dp_mst_topology_state * mst_state,struct drm_dp_mst_topology_mgr * mgr,struct nv50_msto * msto)884 nv50_msto_cleanup(struct drm_atomic_state *state,
885 struct drm_dp_mst_topology_state *mst_state,
886 struct drm_dp_mst_topology_mgr *mgr,
887 struct nv50_msto *msto)
888 {
889 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
890 struct drm_dp_mst_atomic_payload *payload =
891 drm_atomic_get_mst_payload_state(mst_state, msto->mstc->port);
892
893 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
894
895 if (msto->disabled) {
896 msto->mstc = NULL;
897 msto->disabled = false;
898 } else if (msto->enabled) {
899 drm_dp_add_payload_part2(mgr, state, payload);
900 msto->enabled = false;
901 }
902 }
903
904 static void
nv50_msto_prepare(struct drm_atomic_state * state,struct drm_dp_mst_topology_state * mst_state,struct drm_dp_mst_topology_mgr * mgr,struct nv50_msto * msto)905 nv50_msto_prepare(struct drm_atomic_state *state,
906 struct drm_dp_mst_topology_state *mst_state,
907 struct drm_dp_mst_topology_mgr *mgr,
908 struct nv50_msto *msto)
909 {
910 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
911 struct nv50_mstc *mstc = msto->mstc;
912 struct nv50_mstm *mstm = mstc->mstm;
913 struct drm_dp_mst_topology_state *old_mst_state;
914 struct drm_dp_mst_atomic_payload *payload, *old_payload;
915
916 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
917
918 old_mst_state = drm_atomic_get_old_mst_topology_state(state, mgr);
919
920 payload = drm_atomic_get_mst_payload_state(mst_state, mstc->port);
921 old_payload = drm_atomic_get_mst_payload_state(old_mst_state, mstc->port);
922
923 // TODO: Figure out if we want to do a better job of handling VCPI allocation failures here?
924 if (msto->disabled) {
925 drm_dp_remove_payload(mgr, mst_state, old_payload, payload);
926
927 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index, 0, 0, 0, 0);
928 } else {
929 if (msto->enabled)
930 drm_dp_add_payload_part1(mgr, mst_state, payload);
931
932 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index,
933 payload->vc_start_slot, payload->time_slots,
934 payload->pbn, payload->time_slots * mst_state->pbn_div);
935 }
936 }
937
938 static int
nv50_msto_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)939 nv50_msto_atomic_check(struct drm_encoder *encoder,
940 struct drm_crtc_state *crtc_state,
941 struct drm_connector_state *conn_state)
942 {
943 struct drm_atomic_state *state = crtc_state->state;
944 struct drm_connector *connector = conn_state->connector;
945 struct drm_dp_mst_topology_state *mst_state;
946 struct nv50_mstc *mstc = nv50_mstc(connector);
947 struct nv50_mstm *mstm = mstc->mstm;
948 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
949 int slots;
950 int ret;
951
952 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
953 mstc->native);
954 if (ret)
955 return ret;
956
957 if (!drm_atomic_crtc_needs_modeset(crtc_state))
958 return 0;
959
960 /*
961 * When restoring duplicated states, we need to make sure that the bw
962 * remains the same and avoid recalculating it, as the connector's bpc
963 * may have changed after the state was duplicated
964 */
965 if (!state->duplicated) {
966 const int clock = crtc_state->adjusted_mode.clock;
967
968 asyh->or.bpc = connector->display_info.bpc;
969 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3 << 4);
970 }
971
972 mst_state = drm_atomic_get_mst_topology_state(state, &mstm->mgr);
973 if (IS_ERR(mst_state))
974 return PTR_ERR(mst_state);
975
976 if (!mst_state->pbn_div) {
977 struct nouveau_encoder *outp = mstc->mstm->outp;
978
979 mst_state->pbn_div = drm_dp_get_vc_payload_bw(&mstm->mgr,
980 outp->dp.link_bw, outp->dp.link_nr);
981 }
982
983 slots = drm_dp_atomic_find_time_slots(state, &mstm->mgr, mstc->port, asyh->dp.pbn);
984 if (slots < 0)
985 return slots;
986
987 asyh->dp.tu = slots;
988
989 return 0;
990 }
991
992 static u8
nv50_dp_bpc_to_depth(unsigned int bpc)993 nv50_dp_bpc_to_depth(unsigned int bpc)
994 {
995 switch (bpc) {
996 case 6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444;
997 case 8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444;
998 case 10:
999 default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444;
1000 }
1001 }
1002
1003 static void
nv50_msto_atomic_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)1004 nv50_msto_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1005 {
1006 struct nv50_msto *msto = nv50_msto(encoder);
1007 struct nv50_head *head = msto->head;
1008 struct nv50_head_atom *asyh =
1009 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &head->base.base));
1010 struct nv50_mstc *mstc = NULL;
1011 struct nv50_mstm *mstm = NULL;
1012 struct drm_connector *connector;
1013 struct drm_connector_list_iter conn_iter;
1014 u8 proto;
1015
1016 drm_connector_list_iter_begin(encoder->dev, &conn_iter);
1017 drm_for_each_connector_iter(connector, &conn_iter) {
1018 if (connector->state->best_encoder == &msto->encoder) {
1019 mstc = nv50_mstc(connector);
1020 mstm = mstc->mstm;
1021 break;
1022 }
1023 }
1024 drm_connector_list_iter_end(&conn_iter);
1025
1026 if (WARN_ON(!mstc))
1027 return;
1028
1029 if (!mstm->links++) {
1030 /*XXX: MST audio. */
1031 nvif_outp_acquire_dp(&mstm->outp->outp, mstm->outp->dp.dpcd, 0, 0, false, true);
1032 }
1033
1034 if (mstm->outp->outp.or.link & 1)
1035 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A;
1036 else
1037 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B;
1038
1039 mstm->outp->update(mstm->outp, head->base.index, asyh, proto,
1040 nv50_dp_bpc_to_depth(asyh->or.bpc));
1041
1042 msto->mstc = mstc;
1043 msto->enabled = true;
1044 mstm->modified = true;
1045 }
1046
1047 static void
nv50_msto_atomic_disable(struct drm_encoder * encoder,struct drm_atomic_state * state)1048 nv50_msto_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1049 {
1050 struct nv50_msto *msto = nv50_msto(encoder);
1051 struct nv50_mstc *mstc = msto->mstc;
1052 struct nv50_mstm *mstm = mstc->mstm;
1053
1054 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
1055 mstm->modified = true;
1056 if (!--mstm->links)
1057 mstm->disabled = true;
1058 msto->disabled = true;
1059 }
1060
1061 static const struct drm_encoder_helper_funcs
1062 nv50_msto_help = {
1063 .atomic_disable = nv50_msto_atomic_disable,
1064 .atomic_enable = nv50_msto_atomic_enable,
1065 .atomic_check = nv50_msto_atomic_check,
1066 };
1067
1068 static void
nv50_msto_destroy(struct drm_encoder * encoder)1069 nv50_msto_destroy(struct drm_encoder *encoder)
1070 {
1071 struct nv50_msto *msto = nv50_msto(encoder);
1072 drm_encoder_cleanup(&msto->encoder);
1073 kfree(msto);
1074 }
1075
1076 static const struct drm_encoder_funcs
1077 nv50_msto = {
1078 .destroy = nv50_msto_destroy,
1079 };
1080
1081 static struct nv50_msto *
nv50_msto_new(struct drm_device * dev,struct nv50_head * head,int id)1082 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id)
1083 {
1084 struct nv50_msto *msto;
1085 int ret;
1086
1087 msto = kzalloc(sizeof(*msto), GFP_KERNEL);
1088 if (!msto)
1089 return ERR_PTR(-ENOMEM);
1090
1091 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
1092 DRM_MODE_ENCODER_DPMST, "mst-%d", id);
1093 if (ret) {
1094 kfree(msto);
1095 return ERR_PTR(ret);
1096 }
1097
1098 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
1099 msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base);
1100 msto->head = head;
1101 return msto;
1102 }
1103
1104 static struct drm_encoder *
nv50_mstc_atomic_best_encoder(struct drm_connector * connector,struct drm_atomic_state * state)1105 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
1106 struct drm_atomic_state *state)
1107 {
1108 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
1109 connector);
1110 struct nv50_mstc *mstc = nv50_mstc(connector);
1111 struct drm_crtc *crtc = connector_state->crtc;
1112
1113 if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1114 return NULL;
1115
1116 return &nv50_head(crtc)->msto->encoder;
1117 }
1118
1119 static enum drm_mode_status
nv50_mstc_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1120 nv50_mstc_mode_valid(struct drm_connector *connector,
1121 struct drm_display_mode *mode)
1122 {
1123 struct nv50_mstc *mstc = nv50_mstc(connector);
1124 struct nouveau_encoder *outp = mstc->mstm->outp;
1125
1126 /* TODO: calculate the PBN from the dotclock and validate against the
1127 * MSTB's max possible PBN
1128 */
1129
1130 return nv50_dp_mode_valid(outp, mode, NULL);
1131 }
1132
1133 static int
nv50_mstc_get_modes(struct drm_connector * connector)1134 nv50_mstc_get_modes(struct drm_connector *connector)
1135 {
1136 struct nv50_mstc *mstc = nv50_mstc(connector);
1137 int ret = 0;
1138
1139 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
1140 drm_connector_update_edid_property(&mstc->connector, mstc->edid);
1141 if (mstc->edid)
1142 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
1143
1144 /*
1145 * XXX: Since we don't use HDR in userspace quite yet, limit the bpc
1146 * to 8 to save bandwidth on the topology. In the future, we'll want
1147 * to properly fix this by dynamically selecting the highest possible
1148 * bpc that would fit in the topology
1149 */
1150 if (connector->display_info.bpc)
1151 connector->display_info.bpc =
1152 clamp(connector->display_info.bpc, 6U, 8U);
1153 else
1154 connector->display_info.bpc = 8;
1155
1156 if (mstc->native)
1157 drm_mode_destroy(mstc->connector.dev, mstc->native);
1158 mstc->native = nouveau_conn_native_mode(&mstc->connector);
1159 return ret;
1160 }
1161
1162 static int
nv50_mstc_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)1163 nv50_mstc_atomic_check(struct drm_connector *connector,
1164 struct drm_atomic_state *state)
1165 {
1166 struct nv50_mstc *mstc = nv50_mstc(connector);
1167 struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
1168
1169 return drm_dp_atomic_release_time_slots(state, mgr, mstc->port);
1170 }
1171
1172 static int
nv50_mstc_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)1173 nv50_mstc_detect(struct drm_connector *connector,
1174 struct drm_modeset_acquire_ctx *ctx, bool force)
1175 {
1176 struct nv50_mstc *mstc = nv50_mstc(connector);
1177 int ret;
1178
1179 if (drm_connector_is_unregistered(connector))
1180 return connector_status_disconnected;
1181
1182 ret = pm_runtime_get_sync(connector->dev->dev);
1183 if (ret < 0 && ret != -EACCES) {
1184 pm_runtime_put_autosuspend(connector->dev->dev);
1185 return connector_status_disconnected;
1186 }
1187
1188 ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
1189 mstc->port);
1190 if (ret != connector_status_connected)
1191 goto out;
1192
1193 out:
1194 pm_runtime_mark_last_busy(connector->dev->dev);
1195 pm_runtime_put_autosuspend(connector->dev->dev);
1196 return ret;
1197 }
1198
1199 static const struct drm_connector_helper_funcs
1200 nv50_mstc_help = {
1201 .get_modes = nv50_mstc_get_modes,
1202 .mode_valid = nv50_mstc_mode_valid,
1203 .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
1204 .atomic_check = nv50_mstc_atomic_check,
1205 .detect_ctx = nv50_mstc_detect,
1206 };
1207
1208 static void
nv50_mstc_destroy(struct drm_connector * connector)1209 nv50_mstc_destroy(struct drm_connector *connector)
1210 {
1211 struct nv50_mstc *mstc = nv50_mstc(connector);
1212
1213 drm_connector_cleanup(&mstc->connector);
1214 drm_dp_mst_put_port_malloc(mstc->port);
1215
1216 kfree(mstc);
1217 }
1218
1219 static const struct drm_connector_funcs
1220 nv50_mstc = {
1221 .reset = nouveau_conn_reset,
1222 .fill_modes = drm_helper_probe_single_connector_modes,
1223 .destroy = nv50_mstc_destroy,
1224 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1225 .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1226 .atomic_set_property = nouveau_conn_atomic_set_property,
1227 .atomic_get_property = nouveau_conn_atomic_get_property,
1228 };
1229
1230 static int
nv50_mstc_new(struct nv50_mstm * mstm,struct drm_dp_mst_port * port,const char * path,struct nv50_mstc ** pmstc)1231 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1232 const char *path, struct nv50_mstc **pmstc)
1233 {
1234 struct drm_device *dev = mstm->outp->base.base.dev;
1235 struct drm_crtc *crtc;
1236 struct nv50_mstc *mstc;
1237 int ret;
1238
1239 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1240 return -ENOMEM;
1241 mstc->mstm = mstm;
1242 mstc->port = port;
1243
1244 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1245 DRM_MODE_CONNECTOR_DisplayPort);
1246 if (ret) {
1247 kfree(*pmstc);
1248 *pmstc = NULL;
1249 return ret;
1250 }
1251
1252 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1253
1254 mstc->connector.funcs->reset(&mstc->connector);
1255 nouveau_conn_attach_properties(&mstc->connector);
1256
1257 drm_for_each_crtc(crtc, dev) {
1258 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1259 continue;
1260
1261 drm_connector_attach_encoder(&mstc->connector,
1262 &nv50_head(crtc)->msto->encoder);
1263 }
1264
1265 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1266 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1267 drm_connector_set_path_property(&mstc->connector, path);
1268 drm_dp_mst_get_port_malloc(port);
1269 return 0;
1270 }
1271
1272 static void
nv50_mstm_cleanup(struct drm_atomic_state * state,struct drm_dp_mst_topology_state * mst_state,struct nv50_mstm * mstm)1273 nv50_mstm_cleanup(struct drm_atomic_state *state,
1274 struct drm_dp_mst_topology_state *mst_state,
1275 struct nv50_mstm *mstm)
1276 {
1277 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1278 struct drm_encoder *encoder;
1279
1280 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1281 drm_dp_check_act_status(&mstm->mgr);
1282
1283 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1284 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1285 struct nv50_msto *msto = nv50_msto(encoder);
1286 struct nv50_mstc *mstc = msto->mstc;
1287 if (mstc && mstc->mstm == mstm)
1288 nv50_msto_cleanup(state, mst_state, &mstm->mgr, msto);
1289 }
1290 }
1291
1292 mstm->modified = false;
1293 }
1294
1295 static void
nv50_mstm_prepare(struct drm_atomic_state * state,struct drm_dp_mst_topology_state * mst_state,struct nv50_mstm * mstm)1296 nv50_mstm_prepare(struct drm_atomic_state *state,
1297 struct drm_dp_mst_topology_state *mst_state,
1298 struct nv50_mstm *mstm)
1299 {
1300 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1301 struct drm_encoder *encoder;
1302
1303 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1304
1305 /* Disable payloads first */
1306 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1307 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1308 struct nv50_msto *msto = nv50_msto(encoder);
1309 struct nv50_mstc *mstc = msto->mstc;
1310 if (mstc && mstc->mstm == mstm && msto->disabled)
1311 nv50_msto_prepare(state, mst_state, &mstm->mgr, msto);
1312 }
1313 }
1314
1315 /* Add payloads for new heads, while also updating the start slots of any unmodified (but
1316 * active) heads that may have had their VC slots shifted left after the previous step
1317 */
1318 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1319 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1320 struct nv50_msto *msto = nv50_msto(encoder);
1321 struct nv50_mstc *mstc = msto->mstc;
1322 if (mstc && mstc->mstm == mstm && !msto->disabled)
1323 nv50_msto_prepare(state, mst_state, &mstm->mgr, msto);
1324 }
1325 }
1326
1327 if (mstm->disabled) {
1328 if (!mstm->links)
1329 nvif_outp_release(&mstm->outp->outp);
1330 mstm->disabled = false;
1331 }
1332 }
1333
1334 static struct drm_connector *
nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr * mgr,struct drm_dp_mst_port * port,const char * path)1335 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1336 struct drm_dp_mst_port *port, const char *path)
1337 {
1338 struct nv50_mstm *mstm = nv50_mstm(mgr);
1339 struct nv50_mstc *mstc;
1340 int ret;
1341
1342 ret = nv50_mstc_new(mstm, port, path, &mstc);
1343 if (ret)
1344 return NULL;
1345
1346 return &mstc->connector;
1347 }
1348
1349 static const struct drm_dp_mst_topology_cbs
1350 nv50_mstm = {
1351 .add_connector = nv50_mstm_add_connector,
1352 };
1353
1354 bool
nv50_mstm_service(struct nouveau_drm * drm,struct nouveau_connector * nv_connector,struct nv50_mstm * mstm)1355 nv50_mstm_service(struct nouveau_drm *drm,
1356 struct nouveau_connector *nv_connector,
1357 struct nv50_mstm *mstm)
1358 {
1359 struct drm_dp_aux *aux = &nv_connector->aux;
1360 bool handled = true, ret = true;
1361 int rc;
1362 u8 esi[8] = {};
1363
1364 while (handled) {
1365 u8 ack[8] = {};
1366
1367 rc = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1368 if (rc != 8) {
1369 ret = false;
1370 break;
1371 }
1372
1373 drm_dp_mst_hpd_irq_handle_event(&mstm->mgr, esi, ack, &handled);
1374 if (!handled)
1375 break;
1376
1377 rc = drm_dp_dpcd_writeb(aux, DP_SINK_COUNT_ESI + 1, ack[1]);
1378
1379 if (rc != 1) {
1380 ret = false;
1381 break;
1382 }
1383
1384 drm_dp_mst_hpd_irq_send_new_request(&mstm->mgr);
1385 }
1386
1387 if (!ret)
1388 NV_DEBUG(drm, "Failed to handle ESI on %s: %d\n",
1389 nv_connector->base.name, rc);
1390
1391 return ret;
1392 }
1393
1394 void
nv50_mstm_remove(struct nv50_mstm * mstm)1395 nv50_mstm_remove(struct nv50_mstm *mstm)
1396 {
1397 mstm->is_mst = false;
1398 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1399 }
1400
1401 int
nv50_mstm_detect(struct nouveau_encoder * outp)1402 nv50_mstm_detect(struct nouveau_encoder *outp)
1403 {
1404 struct nv50_mstm *mstm = outp->dp.mstm;
1405 struct drm_dp_aux *aux;
1406 int ret;
1407
1408 if (!mstm || !mstm->can_mst)
1409 return 0;
1410
1411 aux = mstm->mgr.aux;
1412
1413 /* Clear any leftover MST state we didn't set ourselves by first
1414 * disabling MST if it was already enabled
1415 */
1416 ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1417 if (ret < 0)
1418 return ret;
1419
1420 /* And start enabling */
1421 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, true);
1422 if (ret)
1423 return ret;
1424
1425 mstm->is_mst = true;
1426 return 1;
1427 }
1428
1429 static void
nv50_mstm_fini(struct nouveau_encoder * outp)1430 nv50_mstm_fini(struct nouveau_encoder *outp)
1431 {
1432 struct nv50_mstm *mstm = outp->dp.mstm;
1433
1434 if (!mstm)
1435 return;
1436
1437 /* Don't change the MST state of this connector until we've finished
1438 * resuming, since we can't safely grab hpd_irq_lock in our resume
1439 * path to protect mstm->is_mst without potentially deadlocking
1440 */
1441 mutex_lock(&outp->dp.hpd_irq_lock);
1442 mstm->suspended = true;
1443 mutex_unlock(&outp->dp.hpd_irq_lock);
1444
1445 if (mstm->is_mst)
1446 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1447 }
1448
1449 static void
nv50_mstm_init(struct nouveau_encoder * outp,bool runtime)1450 nv50_mstm_init(struct nouveau_encoder *outp, bool runtime)
1451 {
1452 struct nv50_mstm *mstm = outp->dp.mstm;
1453 int ret = 0;
1454
1455 if (!mstm)
1456 return;
1457
1458 if (mstm->is_mst) {
1459 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
1460 if (ret == -1)
1461 nv50_mstm_remove(mstm);
1462 }
1463
1464 mutex_lock(&outp->dp.hpd_irq_lock);
1465 mstm->suspended = false;
1466 mutex_unlock(&outp->dp.hpd_irq_lock);
1467
1468 if (ret == -1)
1469 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1470 }
1471
1472 static void
nv50_mstm_del(struct nv50_mstm ** pmstm)1473 nv50_mstm_del(struct nv50_mstm **pmstm)
1474 {
1475 struct nv50_mstm *mstm = *pmstm;
1476 if (mstm) {
1477 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1478 kfree(*pmstm);
1479 *pmstm = NULL;
1480 }
1481 }
1482
1483 static int
nv50_mstm_new(struct nouveau_encoder * outp,struct drm_dp_aux * aux,int aux_max,int conn_base_id,struct nv50_mstm ** pmstm)1484 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1485 int conn_base_id, struct nv50_mstm **pmstm)
1486 {
1487 const int max_payloads = hweight8(outp->dcb->heads);
1488 struct drm_device *dev = outp->base.base.dev;
1489 struct nv50_mstm *mstm;
1490 int ret;
1491
1492 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1493 return -ENOMEM;
1494 mstm->outp = outp;
1495 mstm->mgr.cbs = &nv50_mstm;
1496
1497 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1498 max_payloads, conn_base_id);
1499 if (ret)
1500 return ret;
1501
1502 return 0;
1503 }
1504
1505 /******************************************************************************
1506 * SOR
1507 *****************************************************************************/
1508 static void
nv50_sor_update(struct nouveau_encoder * nv_encoder,u8 head,struct nv50_head_atom * asyh,u8 proto,u8 depth)1509 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1510 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1511 {
1512 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1513 struct nv50_core *core = disp->core;
1514
1515 if (!asyh) {
1516 nv_encoder->ctrl &= ~BIT(head);
1517 if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE))
1518 nv_encoder->ctrl = 0;
1519 } else {
1520 nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto);
1521 nv_encoder->ctrl |= BIT(head);
1522 asyh->or.depth = depth;
1523 }
1524
1525 core->func->sor->ctrl(core, nv_encoder->outp.or.id, nv_encoder->ctrl, asyh);
1526 }
1527
1528 /* TODO: Should we extend this to PWM-only backlights?
1529 * As well, should we add a DRM helper for waiting for the backlight to acknowledge
1530 * the panel backlight has been shut off? Intel doesn't seem to do this, and uses a
1531 * fixed time delay from the vbios…
1532 */
1533 static void
nv50_sor_atomic_disable(struct drm_encoder * encoder,struct drm_atomic_state * state)1534 nv50_sor_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1535 {
1536 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1537 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1538 struct nouveau_connector *nv_connector = nv50_outp_get_old_connector(state, nv_encoder);
1539 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1540 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
1541 struct nouveau_backlight *backlight = nv_connector->backlight;
1542 #endif
1543 struct drm_dp_aux *aux = &nv_connector->aux;
1544 int ret;
1545 u8 pwr;
1546
1547 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1548 if (backlight && backlight->uses_dpcd) {
1549 ret = drm_edp_backlight_disable(aux, &backlight->edp_info);
1550 if (ret < 0)
1551 NV_ERROR(drm, "Failed to disable backlight on [CONNECTOR:%d:%s]: %d\n",
1552 nv_connector->base.base.id, nv_connector->base.name, ret);
1553 }
1554 #endif
1555
1556 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1557 ret = drm_dp_dpcd_readb(aux, DP_SET_POWER, &pwr);
1558
1559 if (ret == 0) {
1560 pwr &= ~DP_SET_POWER_MASK;
1561 pwr |= DP_SET_POWER_D3;
1562 drm_dp_dpcd_writeb(aux, DP_SET_POWER, pwr);
1563 }
1564 }
1565
1566 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1567 nv50_audio_disable(encoder, nv_crtc);
1568 nvif_outp_release(&nv_encoder->outp);
1569 nv_encoder->crtc = NULL;
1570 }
1571
1572 static void
nv50_sor_atomic_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)1573 nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1574 {
1575 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1576 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
1577 struct nv50_head_atom *asyh =
1578 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
1579 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1580 struct nv50_disp *disp = nv50_disp(encoder->dev);
1581 struct nvif_outp *outp = &nv_encoder->outp;
1582 struct drm_device *dev = encoder->dev;
1583 struct nouveau_drm *drm = nouveau_drm(dev);
1584 struct nouveau_connector *nv_connector;
1585 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1586 struct nouveau_backlight *backlight;
1587 #endif
1588 struct nvbios *bios = &drm->vbios;
1589 bool lvds_dual = false, lvds_8bpc = false, hda = false;
1590 u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM;
1591 u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT;
1592
1593 nv_connector = nv50_outp_get_new_connector(state, nv_encoder);
1594 nv_encoder->crtc = &nv_crtc->base;
1595
1596 if ((disp->disp->object.oclass == GT214_DISP ||
1597 disp->disp->object.oclass >= GF110_DISP) &&
1598 drm_detect_monitor_audio(nv_connector->edid))
1599 hda = true;
1600
1601 switch (nv_encoder->dcb->type) {
1602 case DCB_OUTPUT_TMDS:
1603 if (disp->disp->object.oclass == NV50_DISP ||
1604 !drm_detect_hdmi_monitor(nv_connector->edid))
1605 nvif_outp_acquire_tmds(outp, nv_crtc->index, false, 0, 0, 0, false);
1606 else
1607 nv50_hdmi_enable(encoder, nv_crtc, nv_connector, state, mode, hda);
1608
1609 if (nv_encoder->outp.or.link & 1) {
1610 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A;
1611 /* Only enable dual-link if:
1612 * - Need to (i.e. rate > 165MHz)
1613 * - DCB says we can
1614 * - Not an HDMI monitor, since there's no dual-link
1615 * on HDMI.
1616 */
1617 if (mode->clock >= 165000 &&
1618 nv_encoder->dcb->duallink_possible &&
1619 !drm_detect_hdmi_monitor(nv_connector->edid))
1620 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS;
1621 } else {
1622 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B;
1623 }
1624 break;
1625 case DCB_OUTPUT_LVDS:
1626 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM;
1627
1628 if (bios->fp_no_ddc) {
1629 lvds_dual = bios->fp.dual_link;
1630 lvds_8bpc = bios->fp.if_is_24bit;
1631 } else {
1632 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1633 if (((u8 *)nv_connector->edid)[121] == 2)
1634 lvds_dual = true;
1635 } else
1636 if (mode->clock >= bios->fp.duallink_transition_clk) {
1637 lvds_dual = true;
1638 }
1639
1640 if (lvds_dual) {
1641 if (bios->fp.strapless_is_24bit & 2)
1642 lvds_8bpc = true;
1643 } else {
1644 if (bios->fp.strapless_is_24bit & 1)
1645 lvds_8bpc = true;
1646 }
1647
1648 if (asyh->or.bpc == 8)
1649 lvds_8bpc = true;
1650 }
1651
1652 nvif_outp_acquire_lvds(&nv_encoder->outp, lvds_dual, lvds_8bpc);
1653 break;
1654 case DCB_OUTPUT_DP:
1655 nvif_outp_acquire_dp(&nv_encoder->outp, nv_encoder->dp.dpcd, 0, 0, hda, false);
1656 depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1657
1658 if (nv_encoder->outp.or.link & 1)
1659 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A;
1660 else
1661 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B;
1662
1663 nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode);
1664
1665 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1666 backlight = nv_connector->backlight;
1667 if (backlight && backlight->uses_dpcd)
1668 drm_edp_backlight_enable(&nv_connector->aux, &backlight->edp_info,
1669 (u16)backlight->dev->props.brightness);
1670 #endif
1671
1672 break;
1673 default:
1674 BUG();
1675 break;
1676 }
1677
1678 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1679 }
1680
1681 static const struct drm_encoder_helper_funcs
1682 nv50_sor_help = {
1683 .atomic_check = nv50_outp_atomic_check,
1684 .atomic_enable = nv50_sor_atomic_enable,
1685 .atomic_disable = nv50_sor_atomic_disable,
1686 };
1687
1688 static void
nv50_sor_destroy(struct drm_encoder * encoder)1689 nv50_sor_destroy(struct drm_encoder *encoder)
1690 {
1691 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1692
1693 nvif_outp_dtor(&nv_encoder->outp);
1694
1695 nv50_mstm_del(&nv_encoder->dp.mstm);
1696 drm_encoder_cleanup(encoder);
1697
1698 if (nv_encoder->dcb->type == DCB_OUTPUT_DP)
1699 mutex_destroy(&nv_encoder->dp.hpd_irq_lock);
1700
1701 kfree(encoder);
1702 }
1703
1704 static const struct drm_encoder_funcs
1705 nv50_sor_func = {
1706 .destroy = nv50_sor_destroy,
1707 };
1708
nv50_has_mst(struct nouveau_drm * drm)1709 bool nv50_has_mst(struct nouveau_drm *drm)
1710 {
1711 struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1712 u32 data;
1713 u8 ver, hdr, cnt, len;
1714
1715 data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len);
1716 return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04);
1717 }
1718
1719 static int
nv50_sor_create(struct drm_connector * connector,struct dcb_output * dcbe)1720 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1721 {
1722 struct nouveau_connector *nv_connector = nouveau_connector(connector);
1723 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1724 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1725 struct nouveau_encoder *nv_encoder;
1726 struct drm_encoder *encoder;
1727 struct nv50_disp *disp = nv50_disp(connector->dev);
1728 int type, ret;
1729
1730 switch (dcbe->type) {
1731 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1732 case DCB_OUTPUT_TMDS:
1733 case DCB_OUTPUT_DP:
1734 default:
1735 type = DRM_MODE_ENCODER_TMDS;
1736 break;
1737 }
1738
1739 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1740 if (!nv_encoder)
1741 return -ENOMEM;
1742 nv_encoder->dcb = dcbe;
1743 nv_encoder->update = nv50_sor_update;
1744
1745 encoder = to_drm_encoder(nv_encoder);
1746 encoder->possible_crtcs = dcbe->heads;
1747 encoder->possible_clones = 0;
1748 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1749 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1750 drm_encoder_helper_add(encoder, &nv50_sor_help);
1751
1752 drm_connector_attach_encoder(connector, encoder);
1753
1754 disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
1755 nv50_outp_dump_caps(drm, nv_encoder);
1756
1757 if (dcbe->type == DCB_OUTPUT_DP) {
1758 struct nvkm_i2c_aux *aux =
1759 nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1760
1761 mutex_init(&nv_encoder->dp.hpd_irq_lock);
1762
1763 if (aux) {
1764 if (disp->disp->object.oclass < GF110_DISP) {
1765 /* HW has no support for address-only
1766 * transactions, so we're required to
1767 * use custom I2C-over-AUX code.
1768 */
1769 nv_encoder->i2c = &aux->i2c;
1770 } else {
1771 nv_encoder->i2c = &nv_connector->aux.ddc;
1772 }
1773 nv_encoder->aux = aux;
1774 }
1775
1776 if (nv_connector->type != DCB_CONNECTOR_eDP &&
1777 nv50_has_mst(drm)) {
1778 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux,
1779 16, nv_connector->base.base.id,
1780 &nv_encoder->dp.mstm);
1781 if (ret)
1782 return ret;
1783 }
1784 } else {
1785 struct nvkm_i2c_bus *bus =
1786 nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1787 if (bus)
1788 nv_encoder->i2c = &bus->i2c;
1789 }
1790
1791 return nvif_outp_ctor(disp->disp, nv_encoder->base.base.name, dcbe->id, &nv_encoder->outp);
1792 }
1793
1794 /******************************************************************************
1795 * PIOR
1796 *****************************************************************************/
1797 static int
nv50_pior_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1798 nv50_pior_atomic_check(struct drm_encoder *encoder,
1799 struct drm_crtc_state *crtc_state,
1800 struct drm_connector_state *conn_state)
1801 {
1802 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1803 if (ret)
1804 return ret;
1805 crtc_state->adjusted_mode.clock *= 2;
1806 return 0;
1807 }
1808
1809 static void
nv50_pior_atomic_disable(struct drm_encoder * encoder,struct drm_atomic_state * state)1810 nv50_pior_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1811 {
1812 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1813 struct nv50_core *core = nv50_disp(encoder->dev)->core;
1814 const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE);
1815
1816 core->func->pior->ctrl(core, nv_encoder->outp.or.id, ctrl, NULL);
1817 nv_encoder->crtc = NULL;
1818 nvif_outp_release(&nv_encoder->outp);
1819 }
1820
1821 static void
nv50_pior_atomic_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)1822 nv50_pior_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1823 {
1824 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1825 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
1826 struct nv50_head_atom *asyh =
1827 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
1828 struct nv50_core *core = nv50_disp(encoder->dev)->core;
1829 u32 ctrl = 0;
1830
1831 switch (nv_crtc->index) {
1832 case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break;
1833 case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break;
1834 default:
1835 WARN_ON(1);
1836 break;
1837 }
1838
1839 switch (asyh->or.bpc) {
1840 case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break;
1841 case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break;
1842 case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break;
1843 default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break;
1844 }
1845
1846 switch (nv_encoder->dcb->type) {
1847 case DCB_OUTPUT_TMDS:
1848 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
1849 nvif_outp_acquire_tmds(&nv_encoder->outp, false, false, 0, 0, 0, false);
1850 break;
1851 case DCB_OUTPUT_DP:
1852 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
1853 nvif_outp_acquire_dp(&nv_encoder->outp, nv_encoder->dp.dpcd, 0, 0, false, false);
1854 break;
1855 default:
1856 BUG();
1857 break;
1858 }
1859
1860 core->func->pior->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh);
1861 nv_encoder->crtc = &nv_crtc->base;
1862 }
1863
1864 static const struct drm_encoder_helper_funcs
1865 nv50_pior_help = {
1866 .atomic_check = nv50_pior_atomic_check,
1867 .atomic_enable = nv50_pior_atomic_enable,
1868 .atomic_disable = nv50_pior_atomic_disable,
1869 };
1870
1871 static void
nv50_pior_destroy(struct drm_encoder * encoder)1872 nv50_pior_destroy(struct drm_encoder *encoder)
1873 {
1874 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1875
1876 nvif_outp_dtor(&nv_encoder->outp);
1877
1878 drm_encoder_cleanup(encoder);
1879
1880 mutex_destroy(&nv_encoder->dp.hpd_irq_lock);
1881 kfree(encoder);
1882 }
1883
1884 static const struct drm_encoder_funcs
1885 nv50_pior_func = {
1886 .destroy = nv50_pior_destroy,
1887 };
1888
1889 static int
nv50_pior_create(struct drm_connector * connector,struct dcb_output * dcbe)1890 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1891 {
1892 struct drm_device *dev = connector->dev;
1893 struct nouveau_drm *drm = nouveau_drm(dev);
1894 struct nv50_disp *disp = nv50_disp(dev);
1895 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1896 struct nvkm_i2c_bus *bus = NULL;
1897 struct nvkm_i2c_aux *aux = NULL;
1898 struct i2c_adapter *ddc;
1899 struct nouveau_encoder *nv_encoder;
1900 struct drm_encoder *encoder;
1901 int type;
1902
1903 switch (dcbe->type) {
1904 case DCB_OUTPUT_TMDS:
1905 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1906 ddc = bus ? &bus->i2c : NULL;
1907 type = DRM_MODE_ENCODER_TMDS;
1908 break;
1909 case DCB_OUTPUT_DP:
1910 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1911 ddc = aux ? &aux->i2c : NULL;
1912 type = DRM_MODE_ENCODER_TMDS;
1913 break;
1914 default:
1915 return -ENODEV;
1916 }
1917
1918 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1919 if (!nv_encoder)
1920 return -ENOMEM;
1921 nv_encoder->dcb = dcbe;
1922 nv_encoder->i2c = ddc;
1923 nv_encoder->aux = aux;
1924
1925 mutex_init(&nv_encoder->dp.hpd_irq_lock);
1926
1927 encoder = to_drm_encoder(nv_encoder);
1928 encoder->possible_crtcs = dcbe->heads;
1929 encoder->possible_clones = 0;
1930 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1931 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1932 drm_encoder_helper_add(encoder, &nv50_pior_help);
1933
1934 drm_connector_attach_encoder(connector, encoder);
1935
1936 disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
1937 nv50_outp_dump_caps(drm, nv_encoder);
1938
1939 return nvif_outp_ctor(disp->disp, nv_encoder->base.base.name, dcbe->id, &nv_encoder->outp);
1940 }
1941
1942 /******************************************************************************
1943 * Atomic
1944 *****************************************************************************/
1945
1946 static void
nv50_disp_atomic_commit_core(struct drm_atomic_state * state,u32 * interlock)1947 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1948 {
1949 struct drm_dp_mst_topology_mgr *mgr;
1950 struct drm_dp_mst_topology_state *mst_state;
1951 struct nouveau_drm *drm = nouveau_drm(state->dev);
1952 struct nv50_disp *disp = nv50_disp(drm->dev);
1953 struct nv50_core *core = disp->core;
1954 struct nv50_mstm *mstm;
1955 int i;
1956
1957 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1958
1959 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
1960 mstm = nv50_mstm(mgr);
1961 if (mstm->modified)
1962 nv50_mstm_prepare(state, mst_state, mstm);
1963 }
1964
1965 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1966 core->func->update(core, interlock, true);
1967 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1968 disp->core->chan.base.device))
1969 NV_ERROR(drm, "core notifier timeout\n");
1970
1971 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
1972 mstm = nv50_mstm(mgr);
1973 if (mstm->modified)
1974 nv50_mstm_cleanup(state, mst_state, mstm);
1975 }
1976 }
1977
1978 static void
nv50_disp_atomic_commit_wndw(struct drm_atomic_state * state,u32 * interlock)1979 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1980 {
1981 struct drm_plane_state *new_plane_state;
1982 struct drm_plane *plane;
1983 int i;
1984
1985 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1986 struct nv50_wndw *wndw = nv50_wndw(plane);
1987 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1988 if (wndw->func->update)
1989 wndw->func->update(wndw, interlock);
1990 }
1991 }
1992 }
1993
1994 static void
nv50_disp_atomic_commit_tail(struct drm_atomic_state * state)1995 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1996 {
1997 struct drm_device *dev = state->dev;
1998 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
1999 struct drm_crtc *crtc;
2000 struct drm_plane_state *new_plane_state;
2001 struct drm_plane *plane;
2002 struct nouveau_drm *drm = nouveau_drm(dev);
2003 struct nv50_disp *disp = nv50_disp(dev);
2004 struct nv50_atom *atom = nv50_atom(state);
2005 struct nv50_core *core = disp->core;
2006 struct nv50_outp_atom *outp, *outt;
2007 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
2008 int i;
2009 bool flushed = false;
2010
2011 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
2012 nv50_crc_atomic_stop_reporting(state);
2013 drm_atomic_helper_wait_for_fences(dev, state, false);
2014 drm_atomic_helper_wait_for_dependencies(state);
2015 drm_dp_mst_atomic_wait_for_dependencies(state);
2016 drm_atomic_helper_update_legacy_modeset_state(dev, state);
2017 drm_atomic_helper_calc_timestamping_constants(state);
2018
2019 if (atom->lock_core)
2020 mutex_lock(&disp->mutex);
2021
2022 /* Disable head(s). */
2023 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2024 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2025 struct nv50_head *head = nv50_head(crtc);
2026
2027 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
2028 asyh->clr.mask, asyh->set.mask);
2029
2030 if (old_crtc_state->active && !new_crtc_state->active) {
2031 pm_runtime_put_noidle(dev->dev);
2032 drm_crtc_vblank_off(crtc);
2033 }
2034
2035 if (asyh->clr.mask) {
2036 nv50_head_flush_clr(head, asyh, atom->flush_disable);
2037 interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
2038 }
2039 }
2040
2041 /* Disable plane(s). */
2042 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2043 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2044 struct nv50_wndw *wndw = nv50_wndw(plane);
2045
2046 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
2047 asyw->clr.mask, asyw->set.mask);
2048 if (!asyw->clr.mask)
2049 continue;
2050
2051 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
2052 }
2053
2054 /* Disable output path(s). */
2055 list_for_each_entry(outp, &atom->outp, head) {
2056 const struct drm_encoder_helper_funcs *help;
2057 struct drm_encoder *encoder;
2058
2059 encoder = outp->encoder;
2060 help = encoder->helper_private;
2061
2062 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
2063 outp->clr.mask, outp->set.mask);
2064
2065 if (outp->clr.mask) {
2066 help->atomic_disable(encoder, state);
2067 interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
2068 if (outp->flush_disable) {
2069 nv50_disp_atomic_commit_wndw(state, interlock);
2070 nv50_disp_atomic_commit_core(state, interlock);
2071 memset(interlock, 0x00, sizeof(interlock));
2072
2073 flushed = true;
2074 }
2075 }
2076 }
2077
2078 /* Flush disable. */
2079 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2080 if (atom->flush_disable) {
2081 nv50_disp_atomic_commit_wndw(state, interlock);
2082 nv50_disp_atomic_commit_core(state, interlock);
2083 memset(interlock, 0x00, sizeof(interlock));
2084
2085 flushed = true;
2086 }
2087 }
2088
2089 if (flushed)
2090 nv50_crc_atomic_release_notifier_contexts(state);
2091 nv50_crc_atomic_init_notifier_contexts(state);
2092
2093 /* Update output path(s). */
2094 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2095 const struct drm_encoder_helper_funcs *help;
2096 struct drm_encoder *encoder;
2097
2098 encoder = outp->encoder;
2099 help = encoder->helper_private;
2100
2101 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
2102 outp->set.mask, outp->clr.mask);
2103
2104 if (outp->set.mask) {
2105 help->atomic_enable(encoder, state);
2106 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2107 }
2108
2109 list_del(&outp->head);
2110 kfree(outp);
2111 }
2112
2113 /* Update head(s). */
2114 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2115 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2116 struct nv50_head *head = nv50_head(crtc);
2117
2118 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2119 asyh->set.mask, asyh->clr.mask);
2120
2121 if (asyh->set.mask) {
2122 nv50_head_flush_set(head, asyh);
2123 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2124 }
2125
2126 if (new_crtc_state->active) {
2127 if (!old_crtc_state->active) {
2128 drm_crtc_vblank_on(crtc);
2129 pm_runtime_get_noresume(dev->dev);
2130 }
2131 if (new_crtc_state->event)
2132 drm_crtc_vblank_get(crtc);
2133 }
2134 }
2135
2136 /* Update window->head assignment.
2137 *
2138 * This has to happen in an update that's not interlocked with
2139 * any window channels to avoid hitting HW error checks.
2140 *
2141 *TODO: Proper handling of window ownership (Turing apparently
2142 * supports non-fixed mappings).
2143 */
2144 if (core->assign_windows) {
2145 core->func->wndw.owner(core);
2146 nv50_disp_atomic_commit_core(state, interlock);
2147 core->assign_windows = false;
2148 interlock[NV50_DISP_INTERLOCK_CORE] = 0;
2149 }
2150
2151 /* Finish updating head(s)...
2152 *
2153 * NVD is rather picky about both where window assignments can change,
2154 * *and* about certain core and window channel states matching.
2155 *
2156 * The EFI GOP driver on newer GPUs configures window channels with a
2157 * different output format to what we do, and the core channel update
2158 * in the assign_windows case above would result in a state mismatch.
2159 *
2160 * Delay some of the head update until after that point to workaround
2161 * the issue. This only affects the initial modeset.
2162 *
2163 * TODO: handle this better when adding flexible window mapping
2164 */
2165 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2166 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2167 struct nv50_head *head = nv50_head(crtc);
2168
2169 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2170 asyh->set.mask, asyh->clr.mask);
2171
2172 if (asyh->set.mask) {
2173 nv50_head_flush_set_wndw(head, asyh);
2174 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2175 }
2176 }
2177
2178 /* Update plane(s). */
2179 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2180 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2181 struct nv50_wndw *wndw = nv50_wndw(plane);
2182
2183 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
2184 asyw->set.mask, asyw->clr.mask);
2185 if ( !asyw->set.mask &&
2186 (!asyw->clr.mask || atom->flush_disable))
2187 continue;
2188
2189 nv50_wndw_flush_set(wndw, interlock, asyw);
2190 }
2191
2192 /* Flush update. */
2193 nv50_disp_atomic_commit_wndw(state, interlock);
2194
2195 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2196 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
2197 interlock[NV50_DISP_INTERLOCK_OVLY] ||
2198 interlock[NV50_DISP_INTERLOCK_WNDW] ||
2199 !atom->state.legacy_cursor_update)
2200 nv50_disp_atomic_commit_core(state, interlock);
2201 else
2202 disp->core->func->update(disp->core, interlock, false);
2203 }
2204
2205 if (atom->lock_core)
2206 mutex_unlock(&disp->mutex);
2207
2208 /* Wait for HW to signal completion. */
2209 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2210 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2211 struct nv50_wndw *wndw = nv50_wndw(plane);
2212 int ret = nv50_wndw_wait_armed(wndw, asyw);
2213 if (ret)
2214 NV_ERROR(drm, "%s: timeout\n", plane->name);
2215 }
2216
2217 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2218 if (new_crtc_state->event) {
2219 unsigned long flags;
2220 /* Get correct count/ts if racing with vblank irq */
2221 if (new_crtc_state->active)
2222 drm_crtc_accurate_vblank_count(crtc);
2223 spin_lock_irqsave(&crtc->dev->event_lock, flags);
2224 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
2225 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2226
2227 new_crtc_state->event = NULL;
2228 if (new_crtc_state->active)
2229 drm_crtc_vblank_put(crtc);
2230 }
2231 }
2232
2233 nv50_crc_atomic_start_reporting(state);
2234 if (!flushed)
2235 nv50_crc_atomic_release_notifier_contexts(state);
2236
2237 drm_atomic_helper_commit_hw_done(state);
2238 drm_atomic_helper_cleanup_planes(dev, state);
2239 drm_atomic_helper_commit_cleanup_done(state);
2240 drm_atomic_state_put(state);
2241
2242 /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
2243 pm_runtime_mark_last_busy(dev->dev);
2244 pm_runtime_put_autosuspend(dev->dev);
2245 }
2246
2247 static void
nv50_disp_atomic_commit_work(struct work_struct * work)2248 nv50_disp_atomic_commit_work(struct work_struct *work)
2249 {
2250 struct drm_atomic_state *state =
2251 container_of(work, typeof(*state), commit_work);
2252 nv50_disp_atomic_commit_tail(state);
2253 }
2254
2255 static int
nv50_disp_atomic_commit(struct drm_device * dev,struct drm_atomic_state * state,bool nonblock)2256 nv50_disp_atomic_commit(struct drm_device *dev,
2257 struct drm_atomic_state *state, bool nonblock)
2258 {
2259 struct drm_plane_state *new_plane_state;
2260 struct drm_plane *plane;
2261 int ret, i;
2262
2263 ret = pm_runtime_get_sync(dev->dev);
2264 if (ret < 0 && ret != -EACCES) {
2265 pm_runtime_put_autosuspend(dev->dev);
2266 return ret;
2267 }
2268
2269 ret = drm_atomic_helper_setup_commit(state, nonblock);
2270 if (ret)
2271 goto done;
2272
2273 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2274
2275 ret = drm_atomic_helper_prepare_planes(dev, state);
2276 if (ret)
2277 goto done;
2278
2279 if (!nonblock) {
2280 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2281 if (ret)
2282 goto err_cleanup;
2283 }
2284
2285 ret = drm_atomic_helper_swap_state(state, true);
2286 if (ret)
2287 goto err_cleanup;
2288
2289 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2290 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2291 struct nv50_wndw *wndw = nv50_wndw(plane);
2292
2293 if (asyw->set.image)
2294 nv50_wndw_ntfy_enable(wndw, asyw);
2295 }
2296
2297 drm_atomic_state_get(state);
2298
2299 /*
2300 * Grab another RPM ref for the commit tail, which will release the
2301 * ref when it's finished
2302 */
2303 pm_runtime_get_noresume(dev->dev);
2304
2305 if (nonblock)
2306 queue_work(system_unbound_wq, &state->commit_work);
2307 else
2308 nv50_disp_atomic_commit_tail(state);
2309
2310 err_cleanup:
2311 if (ret)
2312 drm_atomic_helper_unprepare_planes(dev, state);
2313 done:
2314 pm_runtime_put_autosuspend(dev->dev);
2315 return ret;
2316 }
2317
2318 static struct nv50_outp_atom *
nv50_disp_outp_atomic_add(struct nv50_atom * atom,struct drm_encoder * encoder)2319 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2320 {
2321 struct nv50_outp_atom *outp;
2322
2323 list_for_each_entry(outp, &atom->outp, head) {
2324 if (outp->encoder == encoder)
2325 return outp;
2326 }
2327
2328 outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2329 if (!outp)
2330 return ERR_PTR(-ENOMEM);
2331
2332 list_add(&outp->head, &atom->outp);
2333 outp->encoder = encoder;
2334 return outp;
2335 }
2336
2337 static int
nv50_disp_outp_atomic_check_clr(struct nv50_atom * atom,struct drm_connector_state * old_connector_state)2338 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2339 struct drm_connector_state *old_connector_state)
2340 {
2341 struct drm_encoder *encoder = old_connector_state->best_encoder;
2342 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2343 struct drm_crtc *crtc;
2344 struct nv50_outp_atom *outp;
2345
2346 if (!(crtc = old_connector_state->crtc))
2347 return 0;
2348
2349 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2350 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2351 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2352 outp = nv50_disp_outp_atomic_add(atom, encoder);
2353 if (IS_ERR(outp))
2354 return PTR_ERR(outp);
2355
2356 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2357 outp->flush_disable = true;
2358 atom->flush_disable = true;
2359 }
2360 outp->clr.ctrl = true;
2361 atom->lock_core = true;
2362 }
2363
2364 return 0;
2365 }
2366
2367 static int
nv50_disp_outp_atomic_check_set(struct nv50_atom * atom,struct drm_connector_state * connector_state)2368 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2369 struct drm_connector_state *connector_state)
2370 {
2371 struct drm_encoder *encoder = connector_state->best_encoder;
2372 struct drm_crtc_state *new_crtc_state;
2373 struct drm_crtc *crtc;
2374 struct nv50_outp_atom *outp;
2375
2376 if (!(crtc = connector_state->crtc))
2377 return 0;
2378
2379 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2380 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2381 outp = nv50_disp_outp_atomic_add(atom, encoder);
2382 if (IS_ERR(outp))
2383 return PTR_ERR(outp);
2384
2385 outp->set.ctrl = true;
2386 atom->lock_core = true;
2387 }
2388
2389 return 0;
2390 }
2391
2392 static int
nv50_disp_atomic_check(struct drm_device * dev,struct drm_atomic_state * state)2393 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2394 {
2395 struct nv50_atom *atom = nv50_atom(state);
2396 struct nv50_core *core = nv50_disp(dev)->core;
2397 struct drm_connector_state *old_connector_state, *new_connector_state;
2398 struct drm_connector *connector;
2399 struct drm_crtc_state *new_crtc_state;
2400 struct drm_crtc *crtc;
2401 struct nv50_head *head;
2402 struct nv50_head_atom *asyh;
2403 int ret, i;
2404
2405 if (core->assign_windows && core->func->head->static_wndw_map) {
2406 drm_for_each_crtc(crtc, dev) {
2407 new_crtc_state = drm_atomic_get_crtc_state(state,
2408 crtc);
2409 if (IS_ERR(new_crtc_state))
2410 return PTR_ERR(new_crtc_state);
2411
2412 head = nv50_head(crtc);
2413 asyh = nv50_head_atom(new_crtc_state);
2414 core->func->head->static_wndw_map(head, asyh);
2415 }
2416 }
2417
2418 /* We need to handle colour management on a per-plane basis. */
2419 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2420 if (new_crtc_state->color_mgmt_changed) {
2421 ret = drm_atomic_add_affected_planes(state, crtc);
2422 if (ret)
2423 return ret;
2424 }
2425 }
2426
2427 ret = drm_atomic_helper_check(dev, state);
2428 if (ret)
2429 return ret;
2430
2431 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2432 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2433 if (ret)
2434 return ret;
2435
2436 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2437 if (ret)
2438 return ret;
2439 }
2440
2441 ret = drm_dp_mst_atomic_check(state);
2442 if (ret)
2443 return ret;
2444
2445 nv50_crc_atomic_check_outp(atom);
2446
2447 return 0;
2448 }
2449
2450 static void
nv50_disp_atomic_state_clear(struct drm_atomic_state * state)2451 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2452 {
2453 struct nv50_atom *atom = nv50_atom(state);
2454 struct nv50_outp_atom *outp, *outt;
2455
2456 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2457 list_del(&outp->head);
2458 kfree(outp);
2459 }
2460
2461 drm_atomic_state_default_clear(state);
2462 }
2463
2464 static void
nv50_disp_atomic_state_free(struct drm_atomic_state * state)2465 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2466 {
2467 struct nv50_atom *atom = nv50_atom(state);
2468 drm_atomic_state_default_release(&atom->state);
2469 kfree(atom);
2470 }
2471
2472 static struct drm_atomic_state *
nv50_disp_atomic_state_alloc(struct drm_device * dev)2473 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2474 {
2475 struct nv50_atom *atom;
2476 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2477 drm_atomic_state_init(dev, &atom->state) < 0) {
2478 kfree(atom);
2479 return NULL;
2480 }
2481 INIT_LIST_HEAD(&atom->outp);
2482 return &atom->state;
2483 }
2484
2485 static const struct drm_mode_config_funcs
2486 nv50_disp_func = {
2487 .fb_create = nouveau_user_framebuffer_create,
2488 .output_poll_changed = drm_fb_helper_output_poll_changed,
2489 .atomic_check = nv50_disp_atomic_check,
2490 .atomic_commit = nv50_disp_atomic_commit,
2491 .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2492 .atomic_state_clear = nv50_disp_atomic_state_clear,
2493 .atomic_state_free = nv50_disp_atomic_state_free,
2494 };
2495
2496 static const struct drm_mode_config_helper_funcs
2497 nv50_disp_helper_func = {
2498 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2499 };
2500
2501 /******************************************************************************
2502 * Init
2503 *****************************************************************************/
2504
2505 static void
nv50_display_fini(struct drm_device * dev,bool runtime,bool suspend)2506 nv50_display_fini(struct drm_device *dev, bool runtime, bool suspend)
2507 {
2508 struct nouveau_drm *drm = nouveau_drm(dev);
2509 struct drm_encoder *encoder;
2510
2511 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2512 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
2513 nv50_mstm_fini(nouveau_encoder(encoder));
2514 }
2515
2516 if (!runtime)
2517 cancel_work_sync(&drm->hpd_work);
2518 }
2519
2520 static int
nv50_display_init(struct drm_device * dev,bool resume,bool runtime)2521 nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2522 {
2523 struct nv50_core *core = nv50_disp(dev)->core;
2524 struct drm_encoder *encoder;
2525
2526 if (resume || runtime)
2527 core->func->init(core);
2528
2529 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2530 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2531 struct nouveau_encoder *nv_encoder =
2532 nouveau_encoder(encoder);
2533 nv50_mstm_init(nv_encoder, runtime);
2534 }
2535 }
2536
2537 return 0;
2538 }
2539
2540 static void
nv50_display_destroy(struct drm_device * dev)2541 nv50_display_destroy(struct drm_device *dev)
2542 {
2543 struct nv50_disp *disp = nv50_disp(dev);
2544
2545 nv50_audio_component_fini(nouveau_drm(dev));
2546
2547 nvif_object_unmap(&disp->caps);
2548 nvif_object_dtor(&disp->caps);
2549 nv50_core_del(&disp->core);
2550
2551 nouveau_bo_unmap(disp->sync);
2552 if (disp->sync)
2553 nouveau_bo_unpin(disp->sync);
2554 nouveau_bo_ref(NULL, &disp->sync);
2555
2556 nouveau_display(dev)->priv = NULL;
2557 kfree(disp);
2558 }
2559
2560 int
nv50_display_create(struct drm_device * dev)2561 nv50_display_create(struct drm_device *dev)
2562 {
2563 struct nvif_device *device = &nouveau_drm(dev)->client.device;
2564 struct nouveau_drm *drm = nouveau_drm(dev);
2565 struct dcb_table *dcb = &drm->vbios.dcb;
2566 struct drm_connector *connector, *tmp;
2567 struct nv50_disp *disp;
2568 struct dcb_output *dcbe;
2569 int crtcs, ret, i;
2570 bool has_mst = nv50_has_mst(drm);
2571
2572 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2573 if (!disp)
2574 return -ENOMEM;
2575
2576 mutex_init(&disp->mutex);
2577
2578 nouveau_display(dev)->priv = disp;
2579 nouveau_display(dev)->dtor = nv50_display_destroy;
2580 nouveau_display(dev)->init = nv50_display_init;
2581 nouveau_display(dev)->fini = nv50_display_fini;
2582 disp->disp = &nouveau_display(dev)->disp;
2583 dev->mode_config.funcs = &nv50_disp_func;
2584 dev->mode_config.helper_private = &nv50_disp_helper_func;
2585 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2586 dev->mode_config.normalize_zpos = true;
2587
2588 /* small shared memory area we use for notifiers and semaphores */
2589 ret = nouveau_bo_new(&drm->client, 4096, 0x1000,
2590 NOUVEAU_GEM_DOMAIN_VRAM,
2591 0, 0x0000, NULL, NULL, &disp->sync);
2592 if (!ret) {
2593 ret = nouveau_bo_pin(disp->sync, NOUVEAU_GEM_DOMAIN_VRAM, true);
2594 if (!ret) {
2595 ret = nouveau_bo_map(disp->sync);
2596 if (ret)
2597 nouveau_bo_unpin(disp->sync);
2598 }
2599 if (ret)
2600 nouveau_bo_ref(NULL, &disp->sync);
2601 }
2602
2603 if (ret)
2604 goto out;
2605
2606 /* allocate master evo channel */
2607 ret = nv50_core_new(drm, &disp->core);
2608 if (ret)
2609 goto out;
2610
2611 disp->core->func->init(disp->core);
2612 if (disp->core->func->caps_init) {
2613 ret = disp->core->func->caps_init(drm, disp);
2614 if (ret)
2615 goto out;
2616 }
2617
2618 /* Assign the correct format modifiers */
2619 if (disp->disp->object.oclass >= TU102_DISP)
2620 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers;
2621 else
2622 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI)
2623 nouveau_display(dev)->format_modifiers = disp90xx_modifiers;
2624 else
2625 nouveau_display(dev)->format_modifiers = disp50xx_modifiers;
2626
2627 /* FIXME: 256x256 cursors are supported on Kepler, however unlike Maxwell and later
2628 * generations Kepler requires that we use small pages (4K) for cursor scanout surfaces. The
2629 * proper fix for this is to teach nouveau to migrate fbs being used for the cursor plane to
2630 * small page allocations in prepare_fb(). When this is implemented, we should also force
2631 * large pages (128K) for ovly fbs in order to fix Kepler ovlys.
2632 * But until then, just limit cursors to 128x128 - which is small enough to avoid ever using
2633 * large pages.
2634 */
2635 if (disp->disp->object.oclass >= GM107_DISP) {
2636 dev->mode_config.cursor_width = 256;
2637 dev->mode_config.cursor_height = 256;
2638 } else if (disp->disp->object.oclass >= GK104_DISP) {
2639 dev->mode_config.cursor_width = 128;
2640 dev->mode_config.cursor_height = 128;
2641 } else {
2642 dev->mode_config.cursor_width = 64;
2643 dev->mode_config.cursor_height = 64;
2644 }
2645
2646 /* create crtc objects to represent the hw heads */
2647 if (disp->disp->object.oclass >= GV100_DISP)
2648 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2649 else
2650 if (disp->disp->object.oclass >= GF110_DISP)
2651 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2652 else
2653 crtcs = 0x3;
2654
2655 for (i = 0; i < fls(crtcs); i++) {
2656 struct nv50_head *head;
2657
2658 if (!(crtcs & (1 << i)))
2659 continue;
2660
2661 head = nv50_head_create(dev, i);
2662 if (IS_ERR(head)) {
2663 ret = PTR_ERR(head);
2664 goto out;
2665 }
2666
2667 if (has_mst) {
2668 head->msto = nv50_msto_new(dev, head, i);
2669 if (IS_ERR(head->msto)) {
2670 ret = PTR_ERR(head->msto);
2671 head->msto = NULL;
2672 goto out;
2673 }
2674
2675 /*
2676 * FIXME: This is a hack to workaround the following
2677 * issues:
2678 *
2679 * https://gitlab.gnome.org/GNOME/mutter/issues/759
2680 * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277
2681 *
2682 * Once these issues are closed, this should be
2683 * removed
2684 */
2685 head->msto->encoder.possible_crtcs = crtcs;
2686 }
2687 }
2688
2689 /* create encoder/connector objects based on VBIOS DCB table */
2690 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2691 connector = nouveau_connector_create(dev, dcbe);
2692 if (IS_ERR(connector))
2693 continue;
2694
2695 if (dcbe->location == DCB_LOC_ON_CHIP) {
2696 switch (dcbe->type) {
2697 case DCB_OUTPUT_TMDS:
2698 case DCB_OUTPUT_LVDS:
2699 case DCB_OUTPUT_DP:
2700 ret = nv50_sor_create(connector, dcbe);
2701 break;
2702 case DCB_OUTPUT_ANALOG:
2703 ret = nv50_dac_create(connector, dcbe);
2704 break;
2705 default:
2706 ret = -ENODEV;
2707 break;
2708 }
2709 } else {
2710 ret = nv50_pior_create(connector, dcbe);
2711 }
2712
2713 if (ret) {
2714 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2715 dcbe->location, dcbe->type,
2716 ffs(dcbe->or) - 1, ret);
2717 ret = 0;
2718 }
2719 }
2720
2721 /* cull any connectors we created that don't have an encoder */
2722 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2723 if (connector->possible_encoders)
2724 continue;
2725
2726 NV_WARN(drm, "%s has no encoders, removing\n",
2727 connector->name);
2728 connector->funcs->destroy(connector);
2729 }
2730
2731 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2732 dev->vblank_disable_immediate = true;
2733
2734 nv50_audio_component_init(drm);
2735
2736 out:
2737 if (ret)
2738 nv50_display_destroy(dev);
2739 return ret;
2740 }
2741
2742 /******************************************************************************
2743 * Format modifiers
2744 *****************************************************************************/
2745
2746 /****************************************************************
2747 * Log2(block height) ----------------------------+ *
2748 * Page Kind ----------------------------------+ | *
2749 * Gob Height/Page Kind Generation ------+ | | *
2750 * Sector layout -------+ | | | *
2751 * Compression ------+ | | | | */
2752 const u64 disp50xx_modifiers[] = { /* | | | | | */
2753 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0),
2754 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1),
2755 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2),
2756 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3),
2757 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4),
2758 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5),
2759 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0),
2760 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1),
2761 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2),
2762 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3),
2763 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4),
2764 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5),
2765 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0),
2766 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1),
2767 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2),
2768 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3),
2769 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4),
2770 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5),
2771 DRM_FORMAT_MOD_LINEAR,
2772 DRM_FORMAT_MOD_INVALID
2773 };
2774
2775 /****************************************************************
2776 * Log2(block height) ----------------------------+ *
2777 * Page Kind ----------------------------------+ | *
2778 * Gob Height/Page Kind Generation ------+ | | *
2779 * Sector layout -------+ | | | *
2780 * Compression ------+ | | | | */
2781 const u64 disp90xx_modifiers[] = { /* | | | | | */
2782 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0),
2783 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1),
2784 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2),
2785 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3),
2786 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4),
2787 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5),
2788 DRM_FORMAT_MOD_LINEAR,
2789 DRM_FORMAT_MOD_INVALID
2790 };
2791