1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25
26 #ifndef __INTEL_DISPLAY_TYPES_H__
27 #define __INTEL_DISPLAY_TYPES_H__
28
29 #include <linux/i2c.h>
30 #include <linux/pm_qos.h>
31 #include <linux/pwm.h>
32 #include <linux/sched/clock.h>
33
34 #include <drm/display/drm_dp_dual_mode_helper.h>
35 #include <drm/display/drm_dp_mst_helper.h>
36 #include <drm/display/drm_dsc.h>
37 #include <drm/drm_atomic.h>
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_encoder.h>
40 #include <drm/drm_fourcc.h>
41 #include <drm/drm_framebuffer.h>
42 #include <drm/drm_probe_helper.h>
43 #include <drm/drm_rect.h>
44 #include <drm/drm_vblank.h>
45 #include <drm/drm_vblank_work.h>
46 #include <drm/i915_hdcp_interface.h>
47 #include <media/cec-notifier.h>
48
49 #include "i915_vma.h"
50 #include "i915_vma_types.h"
51 #include "intel_bios.h"
52 #include "intel_display.h"
53 #include "intel_display_limits.h"
54 #include "intel_display_power.h"
55 #include "intel_dpll_mgr.h"
56 #include "intel_wm_types.h"
57
58 struct drm_printer;
59 struct __intel_global_objs_state;
60 struct intel_ddi_buf_trans;
61 struct intel_fbc;
62 struct intel_connector;
63 struct intel_tc_port;
64
65 /*
66 * Display related stuff
67 */
68
69 /* these are outputs from the chip - integrated only
70 external chips are via DVO or SDVO output */
71 enum intel_output_type {
72 INTEL_OUTPUT_UNUSED = 0,
73 INTEL_OUTPUT_ANALOG = 1,
74 INTEL_OUTPUT_DVO = 2,
75 INTEL_OUTPUT_SDVO = 3,
76 INTEL_OUTPUT_LVDS = 4,
77 INTEL_OUTPUT_TVOUT = 5,
78 INTEL_OUTPUT_HDMI = 6,
79 INTEL_OUTPUT_DP = 7,
80 INTEL_OUTPUT_EDP = 8,
81 INTEL_OUTPUT_DSI = 9,
82 INTEL_OUTPUT_DDI = 10,
83 INTEL_OUTPUT_DP_MST = 11,
84 };
85
86 enum hdmi_force_audio {
87 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
88 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
89 HDMI_AUDIO_AUTO, /* trust EDID */
90 HDMI_AUDIO_ON, /* force turn on HDMI audio */
91 };
92
93 /* "Broadcast RGB" property */
94 enum intel_broadcast_rgb {
95 INTEL_BROADCAST_RGB_AUTO,
96 INTEL_BROADCAST_RGB_FULL,
97 INTEL_BROADCAST_RGB_LIMITED,
98 };
99
100 struct intel_fb_view {
101 /*
102 * The remap information used in the remapped and rotated views to
103 * create the DMA scatter-gather list for each FB color plane. This sg
104 * list is created along with the view type (gtt.type) specific
105 * i915_vma object and contains the list of FB object pages (reordered
106 * in the rotated view) that are visible in the view.
107 * In the normal view the FB object's backing store sg list is used
108 * directly and hence the remap information here is not used.
109 */
110 struct i915_gtt_view gtt;
111
112 /*
113 * The GTT view (gtt.type) specific information for each FB color
114 * plane. In the normal GTT view all formats (up to 4 color planes),
115 * in the rotated and remapped GTT view all no-CCS formats (up to 2
116 * color planes) are supported.
117 *
118 * The view information shared by all FB color planes in the FB,
119 * like dst x/y and src/dst width, is stored separately in
120 * intel_plane_state.
121 */
122 struct i915_color_plane_view {
123 u32 offset;
124 unsigned int x, y;
125 /*
126 * Plane stride in:
127 * bytes for 0/180 degree rotation
128 * pixels for 90/270 degree rotation
129 */
130 unsigned int mapping_stride;
131 unsigned int scanout_stride;
132 } color_plane[4];
133 };
134
135 struct intel_framebuffer {
136 struct drm_framebuffer base;
137 struct intel_frontbuffer *frontbuffer;
138
139 /* Params to remap the FB pages and program the plane registers in each view. */
140 struct intel_fb_view normal_view;
141 union {
142 struct intel_fb_view rotated_view;
143 struct intel_fb_view remapped_view;
144 };
145
146 struct i915_address_space *dpt_vm;
147 };
148
149 enum intel_hotplug_state {
150 INTEL_HOTPLUG_UNCHANGED,
151 INTEL_HOTPLUG_CHANGED,
152 INTEL_HOTPLUG_RETRY,
153 };
154
155 struct intel_encoder {
156 struct drm_encoder base;
157
158 enum intel_output_type type;
159 enum port port;
160 u16 cloneable;
161 u8 pipe_mask;
162 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
163 struct intel_connector *connector);
164 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
165 struct intel_crtc_state *,
166 struct drm_connector_state *);
167 int (*compute_config)(struct intel_encoder *,
168 struct intel_crtc_state *,
169 struct drm_connector_state *);
170 int (*compute_config_late)(struct intel_encoder *,
171 struct intel_crtc_state *,
172 struct drm_connector_state *);
173 void (*pre_pll_enable)(struct intel_atomic_state *,
174 struct intel_encoder *,
175 const struct intel_crtc_state *,
176 const struct drm_connector_state *);
177 void (*pre_enable)(struct intel_atomic_state *,
178 struct intel_encoder *,
179 const struct intel_crtc_state *,
180 const struct drm_connector_state *);
181 void (*enable)(struct intel_atomic_state *,
182 struct intel_encoder *,
183 const struct intel_crtc_state *,
184 const struct drm_connector_state *);
185 void (*disable)(struct intel_atomic_state *,
186 struct intel_encoder *,
187 const struct intel_crtc_state *,
188 const struct drm_connector_state *);
189 void (*post_disable)(struct intel_atomic_state *,
190 struct intel_encoder *,
191 const struct intel_crtc_state *,
192 const struct drm_connector_state *);
193 void (*post_pll_disable)(struct intel_atomic_state *,
194 struct intel_encoder *,
195 const struct intel_crtc_state *,
196 const struct drm_connector_state *);
197 void (*update_pipe)(struct intel_atomic_state *,
198 struct intel_encoder *,
199 const struct intel_crtc_state *,
200 const struct drm_connector_state *);
201 /* Read out the current hw state of this connector, returning true if
202 * the encoder is active. If the encoder is enabled it also set the pipe
203 * it is connected to in the pipe parameter. */
204 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
205 /* Reconstructs the equivalent mode flags for the current hardware
206 * state. This must be called _after_ display->get_pipe_config has
207 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
208 * be set correctly before calling this function. */
209 void (*get_config)(struct intel_encoder *,
210 struct intel_crtc_state *pipe_config);
211
212 /*
213 * Optional hook called during init/resume to sync any state
214 * stored in the encoder (eg. DP link parameters) wrt. the HW state.
215 */
216 void (*sync_state)(struct intel_encoder *encoder,
217 const struct intel_crtc_state *crtc_state);
218
219 /*
220 * Optional hook, returning true if this encoder allows a fastset
221 * during the initial commit, false otherwise.
222 */
223 bool (*initial_fastset_check)(struct intel_encoder *encoder,
224 struct intel_crtc_state *crtc_state);
225
226 /*
227 * Acquires the power domains needed for an active encoder during
228 * hardware state readout.
229 */
230 void (*get_power_domains)(struct intel_encoder *encoder,
231 struct intel_crtc_state *crtc_state);
232 /*
233 * Called during system suspend after all pending requests for the
234 * encoder are flushed (for example for DP AUX transactions) and
235 * device interrupts are disabled.
236 * All modeset locks are held while the hook is called.
237 */
238 void (*suspend)(struct intel_encoder *);
239 /*
240 * Called without the modeset locks held after the suspend() hook for
241 * all encoders have been called.
242 */
243 void (*suspend_complete)(struct intel_encoder *encoder);
244 /*
245 * Called during system reboot/shutdown after all the
246 * encoders have been disabled and suspended.
247 * All modeset locks are held while the hook is called.
248 */
249 void (*shutdown)(struct intel_encoder *encoder);
250 /*
251 * Called without the modeset locks held after the shutdown() hook for
252 * all encoders have been called.
253 */
254 void (*shutdown_complete)(struct intel_encoder *encoder);
255 /*
256 * Enable/disable the clock to the port.
257 */
258 void (*enable_clock)(struct intel_encoder *encoder,
259 const struct intel_crtc_state *crtc_state);
260 void (*disable_clock)(struct intel_encoder *encoder);
261 /*
262 * Returns whether the port clock is enabled or not.
263 */
264 bool (*is_clock_enabled)(struct intel_encoder *encoder);
265 /*
266 * Returns the PLL type the port uses.
267 */
268 enum icl_port_dpll_id (*port_pll_type)(struct intel_encoder *encoder,
269 const struct intel_crtc_state *crtc_state);
270 const struct intel_ddi_buf_trans *(*get_buf_trans)(struct intel_encoder *encoder,
271 const struct intel_crtc_state *crtc_state,
272 int *n_entries);
273 void (*set_signal_levels)(struct intel_encoder *encoder,
274 const struct intel_crtc_state *crtc_state);
275
276 enum hpd_pin hpd_pin;
277 enum intel_display_power_domain power_domain;
278
279 /* VBT information for this encoder (may be NULL for older platforms) */
280 const struct intel_bios_encoder_data *devdata;
281 };
282
283 struct intel_panel_bl_funcs {
284 /* Connector and platform specific backlight functions */
285 int (*setup)(struct intel_connector *connector, enum pipe pipe);
286 u32 (*get)(struct intel_connector *connector, enum pipe pipe);
287 void (*set)(const struct drm_connector_state *conn_state, u32 level);
288 void (*disable)(const struct drm_connector_state *conn_state, u32 level);
289 void (*enable)(const struct intel_crtc_state *crtc_state,
290 const struct drm_connector_state *conn_state, u32 level);
291 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
292 };
293
294 enum drrs_type {
295 DRRS_TYPE_NONE,
296 DRRS_TYPE_STATIC,
297 DRRS_TYPE_SEAMLESS,
298 };
299
300 struct intel_vbt_panel_data {
301 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
302 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
303
304 /* Feature bits */
305 int panel_type;
306 unsigned int lvds_dither:1;
307 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
308
309 bool vrr;
310
311 u8 seamless_drrs_min_refresh_rate;
312 enum drrs_type drrs_type;
313
314 struct {
315 int max_link_rate;
316 int rate;
317 int lanes;
318 int preemphasis;
319 int vswing;
320 int bpp;
321 struct edp_power_seq pps;
322 u8 drrs_msa_timing_delay;
323 bool low_vswing;
324 bool initialized;
325 bool hobl;
326 } edp;
327
328 struct {
329 bool enable;
330 bool full_link;
331 bool require_aux_wakeup;
332 int idle_frames;
333 int tp1_wakeup_time_us;
334 int tp2_tp3_wakeup_time_us;
335 int psr2_tp2_tp3_wakeup_time_us;
336 } psr;
337
338 struct {
339 u16 pwm_freq_hz;
340 u16 brightness_precision_bits;
341 u16 hdr_dpcd_refresh_timeout;
342 bool present;
343 bool active_low_pwm;
344 u8 min_brightness; /* min_brightness/255 of max */
345 s8 controller; /* brightness controller number */
346 enum intel_backlight_type type;
347 } backlight;
348
349 /* MIPI DSI */
350 struct {
351 u16 panel_id;
352 struct mipi_config *config;
353 struct mipi_pps_data *pps;
354 u16 bl_ports;
355 u16 cabc_ports;
356 u8 seq_version;
357 u32 size;
358 u8 *data;
359 const u8 *sequence[MIPI_SEQ_MAX];
360 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
361 enum drm_panel_orientation orientation;
362 } dsi;
363 };
364
365 struct intel_panel {
366 /* Fixed EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
367 const struct drm_edid *fixed_edid;
368
369 struct list_head fixed_modes;
370
371 /* backlight */
372 struct {
373 bool present;
374 u32 level;
375 u32 min;
376 u32 max;
377 bool enabled;
378 bool combination_mode; /* gen 2/4 only */
379 bool active_low_pwm;
380 bool alternate_pwm_increment; /* lpt+ */
381
382 /* PWM chip */
383 u32 pwm_level_min;
384 u32 pwm_level_max;
385 bool pwm_enabled;
386 bool util_pin_active_low; /* bxt+ */
387 u8 controller; /* bxt+ only */
388 struct pwm_device *pwm;
389 struct pwm_state pwm_state;
390
391 /* DPCD backlight */
392 union {
393 struct {
394 struct drm_edp_backlight_info info;
395 } vesa;
396 struct {
397 bool sdr_uses_aux;
398 } intel;
399 } edp;
400
401 struct backlight_device *device;
402
403 const struct intel_panel_bl_funcs *funcs;
404 const struct intel_panel_bl_funcs *pwm_funcs;
405 void (*power)(struct intel_connector *, bool enable);
406 } backlight;
407
408 struct intel_vbt_panel_data vbt;
409 };
410
411 struct intel_digital_port;
412
413 enum check_link_response {
414 HDCP_LINK_PROTECTED = 0,
415 HDCP_TOPOLOGY_CHANGE,
416 HDCP_LINK_INTEGRITY_FAILURE,
417 HDCP_REAUTH_REQUEST
418 };
419
420 /*
421 * This structure serves as a translation layer between the generic HDCP code
422 * and the bus-specific code. What that means is that HDCP over HDMI differs
423 * from HDCP over DP, so to account for these differences, we need to
424 * communicate with the receiver through this shim.
425 *
426 * For completeness, the 2 buses differ in the following ways:
427 * - DP AUX vs. DDC
428 * HDCP registers on the receiver are set via DP AUX for DP, and
429 * they are set via DDC for HDMI.
430 * - Receiver register offsets
431 * The offsets of the registers are different for DP vs. HDMI
432 * - Receiver register masks/offsets
433 * For instance, the ready bit for the KSV fifo is in a different
434 * place on DP vs HDMI
435 * - Receiver register names
436 * Seriously. In the DP spec, the 16-bit register containing
437 * downstream information is called BINFO, on HDMI it's called
438 * BSTATUS. To confuse matters further, DP has a BSTATUS register
439 * with a completely different definition.
440 * - KSV FIFO
441 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
442 * be read 3 keys at a time
443 * - Aksv output
444 * Since Aksv is hidden in hardware, there's different procedures
445 * to send it over DP AUX vs DDC
446 */
447 struct intel_hdcp_shim {
448 /* Outputs the transmitter's An and Aksv values to the receiver. */
449 int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an);
450
451 /* Reads the receiver's key selection vector */
452 int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv);
453
454 /*
455 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
456 * definitions are the same in the respective specs, but the names are
457 * different. Call it BSTATUS since that's the name the HDMI spec
458 * uses and it was there first.
459 */
460 int (*read_bstatus)(struct intel_digital_port *dig_port,
461 u8 *bstatus);
462
463 /* Determines whether a repeater is present downstream */
464 int (*repeater_present)(struct intel_digital_port *dig_port,
465 bool *repeater_present);
466
467 /* Reads the receiver's Ri' value */
468 int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri);
469
470 /* Determines if the receiver's KSV FIFO is ready for consumption */
471 int (*read_ksv_ready)(struct intel_digital_port *dig_port,
472 bool *ksv_ready);
473
474 /* Reads the ksv fifo for num_downstream devices */
475 int (*read_ksv_fifo)(struct intel_digital_port *dig_port,
476 int num_downstream, u8 *ksv_fifo);
477
478 /* Reads a 32-bit part of V' from the receiver */
479 int (*read_v_prime_part)(struct intel_digital_port *dig_port,
480 int i, u32 *part);
481
482 /* Enables HDCP signalling on the port */
483 int (*toggle_signalling)(struct intel_digital_port *dig_port,
484 enum transcoder cpu_transcoder,
485 bool enable);
486
487 /* Enable/Disable stream encryption on DP MST Transport Link */
488 int (*stream_encryption)(struct intel_connector *connector,
489 bool enable);
490
491 /* Ensures the link is still protected */
492 bool (*check_link)(struct intel_digital_port *dig_port,
493 struct intel_connector *connector);
494
495 /* Detects panel's hdcp capability. This is optional for HDMI. */
496 int (*hdcp_capable)(struct intel_digital_port *dig_port,
497 bool *hdcp_capable);
498
499 /* HDCP adaptation(DP/HDMI) required on the port */
500 enum hdcp_wired_protocol protocol;
501
502 /* Detects whether sink is HDCP2.2 capable */
503 int (*hdcp_2_2_capable)(struct intel_digital_port *dig_port,
504 bool *capable);
505
506 /* Write HDCP2.2 messages */
507 int (*write_2_2_msg)(struct intel_digital_port *dig_port,
508 void *buf, size_t size);
509
510 /* Read HDCP2.2 messages */
511 int (*read_2_2_msg)(struct intel_digital_port *dig_port,
512 u8 msg_id, void *buf, size_t size);
513
514 /*
515 * Implementation of DP HDCP2.2 Errata for the communication of stream
516 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
517 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
518 */
519 int (*config_stream_type)(struct intel_digital_port *dig_port,
520 bool is_repeater, u8 type);
521
522 /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
523 int (*stream_2_2_encryption)(struct intel_connector *connector,
524 bool enable);
525
526 /* HDCP2.2 Link Integrity Check */
527 int (*check_2_2_link)(struct intel_digital_port *dig_port,
528 struct intel_connector *connector);
529 };
530
531 struct intel_hdcp {
532 const struct intel_hdcp_shim *shim;
533 /* Mutex for hdcp state of the connector */
534 struct mutex mutex;
535 u64 value;
536 struct delayed_work check_work;
537 struct work_struct prop_work;
538
539 /* HDCP1.4 Encryption status */
540 bool hdcp_encrypted;
541
542 /* HDCP2.2 related definitions */
543 /* Flag indicates whether this connector supports HDCP2.2 or not. */
544 bool hdcp2_supported;
545
546 /* HDCP2.2 Encryption status */
547 bool hdcp2_encrypted;
548
549 /*
550 * Content Stream Type defined by content owner. TYPE0(0x0) content can
551 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
552 * content can flow only through a link protected by HDCP2.2.
553 */
554 u8 content_type;
555
556 bool is_paired;
557 bool is_repeater;
558
559 /*
560 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
561 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
562 * When it rolls over re-auth has to be triggered.
563 */
564 u32 seq_num_v;
565
566 /*
567 * Count of RepeaterAuth_Stream_Manage msg propagated.
568 * Initialized to 0 on AKE_INIT. Incremented after every successful
569 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
570 * over re-Auth has to be triggered.
571 */
572 u32 seq_num_m;
573
574 /*
575 * Work queue to signal the CP_IRQ. Used for the waiters to read the
576 * available information from HDCP DP sink.
577 */
578 wait_queue_head_t cp_irq_queue;
579 atomic_t cp_irq_count;
580 int cp_irq_count_cached;
581
582 /*
583 * HDCP register access for gen12+ need the transcoder associated.
584 * Transcoder attached to the connector could be changed at modeset.
585 * Hence caching the transcoder here.
586 */
587 enum transcoder cpu_transcoder;
588 /* Only used for DP MST stream encryption */
589 enum transcoder stream_transcoder;
590 };
591
592 struct intel_connector {
593 struct drm_connector base;
594 /*
595 * The fixed encoder this connector is connected to.
596 */
597 struct intel_encoder *encoder;
598
599 /* ACPI device id for ACPI and driver cooperation */
600 u32 acpi_device_id;
601
602 /* Reads out the current hw, returning true if the connector is enabled
603 * and active (i.e. dpms ON state). */
604 bool (*get_hw_state)(struct intel_connector *);
605
606 /* Panel info for eDP and LVDS */
607 struct intel_panel panel;
608
609 /* Cached EDID for detect. */
610 const struct drm_edid *detect_edid;
611
612 /* Number of times hotplug detection was tried after an HPD interrupt */
613 int hotplug_retries;
614
615 /* since POLL and HPD connectors may use the same HPD line keep the native
616 state of connector->polled in case hotplug storm detection changes it */
617 u8 polled;
618
619 struct drm_dp_mst_port *port;
620
621 struct intel_dp *mst_port;
622
623 /* Work struct to schedule a uevent on link train failure */
624 struct work_struct modeset_retry_work;
625
626 struct intel_hdcp hdcp;
627 };
628
629 struct intel_digital_connector_state {
630 struct drm_connector_state base;
631
632 enum hdmi_force_audio force_audio;
633 int broadcast_rgb;
634 };
635
636 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
637
638 struct dpll {
639 /* given values */
640 int n;
641 int m1, m2;
642 int p1, p2;
643 /* derived values */
644 int dot;
645 int vco;
646 int m;
647 int p;
648 };
649
650 struct intel_atomic_state {
651 struct drm_atomic_state base;
652
653 intel_wakeref_t wakeref;
654
655 struct __intel_global_objs_state *global_objs;
656 int num_global_objs;
657
658 /* Internal commit, as opposed to userspace/client initiated one */
659 bool internal;
660
661 bool dpll_set, modeset;
662
663 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
664
665 /*
666 * Current watermarks can't be trusted during hardware readout, so
667 * don't bother calculating intermediate watermarks.
668 */
669 bool skip_intermediate_wm;
670
671 bool rps_interactive;
672
673 struct i915_sw_fence commit_ready;
674
675 struct llist_node freed;
676 };
677
678 struct intel_plane_state {
679 struct drm_plane_state uapi;
680
681 /*
682 * actual hardware state, the state we program to the hardware.
683 * The following members are used to verify the hardware state:
684 * During initial hw readout, they need to be copied from uapi.
685 */
686 struct {
687 struct drm_crtc *crtc;
688 struct drm_framebuffer *fb;
689
690 u16 alpha;
691 u16 pixel_blend_mode;
692 unsigned int rotation;
693 enum drm_color_encoding color_encoding;
694 enum drm_color_range color_range;
695 enum drm_scaling_filter scaling_filter;
696 } hw;
697
698 struct i915_vma *ggtt_vma;
699 struct i915_vma *dpt_vma;
700 unsigned long flags;
701 #define PLANE_HAS_FENCE BIT(0)
702
703 struct intel_fb_view view;
704 u32 phys_dma_addr; /* for cursor_needs_physical */
705
706 /* Plane pxp decryption state */
707 bool decrypt;
708
709 /* Plane state to display black pixels when pxp is borked */
710 bool force_black;
711
712 /* plane control register */
713 u32 ctl;
714
715 /* plane color control register */
716 u32 color_ctl;
717
718 /* chroma upsampler control register */
719 u32 cus_ctl;
720
721 /*
722 * scaler_id
723 * = -1 : not using a scaler
724 * >= 0 : using a scalers
725 *
726 * plane requiring a scaler:
727 * - During check_plane, its bit is set in
728 * crtc_state->scaler_state.scaler_users by calling helper function
729 * update_scaler_plane.
730 * - scaler_id indicates the scaler it got assigned.
731 *
732 * plane doesn't require a scaler:
733 * - this can happen when scaling is no more required or plane simply
734 * got disabled.
735 * - During check_plane, corresponding bit is reset in
736 * crtc_state->scaler_state.scaler_users by calling helper function
737 * update_scaler_plane.
738 */
739 int scaler_id;
740
741 /*
742 * planar_linked_plane:
743 *
744 * ICL planar formats require 2 planes that are updated as pairs.
745 * This member is used to make sure the other plane is also updated
746 * when required, and for update_slave() to find the correct
747 * plane_state to pass as argument.
748 */
749 struct intel_plane *planar_linked_plane;
750
751 /*
752 * planar_slave:
753 * If set don't update use the linked plane's state for updating
754 * this plane during atomic commit with the update_slave() callback.
755 *
756 * It's also used by the watermark code to ignore wm calculations on
757 * this plane. They're calculated by the linked plane's wm code.
758 */
759 u32 planar_slave;
760
761 struct drm_intel_sprite_colorkey ckey;
762
763 struct drm_rect psr2_sel_fetch_area;
764
765 /* Clear Color Value */
766 u64 ccval;
767
768 const char *no_fbc_reason;
769 };
770
771 struct intel_initial_plane_config {
772 struct intel_framebuffer *fb;
773 struct i915_vma *vma;
774 unsigned int tiling;
775 int size;
776 u32 base;
777 u8 rotation;
778 };
779
780 struct intel_scaler {
781 int in_use;
782 u32 mode;
783 };
784
785 struct intel_crtc_scaler_state {
786 #define SKL_NUM_SCALERS 2
787 struct intel_scaler scalers[SKL_NUM_SCALERS];
788
789 /*
790 * scaler_users: keeps track of users requesting scalers on this crtc.
791 *
792 * If a bit is set, a user is using a scaler.
793 * Here user can be a plane or crtc as defined below:
794 * bits 0-30 - plane (bit position is index from drm_plane_index)
795 * bit 31 - crtc
796 *
797 * Instead of creating a new index to cover planes and crtc, using
798 * existing drm_plane_index for planes which is well less than 31
799 * planes and bit 31 for crtc. This should be fine to cover all
800 * our platforms.
801 *
802 * intel_atomic_setup_scalers will setup available scalers to users
803 * requesting scalers. It will gracefully fail if request exceeds
804 * avilability.
805 */
806 #define SKL_CRTC_INDEX 31
807 unsigned scaler_users;
808
809 /* scaler used by crtc for panel fitting purpose */
810 int scaler_id;
811 };
812
813 /* {crtc,crtc_state}->mode_flags */
814 /* Flag to get scanline using frame time stamps */
815 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
816 /* Flag to use the scanline counter instead of the pixel counter */
817 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
818 /*
819 * TE0 or TE1 flag is set if the crtc has a DSI encoder which
820 * is operating in command mode.
821 * Flag to use TE from DSI0 instead of VBI in command mode
822 */
823 #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
824 /* Flag to use TE from DSI1 instead of VBI in command mode */
825 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
826 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */
827 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
828 /* Do tricks to make vblank timestamps sane with VRR? */
829 #define I915_MODE_FLAG_VRR (1<<6)
830
831 struct intel_wm_level {
832 bool enable;
833 u32 pri_val;
834 u32 spr_val;
835 u32 cur_val;
836 u32 fbc_val;
837 };
838
839 struct intel_pipe_wm {
840 struct intel_wm_level wm[5];
841 bool fbc_wm_enabled;
842 bool pipe_enabled;
843 bool sprites_enabled;
844 bool sprites_scaled;
845 };
846
847 struct skl_wm_level {
848 u16 min_ddb_alloc;
849 u16 blocks;
850 u8 lines;
851 bool enable;
852 bool ignore_lines;
853 bool can_sagv;
854 };
855
856 struct skl_plane_wm {
857 struct skl_wm_level wm[8];
858 struct skl_wm_level uv_wm[8];
859 struct skl_wm_level trans_wm;
860 struct {
861 struct skl_wm_level wm0;
862 struct skl_wm_level trans_wm;
863 } sagv;
864 bool is_planar;
865 };
866
867 struct skl_pipe_wm {
868 struct skl_plane_wm planes[I915_MAX_PLANES];
869 bool use_sagv_wm;
870 };
871
872 enum vlv_wm_level {
873 VLV_WM_LEVEL_PM2,
874 VLV_WM_LEVEL_PM5,
875 VLV_WM_LEVEL_DDR_DVFS,
876 NUM_VLV_WM_LEVELS,
877 };
878
879 struct vlv_wm_state {
880 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
881 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
882 u8 num_levels;
883 bool cxsr;
884 };
885
886 struct vlv_fifo_state {
887 u16 plane[I915_MAX_PLANES];
888 };
889
890 enum g4x_wm_level {
891 G4X_WM_LEVEL_NORMAL,
892 G4X_WM_LEVEL_SR,
893 G4X_WM_LEVEL_HPLL,
894 NUM_G4X_WM_LEVELS,
895 };
896
897 struct g4x_wm_state {
898 struct g4x_pipe_wm wm;
899 struct g4x_sr_wm sr;
900 struct g4x_sr_wm hpll;
901 bool cxsr;
902 bool hpll_en;
903 bool fbc_en;
904 };
905
906 struct intel_crtc_wm_state {
907 union {
908 /*
909 * raw:
910 * The "raw" watermark values produced by the formula
911 * given the plane's current state. They do not consider
912 * how much FIFO is actually allocated for each plane.
913 *
914 * optimal:
915 * The "optimal" watermark values given the current
916 * state of the planes and the amount of FIFO
917 * allocated to each, ignoring any previous state
918 * of the planes.
919 *
920 * intermediate:
921 * The "intermediate" watermark values when transitioning
922 * between the old and new "optimal" values. Used when
923 * the watermark registers are single buffered and hence
924 * their state changes asynchronously with regards to the
925 * actual plane registers. These are essentially the
926 * worst case combination of the old and new "optimal"
927 * watermarks, which are therefore safe to use when the
928 * plane is in either its old or new state.
929 */
930 struct {
931 struct intel_pipe_wm intermediate;
932 struct intel_pipe_wm optimal;
933 } ilk;
934
935 struct {
936 struct skl_pipe_wm raw;
937 /* gen9+ only needs 1-step wm programming */
938 struct skl_pipe_wm optimal;
939 struct skl_ddb_entry ddb;
940 /*
941 * pre-icl: for packed/planar CbCr
942 * icl+: for everything
943 */
944 struct skl_ddb_entry plane_ddb[I915_MAX_PLANES];
945 /* pre-icl: for planar Y */
946 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
947 } skl;
948
949 struct {
950 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not inverted */
951 struct vlv_wm_state intermediate; /* inverted */
952 struct vlv_wm_state optimal; /* inverted */
953 struct vlv_fifo_state fifo_state;
954 } vlv;
955
956 struct {
957 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
958 struct g4x_wm_state intermediate;
959 struct g4x_wm_state optimal;
960 } g4x;
961 };
962
963 /*
964 * Platforms with two-step watermark programming will need to
965 * update watermark programming post-vblank to switch from the
966 * safe intermediate watermarks to the optimal final
967 * watermarks.
968 */
969 bool need_postvbl_update;
970 };
971
972 enum intel_output_format {
973 INTEL_OUTPUT_FORMAT_RGB,
974 INTEL_OUTPUT_FORMAT_YCBCR420,
975 INTEL_OUTPUT_FORMAT_YCBCR444,
976 };
977
978 struct intel_mpllb_state {
979 u32 clock; /* in KHz */
980 u32 ref_control;
981 u32 mpllb_cp;
982 u32 mpllb_div;
983 u32 mpllb_div2;
984 u32 mpllb_fracn1;
985 u32 mpllb_fracn2;
986 u32 mpllb_sscen;
987 u32 mpllb_sscstep;
988 };
989
990 /* Used by dp and fdi links */
991 struct intel_link_m_n {
992 u32 tu;
993 u32 data_m;
994 u32 data_n;
995 u32 link_m;
996 u32 link_n;
997 };
998
999 struct intel_csc_matrix {
1000 u16 coeff[9];
1001 u16 preoff[3];
1002 u16 postoff[3];
1003 };
1004
1005 struct intel_c10pll_state {
1006 u32 clock; /* in KHz */
1007 u8 tx;
1008 u8 cmn;
1009 u8 pll[20];
1010 };
1011
1012 struct intel_c20pll_state {
1013 u32 link_bit_rate;
1014 u32 clock; /* in kHz */
1015 u16 tx[3];
1016 u16 cmn[4];
1017 union {
1018 u16 mplla[10];
1019 u16 mpllb[11];
1020 };
1021 };
1022
1023 struct intel_cx0pll_state {
1024 union {
1025 struct intel_c10pll_state c10;
1026 struct intel_c20pll_state c20;
1027 };
1028 bool ssc_enabled;
1029 };
1030
1031 struct intel_crtc_state {
1032 /*
1033 * uapi (drm) state. This is the software state shown to userspace.
1034 * In particular, the following members are used for bookkeeping:
1035 * - crtc
1036 * - state
1037 * - *_changed
1038 * - event
1039 * - commit
1040 * - mode_blob
1041 */
1042 struct drm_crtc_state uapi;
1043
1044 /*
1045 * actual hardware state, the state we program to the hardware.
1046 * The following members are used to verify the hardware state:
1047 * - enable
1048 * - active
1049 * - mode / pipe_mode / adjusted_mode
1050 * - color property blobs.
1051 *
1052 * During initial hw readout, they need to be copied to uapi.
1053 *
1054 * Bigjoiner will allow a transcoder mode that spans 2 pipes;
1055 * Use the pipe_mode for calculations like watermarks, pipe
1056 * scaler, and bandwidth.
1057 *
1058 * Use adjusted_mode for things that need to know the full
1059 * mode on the transcoder, which spans all pipes.
1060 */
1061 struct {
1062 bool active, enable;
1063 /* logical state of LUTs */
1064 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
1065 struct drm_display_mode mode, pipe_mode, adjusted_mode;
1066 enum drm_scaling_filter scaling_filter;
1067 } hw;
1068
1069 /* actual state of LUTs */
1070 struct drm_property_blob *pre_csc_lut, *post_csc_lut;
1071
1072 struct intel_csc_matrix csc, output_csc;
1073
1074 /**
1075 * quirks - bitfield with hw state readout quirks
1076 *
1077 * For various reasons the hw state readout code might not be able to
1078 * completely faithfully read out the current state. These cases are
1079 * tracked with quirk flags so that fastboot and state checker can act
1080 * accordingly.
1081 */
1082 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
1083 unsigned long quirks;
1084
1085 unsigned fb_bits; /* framebuffers to flip */
1086 bool update_pipe; /* can a fast modeset be performed? */
1087 bool update_m_n; /* update M/N seamlessly during fastset? */
1088 bool disable_cxsr;
1089 bool update_wm_pre, update_wm_post; /* watermarks are updated */
1090 bool fifo_changed; /* FIFO split is changed */
1091 bool preload_luts;
1092 bool inherited; /* state inherited from BIOS? */
1093
1094 /* Ask the hardware to actually async flip? */
1095 bool do_async_flip;
1096
1097 /* Pipe source size (ie. panel fitter input size)
1098 * All planes will be positioned inside this space,
1099 * and get clipped at the edges. */
1100 struct drm_rect pipe_src;
1101
1102 /*
1103 * Pipe pixel rate, adjusted for
1104 * panel fitter/pipe scaler downscaling.
1105 */
1106 unsigned int pixel_rate;
1107
1108 /* Whether to set up the PCH/FDI. Note that we never allow sharing
1109 * between pch encoders and cpu encoders. */
1110 bool has_pch_encoder;
1111
1112 /* Are we sending infoframes on the attached port */
1113 bool has_infoframe;
1114
1115 /* CPU Transcoder for the pipe. Currently this can only differ from the
1116 * pipe on Haswell and later (where we have a special eDP transcoder)
1117 * and Broxton (where we have special DSI transcoders). */
1118 enum transcoder cpu_transcoder;
1119
1120 /*
1121 * Use reduced/limited/broadcast rbg range, compressing from the full
1122 * range fed into the crtcs.
1123 */
1124 bool limited_color_range;
1125
1126 /* Bitmask of encoder types (enum intel_output_type)
1127 * driven by the pipe.
1128 */
1129 unsigned int output_types;
1130
1131 /* Whether we should send NULL infoframes. Required for audio. */
1132 bool has_hdmi_sink;
1133
1134 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
1135 * has_dp_encoder is set. */
1136 bool has_audio;
1137
1138 /*
1139 * Enable dithering, used when the selected pipe bpp doesn't match the
1140 * plane bpp.
1141 */
1142 bool dither;
1143
1144 /*
1145 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
1146 * compliance video pattern tests.
1147 * Disable dither only if it is a compliance test request for
1148 * 18bpp.
1149 */
1150 bool dither_force_disable;
1151
1152 /* Controls for the clock computation, to override various stages. */
1153 bool clock_set;
1154
1155 /* SDVO TV has a bunch of special case. To make multifunction encoders
1156 * work correctly, we need to track this at runtime.*/
1157 bool sdvo_tv_clock;
1158
1159 /*
1160 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
1161 * required. This is set in the 2nd loop of calling encoder's
1162 * ->compute_config if the first pick doesn't work out.
1163 */
1164 bool bw_constrained;
1165
1166 /* Settings for the intel dpll used on pretty much everything but
1167 * haswell. */
1168 struct dpll dpll;
1169
1170 /* Selected dpll when shared or NULL. */
1171 struct intel_shared_dpll *shared_dpll;
1172
1173 /* Actual register state of the dpll, for shared dpll cross-checking. */
1174 union {
1175 struct intel_dpll_hw_state dpll_hw_state;
1176 struct intel_mpllb_state mpllb_state;
1177 struct intel_cx0pll_state cx0pll_state;
1178 };
1179
1180 /*
1181 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
1182 * setting shared_dpll and dpll_hw_state to one of these reserved ones.
1183 */
1184 struct icl_port_dpll {
1185 struct intel_shared_dpll *pll;
1186 struct intel_dpll_hw_state hw_state;
1187 } icl_port_dplls[ICL_PORT_DPLL_COUNT];
1188
1189 /* DSI PLL registers */
1190 struct {
1191 u32 ctrl, div;
1192 } dsi_pll;
1193
1194 int pipe_bpp;
1195 struct intel_link_m_n dp_m_n;
1196
1197 /* m2_n2 for eDP downclock */
1198 struct intel_link_m_n dp_m2_n2;
1199 bool has_drrs;
1200
1201 /* PSR is supported but might not be enabled due the lack of enabled planes */
1202 bool has_psr;
1203 bool has_psr2;
1204 bool enable_psr2_sel_fetch;
1205 bool req_psr2_sdp_prior_scanline;
1206 bool wm_level_disabled;
1207 u32 dc3co_exitline;
1208 u16 su_y_granularity;
1209 struct drm_dp_vsc_sdp psr_vsc;
1210
1211 /*
1212 * Frequence the dpll for the port should run at. Differs from the
1213 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also
1214 * already multiplied by pixel_multiplier.
1215 */
1216 int port_clock;
1217
1218 /* Used by SDVO (and if we ever fix it, HDMI). */
1219 unsigned pixel_multiplier;
1220
1221 /* I915_MODE_FLAG_* */
1222 u8 mode_flags;
1223
1224 u8 lane_count;
1225
1226 /*
1227 * Used by platforms having DP/HDMI PHY with programmable lane
1228 * latency optimization.
1229 */
1230 u8 lane_lat_optim_mask;
1231
1232 /* minimum acceptable voltage level */
1233 u8 min_voltage_level;
1234
1235 /* Panel fitter controls for gen2-gen4 + VLV */
1236 struct {
1237 u32 control;
1238 u32 pgm_ratios;
1239 u32 lvds_border_bits;
1240 } gmch_pfit;
1241
1242 /* Panel fitter placement and size for Ironlake+ */
1243 struct {
1244 struct drm_rect dst;
1245 bool enabled;
1246 bool force_thru;
1247 } pch_pfit;
1248
1249 /* FDI configuration, only valid if has_pch_encoder is set. */
1250 int fdi_lanes;
1251 struct intel_link_m_n fdi_m_n;
1252
1253 bool ips_enabled;
1254
1255 bool crc_enabled;
1256
1257 bool double_wide;
1258
1259 int pbn;
1260
1261 struct intel_crtc_scaler_state scaler_state;
1262
1263 /* w/a for waiting 2 vblanks during crtc enable */
1264 enum pipe hsw_workaround_pipe;
1265
1266 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
1267 bool disable_lp_wm;
1268
1269 struct intel_crtc_wm_state wm;
1270
1271 int min_cdclk[I915_MAX_PLANES];
1272
1273 /* for packed/planar CbCr */
1274 u32 data_rate[I915_MAX_PLANES];
1275 /* for planar Y */
1276 u32 data_rate_y[I915_MAX_PLANES];
1277
1278 /* FIXME unify with data_rate[]? */
1279 u64 rel_data_rate[I915_MAX_PLANES];
1280 u64 rel_data_rate_y[I915_MAX_PLANES];
1281
1282 /* Gamma mode programmed on the pipe */
1283 u32 gamma_mode;
1284
1285 union {
1286 /* CSC mode programmed on the pipe */
1287 u32 csc_mode;
1288
1289 /* CHV CGM mode */
1290 u32 cgm_mode;
1291 };
1292
1293 /* bitmask of logically enabled planes (enum plane_id) */
1294 u8 enabled_planes;
1295
1296 /* bitmask of actually visible planes (enum plane_id) */
1297 u8 active_planes;
1298 u8 scaled_planes;
1299 u8 nv12_planes;
1300 u8 c8_planes;
1301
1302 /* bitmask of planes that will be updated during the commit */
1303 u8 update_planes;
1304
1305 /* bitmask of planes with async flip active */
1306 u8 async_flip_planes;
1307
1308 u8 framestart_delay; /* 1-4 */
1309 u8 msa_timing_delay; /* 0-3 */
1310
1311 struct {
1312 u32 enable;
1313 u32 gcp;
1314 union hdmi_infoframe avi;
1315 union hdmi_infoframe spd;
1316 union hdmi_infoframe hdmi;
1317 union hdmi_infoframe drm;
1318 struct drm_dp_vsc_sdp vsc;
1319 } infoframes;
1320
1321 u8 eld[MAX_ELD_BYTES];
1322
1323 /* HDMI scrambling status */
1324 bool hdmi_scrambling;
1325
1326 /* HDMI High TMDS char rate ratio */
1327 bool hdmi_high_tmds_clock_ratio;
1328
1329 /*
1330 * Output format RGB/YCBCR etc., that is coming out
1331 * at the end of the pipe.
1332 */
1333 enum intel_output_format output_format;
1334
1335 /*
1336 * Sink output format RGB/YCBCR etc., that is going
1337 * into the sink.
1338 */
1339 enum intel_output_format sink_format;
1340
1341 /* enable pipe gamma? */
1342 bool gamma_enable;
1343
1344 /* enable pipe csc? */
1345 bool csc_enable;
1346
1347 /* enable vlv/chv wgc csc? */
1348 bool wgc_enable;
1349
1350 /* big joiner pipe bitmask */
1351 u8 bigjoiner_pipes;
1352
1353 /* Display Stream compression state */
1354 struct {
1355 bool compression_enable;
1356 bool dsc_split;
1357 u16 compressed_bpp;
1358 u8 slice_count;
1359 struct drm_dsc_config config;
1360 } dsc;
1361
1362 /* HSW+ linetime watermarks */
1363 u16 linetime;
1364 u16 ips_linetime;
1365
1366 bool enhanced_framing;
1367
1368 /* Forward Error correction State */
1369 bool fec_enable;
1370
1371 bool sdp_split_enable;
1372
1373 /* Pointer to master transcoder in case of tiled displays */
1374 enum transcoder master_transcoder;
1375
1376 /* Bitmask to indicate slaves attached */
1377 u8 sync_mode_slaves_mask;
1378
1379 /* Only valid on TGL+ */
1380 enum transcoder mst_master_transcoder;
1381
1382 /* For DSB related info */
1383 struct intel_dsb *dsb;
1384
1385 u32 psr2_man_track_ctl;
1386
1387 /* Variable Refresh Rate state */
1388 struct {
1389 bool enable;
1390 u8 pipeline_full;
1391 u16 flipline, vmin, vmax, guardband;
1392 } vrr;
1393
1394 /* Stream Splitter for eDP MSO */
1395 struct {
1396 bool enable;
1397 u8 link_count;
1398 u8 pixel_overlap;
1399 } splitter;
1400
1401 /* for loading single buffered registers during vblank */
1402 struct drm_vblank_work vblank_work;
1403 };
1404
1405 enum intel_pipe_crc_source {
1406 INTEL_PIPE_CRC_SOURCE_NONE,
1407 INTEL_PIPE_CRC_SOURCE_PLANE1,
1408 INTEL_PIPE_CRC_SOURCE_PLANE2,
1409 INTEL_PIPE_CRC_SOURCE_PLANE3,
1410 INTEL_PIPE_CRC_SOURCE_PLANE4,
1411 INTEL_PIPE_CRC_SOURCE_PLANE5,
1412 INTEL_PIPE_CRC_SOURCE_PLANE6,
1413 INTEL_PIPE_CRC_SOURCE_PLANE7,
1414 INTEL_PIPE_CRC_SOURCE_PIPE,
1415 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1416 INTEL_PIPE_CRC_SOURCE_TV,
1417 INTEL_PIPE_CRC_SOURCE_DP_B,
1418 INTEL_PIPE_CRC_SOURCE_DP_C,
1419 INTEL_PIPE_CRC_SOURCE_DP_D,
1420 INTEL_PIPE_CRC_SOURCE_AUTO,
1421 INTEL_PIPE_CRC_SOURCE_MAX,
1422 };
1423
1424 enum drrs_refresh_rate {
1425 DRRS_REFRESH_RATE_HIGH,
1426 DRRS_REFRESH_RATE_LOW,
1427 };
1428
1429 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1430 struct intel_pipe_crc {
1431 spinlock_t lock;
1432 int skipped;
1433 enum intel_pipe_crc_source source;
1434 };
1435
1436 struct intel_crtc {
1437 struct drm_crtc base;
1438 enum pipe pipe;
1439 /*
1440 * Whether the crtc and the connected output pipeline is active. Implies
1441 * that crtc->enabled is set, i.e. the current mode configuration has
1442 * some outputs connected to this crtc.
1443 */
1444 bool active;
1445 u8 plane_ids_mask;
1446
1447 /* I915_MODE_FLAG_* */
1448 u8 mode_flags;
1449
1450 u16 vmax_vblank_start;
1451
1452 struct intel_display_power_domain_set enabled_power_domains;
1453 struct intel_display_power_domain_set hw_readout_power_domains;
1454 struct intel_overlay *overlay;
1455
1456 struct intel_crtc_state *config;
1457
1458 /* Access to these should be protected by dev_priv->irq_lock. */
1459 bool cpu_fifo_underrun_disabled;
1460 bool pch_fifo_underrun_disabled;
1461
1462 /* per-pipe watermark state */
1463 struct {
1464 /* watermarks currently being used */
1465 union {
1466 struct intel_pipe_wm ilk;
1467 struct vlv_wm_state vlv;
1468 struct g4x_wm_state g4x;
1469 } active;
1470 } wm;
1471
1472 struct {
1473 struct mutex mutex;
1474 struct delayed_work work;
1475 enum drrs_refresh_rate refresh_rate;
1476 unsigned int frontbuffer_bits;
1477 unsigned int busy_frontbuffer_bits;
1478 enum transcoder cpu_transcoder;
1479 struct intel_link_m_n m_n, m2_n2;
1480 } drrs;
1481
1482 int scanline_offset;
1483
1484 struct {
1485 unsigned start_vbl_count;
1486 ktime_t start_vbl_time;
1487 int min_vbl, max_vbl;
1488 int scanline_start;
1489 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
1490 struct {
1491 u64 min;
1492 u64 max;
1493 u64 sum;
1494 unsigned int over;
1495 unsigned int times[17]; /* [1us, 16ms] */
1496 } vbl;
1497 #endif
1498 } debug;
1499
1500 /* scalers available on this crtc */
1501 int num_scalers;
1502
1503 /* for loading single buffered registers during vblank */
1504 struct pm_qos_request vblank_pm_qos;
1505
1506 #ifdef CONFIG_DEBUG_FS
1507 struct intel_pipe_crc pipe_crc;
1508 #endif
1509 };
1510
1511 struct intel_plane {
1512 struct drm_plane base;
1513 enum i9xx_plane_id i9xx_plane;
1514 enum plane_id id;
1515 enum pipe pipe;
1516 bool need_async_flip_disable_wa;
1517 u32 frontbuffer_bit;
1518
1519 struct {
1520 u32 base, cntl, size;
1521 } cursor;
1522
1523 struct intel_fbc *fbc;
1524
1525 /*
1526 * NOTE: Do not place new plane state fields here (e.g., when adding
1527 * new plane properties). New runtime state should now be placed in
1528 * the intel_plane_state structure and accessed via plane_state.
1529 */
1530
1531 int (*min_width)(const struct drm_framebuffer *fb,
1532 int color_plane,
1533 unsigned int rotation);
1534 int (*max_width)(const struct drm_framebuffer *fb,
1535 int color_plane,
1536 unsigned int rotation);
1537 int (*max_height)(const struct drm_framebuffer *fb,
1538 int color_plane,
1539 unsigned int rotation);
1540 unsigned int (*max_stride)(struct intel_plane *plane,
1541 u32 pixel_format, u64 modifier,
1542 unsigned int rotation);
1543 /* Write all non-self arming plane registers */
1544 void (*update_noarm)(struct intel_plane *plane,
1545 const struct intel_crtc_state *crtc_state,
1546 const struct intel_plane_state *plane_state);
1547 /* Write all self-arming plane registers */
1548 void (*update_arm)(struct intel_plane *plane,
1549 const struct intel_crtc_state *crtc_state,
1550 const struct intel_plane_state *plane_state);
1551 /* Disable the plane, must arm */
1552 void (*disable_arm)(struct intel_plane *plane,
1553 const struct intel_crtc_state *crtc_state);
1554 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1555 int (*check_plane)(struct intel_crtc_state *crtc_state,
1556 struct intel_plane_state *plane_state);
1557 int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1558 const struct intel_plane_state *plane_state);
1559 void (*async_flip)(struct intel_plane *plane,
1560 const struct intel_crtc_state *crtc_state,
1561 const struct intel_plane_state *plane_state,
1562 bool async_flip);
1563 void (*enable_flip_done)(struct intel_plane *plane);
1564 void (*disable_flip_done)(struct intel_plane *plane);
1565 };
1566
1567 struct intel_watermark_params {
1568 u16 fifo_size;
1569 u16 max_wm;
1570 u8 default_wm;
1571 u8 guard_size;
1572 u8 cacheline_size;
1573 };
1574
1575 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1576 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1577 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
1578 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1579 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1580 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1581 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1582 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
1583 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1584
1585 struct intel_hdmi {
1586 i915_reg_t hdmi_reg;
1587 int ddc_bus;
1588 struct {
1589 enum drm_dp_dual_mode_type type;
1590 int max_tmds_clock;
1591 } dp_dual_mode;
1592 struct intel_connector *attached_connector;
1593 struct cec_notifier *cec_notifier;
1594 };
1595
1596 struct intel_dp_mst_encoder;
1597
1598 struct intel_dp_compliance_data {
1599 unsigned long edid;
1600 u8 video_pattern;
1601 u16 hdisplay, vdisplay;
1602 u8 bpc;
1603 struct drm_dp_phy_test_params phytest;
1604 };
1605
1606 struct intel_dp_compliance {
1607 unsigned long test_type;
1608 struct intel_dp_compliance_data test_data;
1609 bool test_active;
1610 int test_link_rate;
1611 u8 test_lane_count;
1612 };
1613
1614 struct intel_dp_pcon_frl {
1615 bool is_trained;
1616 int trained_rate_gbps;
1617 };
1618
1619 struct intel_pps {
1620 int panel_power_up_delay;
1621 int panel_power_down_delay;
1622 int panel_power_cycle_delay;
1623 int backlight_on_delay;
1624 int backlight_off_delay;
1625 struct delayed_work panel_vdd_work;
1626 bool want_panel_vdd;
1627 bool initializing;
1628 unsigned long last_power_on;
1629 unsigned long last_backlight_off;
1630 ktime_t panel_power_off_time;
1631 intel_wakeref_t vdd_wakeref;
1632
1633 union {
1634 /*
1635 * Pipe whose power sequencer is currently locked into
1636 * this port. Only relevant on VLV/CHV.
1637 */
1638 enum pipe pps_pipe;
1639
1640 /*
1641 * Power sequencer index. Only relevant on BXT+.
1642 */
1643 int pps_idx;
1644 };
1645
1646 /*
1647 * Pipe currently driving the port. Used for preventing
1648 * the use of the PPS for any pipe currentrly driving
1649 * external DP as that will mess things up on VLV.
1650 */
1651 enum pipe active_pipe;
1652 /*
1653 * Set if the sequencer may be reset due to a power transition,
1654 * requiring a reinitialization. Only relevant on BXT+.
1655 */
1656 bool pps_reset;
1657 struct edp_power_seq pps_delays;
1658 struct edp_power_seq bios_pps_delays;
1659 };
1660
1661 struct intel_psr {
1662 /* Mutex for PSR state of the transcoder */
1663 struct mutex lock;
1664
1665 #define I915_PSR_DEBUG_MODE_MASK 0x0f
1666 #define I915_PSR_DEBUG_DEFAULT 0x00
1667 #define I915_PSR_DEBUG_DISABLE 0x01
1668 #define I915_PSR_DEBUG_ENABLE 0x02
1669 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
1670 #define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4
1671 #define I915_PSR_DEBUG_IRQ 0x10
1672
1673 u32 debug;
1674 bool sink_support;
1675 bool source_support;
1676 bool enabled;
1677 bool paused;
1678 enum pipe pipe;
1679 enum transcoder transcoder;
1680 bool active;
1681 struct work_struct work;
1682 unsigned int busy_frontbuffer_bits;
1683 bool sink_psr2_support;
1684 bool link_standby;
1685 bool colorimetry_support;
1686 bool psr2_enabled;
1687 bool psr2_sel_fetch_enabled;
1688 bool psr2_sel_fetch_cff_enabled;
1689 bool req_psr2_sdp_prior_scanline;
1690 u8 sink_sync_latency;
1691 u8 io_wake_lines;
1692 u8 fast_wake_lines;
1693 ktime_t last_entry_attempt;
1694 ktime_t last_exit;
1695 bool sink_not_reliable;
1696 bool irq_aux_error;
1697 u16 su_w_granularity;
1698 u16 su_y_granularity;
1699 u32 dc3co_exitline;
1700 u32 dc3co_exit_delay;
1701 struct delayed_work dc3co_work;
1702 };
1703
1704 struct intel_dp {
1705 i915_reg_t output_reg;
1706 u32 DP;
1707 int link_rate;
1708 u8 lane_count;
1709 u8 sink_count;
1710 bool link_trained;
1711 bool reset_link_params;
1712 bool use_max_params;
1713 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1714 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1715 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1716 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1717 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1718 u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
1719 u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
1720 u8 fec_capable;
1721 u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
1722 /* source rates */
1723 int num_source_rates;
1724 const int *source_rates;
1725 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1726 int num_sink_rates;
1727 int sink_rates[DP_MAX_SUPPORTED_RATES];
1728 bool use_rate_select;
1729 /* Max sink lane count as reported by DP_MAX_LANE_COUNT */
1730 int max_sink_lane_count;
1731 /* intersection of source and sink rates */
1732 int num_common_rates;
1733 int common_rates[DP_MAX_SUPPORTED_RATES];
1734 /* Max lane count for the current link */
1735 int max_link_lane_count;
1736 /* Max rate for the current link */
1737 int max_link_rate;
1738 int mso_link_count;
1739 int mso_pixel_overlap;
1740 /* sink or branch descriptor */
1741 struct drm_dp_desc desc;
1742 struct drm_dp_aux aux;
1743 u32 aux_busy_last_status;
1744 u8 train_set[4];
1745
1746 struct intel_pps pps;
1747
1748 bool is_mst;
1749 int active_mst_links;
1750
1751 /* connector directly attached - won't be use for modeset in mst world */
1752 struct intel_connector *attached_connector;
1753
1754 /* mst connector list */
1755 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1756 struct drm_dp_mst_topology_mgr mst_mgr;
1757
1758 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1759 /*
1760 * This function returns the value we have to program the AUX_CTL
1761 * register with to kick off an AUX transaction.
1762 */
1763 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1764 u32 aux_clock_divider);
1765
1766 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1767 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1768
1769 /* This is called before a link training is starterd */
1770 void (*prepare_link_retrain)(struct intel_dp *intel_dp,
1771 const struct intel_crtc_state *crtc_state);
1772 void (*set_link_train)(struct intel_dp *intel_dp,
1773 const struct intel_crtc_state *crtc_state,
1774 u8 dp_train_pat);
1775 void (*set_idle_link_train)(struct intel_dp *intel_dp,
1776 const struct intel_crtc_state *crtc_state);
1777
1778 u8 (*preemph_max)(struct intel_dp *intel_dp);
1779 u8 (*voltage_max)(struct intel_dp *intel_dp,
1780 const struct intel_crtc_state *crtc_state);
1781
1782 /* Displayport compliance testing */
1783 struct intel_dp_compliance compliance;
1784
1785 /* Downstream facing port caps */
1786 struct {
1787 int min_tmds_clock, max_tmds_clock;
1788 int max_dotclock;
1789 int pcon_max_frl_bw;
1790 u8 max_bpc;
1791 bool ycbcr_444_to_420;
1792 bool ycbcr420_passthrough;
1793 bool rgb_to_ycbcr;
1794 } dfp;
1795
1796 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1797 struct pm_qos_request pm_qos;
1798
1799 /* Display stream compression testing */
1800 bool force_dsc_en;
1801 int force_dsc_output_format;
1802 int force_dsc_bpc;
1803
1804 bool hobl_failed;
1805 bool hobl_active;
1806
1807 struct intel_dp_pcon_frl frl;
1808
1809 struct intel_psr psr;
1810
1811 /* When we last wrote the OUI for eDP */
1812 unsigned long last_oui_write;
1813 };
1814
1815 enum lspcon_vendor {
1816 LSPCON_VENDOR_MCA,
1817 LSPCON_VENDOR_PARADE
1818 };
1819
1820 struct intel_lspcon {
1821 bool active;
1822 bool hdr_supported;
1823 enum drm_lspcon_mode mode;
1824 enum lspcon_vendor vendor;
1825 };
1826
1827 struct intel_digital_port {
1828 struct intel_encoder base;
1829 u32 saved_port_bits;
1830 struct intel_dp dp;
1831 struct intel_hdmi hdmi;
1832 struct intel_lspcon lspcon;
1833 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1834 bool release_cl2_override;
1835 u8 max_lanes;
1836 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1837 enum aux_ch aux_ch;
1838 enum intel_display_power_domain ddi_io_power_domain;
1839 intel_wakeref_t ddi_io_wakeref;
1840 intel_wakeref_t aux_wakeref;
1841
1842 struct intel_tc_port *tc;
1843
1844 /* protects num_hdcp_streams reference count, hdcp_port_data and hdcp_auth_status */
1845 struct mutex hdcp_mutex;
1846 /* the number of pipes using HDCP signalling out of this port */
1847 unsigned int num_hdcp_streams;
1848 /* port HDCP auth status */
1849 bool hdcp_auth_status;
1850 /* HDCP port data need to pass to security f/w */
1851 struct hdcp_port_data hdcp_port_data;
1852 /* Whether the MST topology supports HDCP Type 1 Content */
1853 bool hdcp_mst_type1_capable;
1854
1855 void (*write_infoframe)(struct intel_encoder *encoder,
1856 const struct intel_crtc_state *crtc_state,
1857 unsigned int type,
1858 const void *frame, ssize_t len);
1859 void (*read_infoframe)(struct intel_encoder *encoder,
1860 const struct intel_crtc_state *crtc_state,
1861 unsigned int type,
1862 void *frame, ssize_t len);
1863 void (*set_infoframes)(struct intel_encoder *encoder,
1864 bool enable,
1865 const struct intel_crtc_state *crtc_state,
1866 const struct drm_connector_state *conn_state);
1867 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1868 const struct intel_crtc_state *pipe_config);
1869 bool (*connected)(struct intel_encoder *encoder);
1870 };
1871
1872 struct intel_dp_mst_encoder {
1873 struct intel_encoder base;
1874 enum pipe pipe;
1875 struct intel_digital_port *primary;
1876 struct intel_connector *connector;
1877 };
1878
1879 static inline struct intel_encoder *
intel_attached_encoder(struct intel_connector * connector)1880 intel_attached_encoder(struct intel_connector *connector)
1881 {
1882 return connector->encoder;
1883 }
1884
intel_encoder_is_dig_port(struct intel_encoder * encoder)1885 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1886 {
1887 switch (encoder->type) {
1888 case INTEL_OUTPUT_DDI:
1889 case INTEL_OUTPUT_DP:
1890 case INTEL_OUTPUT_EDP:
1891 case INTEL_OUTPUT_HDMI:
1892 return true;
1893 default:
1894 return false;
1895 }
1896 }
1897
intel_encoder_is_mst(struct intel_encoder * encoder)1898 static inline bool intel_encoder_is_mst(struct intel_encoder *encoder)
1899 {
1900 return encoder->type == INTEL_OUTPUT_DP_MST;
1901 }
1902
1903 static inline struct intel_dp_mst_encoder *
enc_to_mst(struct intel_encoder * encoder)1904 enc_to_mst(struct intel_encoder *encoder)
1905 {
1906 return container_of(&encoder->base, struct intel_dp_mst_encoder,
1907 base.base);
1908 }
1909
1910 static inline struct intel_digital_port *
enc_to_dig_port(struct intel_encoder * encoder)1911 enc_to_dig_port(struct intel_encoder *encoder)
1912 {
1913 struct intel_encoder *intel_encoder = encoder;
1914
1915 if (intel_encoder_is_dig_port(intel_encoder))
1916 return container_of(&encoder->base, struct intel_digital_port,
1917 base.base);
1918 else if (intel_encoder_is_mst(intel_encoder))
1919 return enc_to_mst(encoder)->primary;
1920 else
1921 return NULL;
1922 }
1923
1924 static inline struct intel_digital_port *
intel_attached_dig_port(struct intel_connector * connector)1925 intel_attached_dig_port(struct intel_connector *connector)
1926 {
1927 return enc_to_dig_port(intel_attached_encoder(connector));
1928 }
1929
1930 static inline struct intel_hdmi *
enc_to_intel_hdmi(struct intel_encoder * encoder)1931 enc_to_intel_hdmi(struct intel_encoder *encoder)
1932 {
1933 return &enc_to_dig_port(encoder)->hdmi;
1934 }
1935
1936 static inline struct intel_hdmi *
intel_attached_hdmi(struct intel_connector * connector)1937 intel_attached_hdmi(struct intel_connector *connector)
1938 {
1939 return enc_to_intel_hdmi(intel_attached_encoder(connector));
1940 }
1941
enc_to_intel_dp(struct intel_encoder * encoder)1942 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)
1943 {
1944 return &enc_to_dig_port(encoder)->dp;
1945 }
1946
intel_attached_dp(struct intel_connector * connector)1947 static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector)
1948 {
1949 return enc_to_intel_dp(intel_attached_encoder(connector));
1950 }
1951
intel_encoder_is_dp(struct intel_encoder * encoder)1952 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1953 {
1954 switch (encoder->type) {
1955 case INTEL_OUTPUT_DP:
1956 case INTEL_OUTPUT_EDP:
1957 return true;
1958 case INTEL_OUTPUT_DDI:
1959 /* Skip pure HDMI/DVI DDI encoders */
1960 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg);
1961 default:
1962 return false;
1963 }
1964 }
1965
1966 static inline struct intel_lspcon *
enc_to_intel_lspcon(struct intel_encoder * encoder)1967 enc_to_intel_lspcon(struct intel_encoder *encoder)
1968 {
1969 return &enc_to_dig_port(encoder)->lspcon;
1970 }
1971
1972 static inline struct intel_digital_port *
dp_to_dig_port(struct intel_dp * intel_dp)1973 dp_to_dig_port(struct intel_dp *intel_dp)
1974 {
1975 return container_of(intel_dp, struct intel_digital_port, dp);
1976 }
1977
1978 static inline struct intel_lspcon *
dp_to_lspcon(struct intel_dp * intel_dp)1979 dp_to_lspcon(struct intel_dp *intel_dp)
1980 {
1981 return &dp_to_dig_port(intel_dp)->lspcon;
1982 }
1983
1984 #define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)
1985
1986 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
1987 (intel_dp)->psr.source_support)
1988
intel_encoder_can_psr(struct intel_encoder * encoder)1989 static inline bool intel_encoder_can_psr(struct intel_encoder *encoder)
1990 {
1991 if (!intel_encoder_is_dp(encoder))
1992 return false;
1993
1994 return CAN_PSR(enc_to_intel_dp(encoder));
1995 }
1996
1997 static inline struct intel_digital_port *
hdmi_to_dig_port(struct intel_hdmi * intel_hdmi)1998 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1999 {
2000 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
2001 }
2002
2003 static inline struct intel_plane_state *
intel_atomic_get_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)2004 intel_atomic_get_plane_state(struct intel_atomic_state *state,
2005 struct intel_plane *plane)
2006 {
2007 struct drm_plane_state *ret =
2008 drm_atomic_get_plane_state(&state->base, &plane->base);
2009
2010 if (IS_ERR(ret))
2011 return ERR_CAST(ret);
2012
2013 return to_intel_plane_state(ret);
2014 }
2015
2016 static inline struct intel_plane_state *
intel_atomic_get_old_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)2017 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
2018 struct intel_plane *plane)
2019 {
2020 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
2021 &plane->base));
2022 }
2023
2024 static inline struct intel_plane_state *
intel_atomic_get_new_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)2025 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
2026 struct intel_plane *plane)
2027 {
2028 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
2029 &plane->base));
2030 }
2031
2032 static inline struct intel_crtc_state *
intel_atomic_get_old_crtc_state(struct intel_atomic_state * state,struct intel_crtc * crtc)2033 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
2034 struct intel_crtc *crtc)
2035 {
2036 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
2037 &crtc->base));
2038 }
2039
2040 static inline struct intel_crtc_state *
intel_atomic_get_new_crtc_state(struct intel_atomic_state * state,struct intel_crtc * crtc)2041 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
2042 struct intel_crtc *crtc)
2043 {
2044 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
2045 &crtc->base));
2046 }
2047
2048 static inline struct intel_digital_connector_state *
intel_atomic_get_new_connector_state(struct intel_atomic_state * state,struct intel_connector * connector)2049 intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
2050 struct intel_connector *connector)
2051 {
2052 return to_intel_digital_connector_state(
2053 drm_atomic_get_new_connector_state(&state->base,
2054 &connector->base));
2055 }
2056
2057 static inline struct intel_digital_connector_state *
intel_atomic_get_old_connector_state(struct intel_atomic_state * state,struct intel_connector * connector)2058 intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
2059 struct intel_connector *connector)
2060 {
2061 return to_intel_digital_connector_state(
2062 drm_atomic_get_old_connector_state(&state->base,
2063 &connector->base));
2064 }
2065
2066 /* intel_display.c */
2067 static inline bool
intel_crtc_has_type(const struct intel_crtc_state * crtc_state,enum intel_output_type type)2068 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
2069 enum intel_output_type type)
2070 {
2071 return crtc_state->output_types & BIT(type);
2072 }
2073
2074 static inline bool
intel_crtc_has_dp_encoder(const struct intel_crtc_state * crtc_state)2075 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
2076 {
2077 return crtc_state->output_types &
2078 (BIT(INTEL_OUTPUT_DP) |
2079 BIT(INTEL_OUTPUT_DP_MST) |
2080 BIT(INTEL_OUTPUT_EDP));
2081 }
2082
2083 static inline bool
intel_crtc_needs_modeset(const struct intel_crtc_state * crtc_state)2084 intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state)
2085 {
2086 return drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
2087 }
2088
2089 static inline bool
intel_crtc_needs_fastset(const struct intel_crtc_state * crtc_state)2090 intel_crtc_needs_fastset(const struct intel_crtc_state *crtc_state)
2091 {
2092 return crtc_state->update_pipe;
2093 }
2094
2095 static inline bool
intel_crtc_needs_color_update(const struct intel_crtc_state * crtc_state)2096 intel_crtc_needs_color_update(const struct intel_crtc_state *crtc_state)
2097 {
2098 return crtc_state->uapi.color_mgmt_changed ||
2099 intel_crtc_needs_fastset(crtc_state) ||
2100 intel_crtc_needs_modeset(crtc_state);
2101 }
2102
intel_plane_ggtt_offset(const struct intel_plane_state * plane_state)2103 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state)
2104 {
2105 return i915_ggtt_offset(plane_state->ggtt_vma);
2106 }
2107
2108 static inline struct intel_frontbuffer *
to_intel_frontbuffer(struct drm_framebuffer * fb)2109 to_intel_frontbuffer(struct drm_framebuffer *fb)
2110 {
2111 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
2112 }
2113
2114 #endif /* __INTEL_DISPLAY_TYPES_H__ */
2115