1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Synopsys DesignWare PCIe host controller driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * https://www.samsung.com
7 *
8 * Author: Jingoo Han <jg1.han@samsung.com>
9 */
10
11 #include <linux/align.h>
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dma/edma.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/ioport.h>
18 #include <linux/of.h>
19 #include <linux/platform_device.h>
20 #include <linux/sizes.h>
21 #include <linux/types.h>
22
23 #include "../../pci.h"
24 #include "pcie-designware.h"
25
26 static const char * const dw_pcie_app_clks[DW_PCIE_NUM_APP_CLKS] = {
27 [DW_PCIE_DBI_CLK] = "dbi",
28 [DW_PCIE_MSTR_CLK] = "mstr",
29 [DW_PCIE_SLV_CLK] = "slv",
30 };
31
32 static const char * const dw_pcie_core_clks[DW_PCIE_NUM_CORE_CLKS] = {
33 [DW_PCIE_PIPE_CLK] = "pipe",
34 [DW_PCIE_CORE_CLK] = "core",
35 [DW_PCIE_AUX_CLK] = "aux",
36 [DW_PCIE_REF_CLK] = "ref",
37 };
38
39 static const char * const dw_pcie_app_rsts[DW_PCIE_NUM_APP_RSTS] = {
40 [DW_PCIE_DBI_RST] = "dbi",
41 [DW_PCIE_MSTR_RST] = "mstr",
42 [DW_PCIE_SLV_RST] = "slv",
43 };
44
45 static const char * const dw_pcie_core_rsts[DW_PCIE_NUM_CORE_RSTS] = {
46 [DW_PCIE_NON_STICKY_RST] = "non-sticky",
47 [DW_PCIE_STICKY_RST] = "sticky",
48 [DW_PCIE_CORE_RST] = "core",
49 [DW_PCIE_PIPE_RST] = "pipe",
50 [DW_PCIE_PHY_RST] = "phy",
51 [DW_PCIE_HOT_RST] = "hot",
52 [DW_PCIE_PWR_RST] = "pwr",
53 };
54
dw_pcie_get_clocks(struct dw_pcie * pci)55 static int dw_pcie_get_clocks(struct dw_pcie *pci)
56 {
57 int i, ret;
58
59 for (i = 0; i < DW_PCIE_NUM_APP_CLKS; i++)
60 pci->app_clks[i].id = dw_pcie_app_clks[i];
61
62 for (i = 0; i < DW_PCIE_NUM_CORE_CLKS; i++)
63 pci->core_clks[i].id = dw_pcie_core_clks[i];
64
65 ret = devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_APP_CLKS,
66 pci->app_clks);
67 if (ret)
68 return ret;
69
70 return devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_CORE_CLKS,
71 pci->core_clks);
72 }
73
dw_pcie_get_resets(struct dw_pcie * pci)74 static int dw_pcie_get_resets(struct dw_pcie *pci)
75 {
76 int i, ret;
77
78 for (i = 0; i < DW_PCIE_NUM_APP_RSTS; i++)
79 pci->app_rsts[i].id = dw_pcie_app_rsts[i];
80
81 for (i = 0; i < DW_PCIE_NUM_CORE_RSTS; i++)
82 pci->core_rsts[i].id = dw_pcie_core_rsts[i];
83
84 ret = devm_reset_control_bulk_get_optional_shared(pci->dev,
85 DW_PCIE_NUM_APP_RSTS,
86 pci->app_rsts);
87 if (ret)
88 return ret;
89
90 ret = devm_reset_control_bulk_get_optional_exclusive(pci->dev,
91 DW_PCIE_NUM_CORE_RSTS,
92 pci->core_rsts);
93 if (ret)
94 return ret;
95
96 pci->pe_rst = devm_gpiod_get_optional(pci->dev, "reset", GPIOD_OUT_HIGH);
97 if (IS_ERR(pci->pe_rst))
98 return PTR_ERR(pci->pe_rst);
99
100 return 0;
101 }
102
dw_pcie_get_resources(struct dw_pcie * pci)103 int dw_pcie_get_resources(struct dw_pcie *pci)
104 {
105 struct platform_device *pdev = to_platform_device(pci->dev);
106 struct device_node *np = dev_of_node(pci->dev);
107 struct resource *res;
108 int ret;
109
110 if (!pci->dbi_base) {
111 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
112 pci->dbi_base = devm_pci_remap_cfg_resource(pci->dev, res);
113 if (IS_ERR(pci->dbi_base))
114 return PTR_ERR(pci->dbi_base);
115 }
116
117 /* DBI2 is mainly useful for the endpoint controller */
118 if (!pci->dbi_base2) {
119 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2");
120 if (res) {
121 pci->dbi_base2 = devm_pci_remap_cfg_resource(pci->dev, res);
122 if (IS_ERR(pci->dbi_base2))
123 return PTR_ERR(pci->dbi_base2);
124 } else {
125 pci->dbi_base2 = pci->dbi_base + SZ_4K;
126 }
127 }
128
129 /* For non-unrolled iATU/eDMA platforms this range will be ignored */
130 if (!pci->atu_base) {
131 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu");
132 if (res) {
133 pci->atu_size = resource_size(res);
134 pci->atu_base = devm_ioremap_resource(pci->dev, res);
135 if (IS_ERR(pci->atu_base))
136 return PTR_ERR(pci->atu_base);
137 } else {
138 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
139 }
140 }
141
142 /* Set a default value suitable for at most 8 in and 8 out windows */
143 if (!pci->atu_size)
144 pci->atu_size = SZ_4K;
145
146 /* eDMA region can be mapped to a custom base address */
147 if (!pci->edma.reg_base) {
148 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
149 if (res) {
150 pci->edma.reg_base = devm_ioremap_resource(pci->dev, res);
151 if (IS_ERR(pci->edma.reg_base))
152 return PTR_ERR(pci->edma.reg_base);
153 } else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) {
154 pci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET;
155 }
156 }
157
158 /* LLDD is supposed to manually switch the clocks and resets state */
159 if (dw_pcie_cap_is(pci, REQ_RES)) {
160 ret = dw_pcie_get_clocks(pci);
161 if (ret)
162 return ret;
163
164 ret = dw_pcie_get_resets(pci);
165 if (ret)
166 return ret;
167 }
168
169 if (pci->link_gen < 1)
170 pci->link_gen = of_pci_get_max_link_speed(np);
171
172 of_property_read_u32(np, "num-lanes", &pci->num_lanes);
173
174 if (of_property_read_bool(np, "snps,enable-cdm-check"))
175 dw_pcie_cap_set(pci, CDM_CHECK);
176
177 return 0;
178 }
179
dw_pcie_version_detect(struct dw_pcie * pci)180 void dw_pcie_version_detect(struct dw_pcie *pci)
181 {
182 u32 ver;
183
184 /* The content of the CSR is zero on DWC PCIe older than v4.70a */
185 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_NUMBER);
186 if (!ver)
187 return;
188
189 if (pci->version && pci->version != ver)
190 dev_warn(pci->dev, "Versions don't match (%08x != %08x)\n",
191 pci->version, ver);
192 else
193 pci->version = ver;
194
195 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_TYPE);
196
197 if (pci->type && pci->type != ver)
198 dev_warn(pci->dev, "Types don't match (%08x != %08x)\n",
199 pci->type, ver);
200 else
201 pci->type = ver;
202 }
203
204 /*
205 * These interfaces resemble the pci_find_*capability() interfaces, but these
206 * are for configuring host controllers, which are bridges *to* PCI devices but
207 * are not PCI devices themselves.
208 */
__dw_pcie_find_next_cap(struct dw_pcie * pci,u8 cap_ptr,u8 cap)209 static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
210 u8 cap)
211 {
212 u8 cap_id, next_cap_ptr;
213 u16 reg;
214
215 if (!cap_ptr)
216 return 0;
217
218 reg = dw_pcie_readw_dbi(pci, cap_ptr);
219 cap_id = (reg & 0x00ff);
220
221 if (cap_id > PCI_CAP_ID_MAX)
222 return 0;
223
224 if (cap_id == cap)
225 return cap_ptr;
226
227 next_cap_ptr = (reg & 0xff00) >> 8;
228 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
229 }
230
dw_pcie_find_capability(struct dw_pcie * pci,u8 cap)231 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
232 {
233 u8 next_cap_ptr;
234 u16 reg;
235
236 reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
237 next_cap_ptr = (reg & 0x00ff);
238
239 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
240 }
241 EXPORT_SYMBOL_GPL(dw_pcie_find_capability);
242
dw_pcie_find_next_ext_capability(struct dw_pcie * pci,u16 start,u8 cap)243 static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start,
244 u8 cap)
245 {
246 u32 header;
247 int ttl;
248 int pos = PCI_CFG_SPACE_SIZE;
249
250 /* minimum 8 bytes per capability */
251 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
252
253 if (start)
254 pos = start;
255
256 header = dw_pcie_readl_dbi(pci, pos);
257 /*
258 * If we have no capabilities, this is indicated by cap ID,
259 * cap version and next pointer all being 0.
260 */
261 if (header == 0)
262 return 0;
263
264 while (ttl-- > 0) {
265 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
266 return pos;
267
268 pos = PCI_EXT_CAP_NEXT(header);
269 if (pos < PCI_CFG_SPACE_SIZE)
270 break;
271
272 header = dw_pcie_readl_dbi(pci, pos);
273 }
274
275 return 0;
276 }
277
dw_pcie_find_ext_capability(struct dw_pcie * pci,u8 cap)278 u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap)
279 {
280 return dw_pcie_find_next_ext_capability(pci, 0, cap);
281 }
282 EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
283
dw_pcie_read(void __iomem * addr,int size,u32 * val)284 int dw_pcie_read(void __iomem *addr, int size, u32 *val)
285 {
286 if (!IS_ALIGNED((uintptr_t)addr, size)) {
287 *val = 0;
288 return PCIBIOS_BAD_REGISTER_NUMBER;
289 }
290
291 if (size == 4) {
292 *val = readl(addr);
293 } else if (size == 2) {
294 *val = readw(addr);
295 } else if (size == 1) {
296 *val = readb(addr);
297 } else {
298 *val = 0;
299 return PCIBIOS_BAD_REGISTER_NUMBER;
300 }
301
302 return PCIBIOS_SUCCESSFUL;
303 }
304 EXPORT_SYMBOL_GPL(dw_pcie_read);
305
dw_pcie_write(void __iomem * addr,int size,u32 val)306 int dw_pcie_write(void __iomem *addr, int size, u32 val)
307 {
308 if (!IS_ALIGNED((uintptr_t)addr, size))
309 return PCIBIOS_BAD_REGISTER_NUMBER;
310
311 if (size == 4)
312 writel(val, addr);
313 else if (size == 2)
314 writew(val, addr);
315 else if (size == 1)
316 writeb(val, addr);
317 else
318 return PCIBIOS_BAD_REGISTER_NUMBER;
319
320 return PCIBIOS_SUCCESSFUL;
321 }
322 EXPORT_SYMBOL_GPL(dw_pcie_write);
323
dw_pcie_read_dbi(struct dw_pcie * pci,u32 reg,size_t size)324 u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size)
325 {
326 int ret;
327 u32 val;
328
329 if (pci->ops && pci->ops->read_dbi)
330 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size);
331
332 ret = dw_pcie_read(pci->dbi_base + reg, size, &val);
333 if (ret)
334 dev_err(pci->dev, "Read DBI address failed\n");
335
336 return val;
337 }
338 EXPORT_SYMBOL_GPL(dw_pcie_read_dbi);
339
dw_pcie_write_dbi(struct dw_pcie * pci,u32 reg,size_t size,u32 val)340 void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
341 {
342 int ret;
343
344 if (pci->ops && pci->ops->write_dbi) {
345 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val);
346 return;
347 }
348
349 ret = dw_pcie_write(pci->dbi_base + reg, size, val);
350 if (ret)
351 dev_err(pci->dev, "Write DBI address failed\n");
352 }
353 EXPORT_SYMBOL_GPL(dw_pcie_write_dbi);
354
dw_pcie_write_dbi2(struct dw_pcie * pci,u32 reg,size_t size,u32 val)355 void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
356 {
357 int ret;
358
359 if (pci->ops && pci->ops->write_dbi2) {
360 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val);
361 return;
362 }
363
364 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val);
365 if (ret)
366 dev_err(pci->dev, "write DBI address failed\n");
367 }
368
dw_pcie_select_atu(struct dw_pcie * pci,u32 dir,u32 index)369 static inline void __iomem *dw_pcie_select_atu(struct dw_pcie *pci, u32 dir,
370 u32 index)
371 {
372 if (dw_pcie_cap_is(pci, IATU_UNROLL))
373 return pci->atu_base + PCIE_ATU_UNROLL_BASE(dir, index);
374
375 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, dir | index);
376 return pci->atu_base;
377 }
378
dw_pcie_readl_atu(struct dw_pcie * pci,u32 dir,u32 index,u32 reg)379 static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 dir, u32 index, u32 reg)
380 {
381 void __iomem *base;
382 int ret;
383 u32 val;
384
385 base = dw_pcie_select_atu(pci, dir, index);
386
387 if (pci->ops && pci->ops->read_dbi)
388 return pci->ops->read_dbi(pci, base, reg, 4);
389
390 ret = dw_pcie_read(base + reg, 4, &val);
391 if (ret)
392 dev_err(pci->dev, "Read ATU address failed\n");
393
394 return val;
395 }
396
dw_pcie_writel_atu(struct dw_pcie * pci,u32 dir,u32 index,u32 reg,u32 val)397 static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 dir, u32 index,
398 u32 reg, u32 val)
399 {
400 void __iomem *base;
401 int ret;
402
403 base = dw_pcie_select_atu(pci, dir, index);
404
405 if (pci->ops && pci->ops->write_dbi) {
406 pci->ops->write_dbi(pci, base, reg, 4, val);
407 return;
408 }
409
410 ret = dw_pcie_write(base + reg, 4, val);
411 if (ret)
412 dev_err(pci->dev, "Write ATU address failed\n");
413 }
414
dw_pcie_readl_atu_ob(struct dw_pcie * pci,u32 index,u32 reg)415 static inline u32 dw_pcie_readl_atu_ob(struct dw_pcie *pci, u32 index, u32 reg)
416 {
417 return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg);
418 }
419
dw_pcie_writel_atu_ob(struct dw_pcie * pci,u32 index,u32 reg,u32 val)420 static inline void dw_pcie_writel_atu_ob(struct dw_pcie *pci, u32 index, u32 reg,
421 u32 val)
422 {
423 dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg, val);
424 }
425
dw_pcie_enable_ecrc(u32 val)426 static inline u32 dw_pcie_enable_ecrc(u32 val)
427 {
428 /*
429 * DesignWare core version 4.90A has a design issue where the 'TD'
430 * bit in the Control register-1 of the ATU outbound region acts
431 * like an override for the ECRC setting, i.e., the presence of TLP
432 * Digest (ECRC) in the outgoing TLPs is solely determined by this
433 * bit. This is contrary to the PCIe spec which says that the
434 * enablement of the ECRC is solely determined by the AER
435 * registers.
436 *
437 * Because of this, even when the ECRC is enabled through AER
438 * registers, the transactions going through ATU won't have TLP
439 * Digest as there is no way the PCI core AER code could program
440 * the TD bit which is specific to the DesignWare core.
441 *
442 * The best way to handle this scenario is to program the TD bit
443 * always. It affects only the traffic from root port to downstream
444 * devices.
445 *
446 * At this point,
447 * When ECRC is enabled in AER registers, everything works normally
448 * When ECRC is NOT enabled in AER registers, then,
449 * on Root Port:- TLP Digest (DWord size) gets appended to each packet
450 * even through it is not required. Since downstream
451 * TLPs are mostly for configuration accesses and BAR
452 * accesses, they are not in critical path and won't
453 * have much negative effect on the performance.
454 * on End Point:- TLP Digest is received for some/all the packets coming
455 * from the root port. TLP Digest is ignored because,
456 * as per the PCIe Spec r5.0 v1.0 section 2.2.3
457 * "TLP Digest Rules", when an endpoint receives TLP
458 * Digest when its ECRC check functionality is disabled
459 * in AER registers, received TLP Digest is just ignored.
460 * Since there is no issue or error reported either side, best way to
461 * handle the scenario is to program TD bit by default.
462 */
463
464 return val | PCIE_ATU_TD;
465 }
466
__dw_pcie_prog_outbound_atu(struct dw_pcie * pci,u8 func_no,int index,int type,u64 cpu_addr,u64 pci_addr,u64 size)467 static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
468 int index, int type, u64 cpu_addr,
469 u64 pci_addr, u64 size)
470 {
471 u32 retries, val;
472 u64 limit_addr;
473
474 if (pci->ops && pci->ops->cpu_addr_fixup)
475 cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
476
477 limit_addr = cpu_addr + size - 1;
478
479 if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) ||
480 !IS_ALIGNED(cpu_addr, pci->region_align) ||
481 !IS_ALIGNED(pci_addr, pci->region_align) || !size) {
482 return -EINVAL;
483 }
484
485 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_BASE,
486 lower_32_bits(cpu_addr));
487 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_BASE,
488 upper_32_bits(cpu_addr));
489
490 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LIMIT,
491 lower_32_bits(limit_addr));
492 if (dw_pcie_ver_is_ge(pci, 460A))
493 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_LIMIT,
494 upper_32_bits(limit_addr));
495
496 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_TARGET,
497 lower_32_bits(pci_addr));
498 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_TARGET,
499 upper_32_bits(pci_addr));
500
501 val = type | PCIE_ATU_FUNC_NUM(func_no);
502 if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
503 dw_pcie_ver_is_ge(pci, 460A))
504 val |= PCIE_ATU_INCREASE_REGION_SIZE;
505 if (dw_pcie_ver_is(pci, 490A))
506 val = dw_pcie_enable_ecrc(val);
507 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL1, val);
508
509 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
510
511 /*
512 * Make sure ATU enable takes effect before any subsequent config
513 * and I/O accesses.
514 */
515 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
516 val = dw_pcie_readl_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2);
517 if (val & PCIE_ATU_ENABLE)
518 return 0;
519
520 mdelay(LINK_WAIT_IATU);
521 }
522
523 dev_err(pci->dev, "Outbound iATU is not being enabled\n");
524
525 return -ETIMEDOUT;
526 }
527
dw_pcie_prog_outbound_atu(struct dw_pcie * pci,int index,int type,u64 cpu_addr,u64 pci_addr,u64 size)528 int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
529 u64 cpu_addr, u64 pci_addr, u64 size)
530 {
531 return __dw_pcie_prog_outbound_atu(pci, 0, index, type,
532 cpu_addr, pci_addr, size);
533 }
534
dw_pcie_prog_ep_outbound_atu(struct dw_pcie * pci,u8 func_no,int index,int type,u64 cpu_addr,u64 pci_addr,u64 size)535 int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
536 int type, u64 cpu_addr, u64 pci_addr,
537 u64 size)
538 {
539 return __dw_pcie_prog_outbound_atu(pci, func_no, index, type,
540 cpu_addr, pci_addr, size);
541 }
542
dw_pcie_readl_atu_ib(struct dw_pcie * pci,u32 index,u32 reg)543 static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg)
544 {
545 return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg);
546 }
547
dw_pcie_writel_atu_ib(struct dw_pcie * pci,u32 index,u32 reg,u32 val)548 static inline void dw_pcie_writel_atu_ib(struct dw_pcie *pci, u32 index, u32 reg,
549 u32 val)
550 {
551 dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg, val);
552 }
553
dw_pcie_prog_inbound_atu(struct dw_pcie * pci,int index,int type,u64 cpu_addr,u64 pci_addr,u64 size)554 int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
555 u64 cpu_addr, u64 pci_addr, u64 size)
556 {
557 u64 limit_addr = pci_addr + size - 1;
558 u32 retries, val;
559
560 if ((limit_addr & ~pci->region_limit) != (pci_addr & ~pci->region_limit) ||
561 !IS_ALIGNED(cpu_addr, pci->region_align) ||
562 !IS_ALIGNED(pci_addr, pci->region_align) || !size) {
563 return -EINVAL;
564 }
565
566 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_BASE,
567 lower_32_bits(pci_addr));
568 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_BASE,
569 upper_32_bits(pci_addr));
570
571 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LIMIT,
572 lower_32_bits(limit_addr));
573 if (dw_pcie_ver_is_ge(pci, 460A))
574 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_LIMIT,
575 upper_32_bits(limit_addr));
576
577 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET,
578 lower_32_bits(cpu_addr));
579 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET,
580 upper_32_bits(cpu_addr));
581
582 val = type;
583 if (upper_32_bits(limit_addr) > upper_32_bits(pci_addr) &&
584 dw_pcie_ver_is_ge(pci, 460A))
585 val |= PCIE_ATU_INCREASE_REGION_SIZE;
586 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, val);
587 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
588
589 /*
590 * Make sure ATU enable takes effect before any subsequent config
591 * and I/O accesses.
592 */
593 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
594 val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2);
595 if (val & PCIE_ATU_ENABLE)
596 return 0;
597
598 mdelay(LINK_WAIT_IATU);
599 }
600
601 dev_err(pci->dev, "Inbound iATU is not being enabled\n");
602
603 return -ETIMEDOUT;
604 }
605
dw_pcie_prog_ep_inbound_atu(struct dw_pcie * pci,u8 func_no,int index,int type,u64 cpu_addr,u8 bar)606 int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
607 int type, u64 cpu_addr, u8 bar)
608 {
609 u32 retries, val;
610
611 if (!IS_ALIGNED(cpu_addr, pci->region_align))
612 return -EINVAL;
613
614 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET,
615 lower_32_bits(cpu_addr));
616 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET,
617 upper_32_bits(cpu_addr));
618
619 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, type |
620 PCIE_ATU_FUNC_NUM(func_no));
621 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2,
622 PCIE_ATU_ENABLE | PCIE_ATU_FUNC_NUM_MATCH_EN |
623 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
624
625 /*
626 * Make sure ATU enable takes effect before any subsequent config
627 * and I/O accesses.
628 */
629 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
630 val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2);
631 if (val & PCIE_ATU_ENABLE)
632 return 0;
633
634 mdelay(LINK_WAIT_IATU);
635 }
636
637 dev_err(pci->dev, "Inbound iATU is not being enabled\n");
638
639 return -ETIMEDOUT;
640 }
641
dw_pcie_disable_atu(struct dw_pcie * pci,u32 dir,int index)642 void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index)
643 {
644 dw_pcie_writel_atu(pci, dir, index, PCIE_ATU_REGION_CTRL2, 0);
645 }
646
dw_pcie_wait_for_link(struct dw_pcie * pci)647 int dw_pcie_wait_for_link(struct dw_pcie *pci)
648 {
649 u32 offset, val;
650 int retries;
651
652 /* Check if the link is up or not */
653 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
654 if (dw_pcie_link_up(pci))
655 break;
656
657 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
658 }
659
660 if (retries >= LINK_WAIT_MAX_RETRIES) {
661 dev_info(pci->dev, "Phy link never came up\n");
662 return -ETIMEDOUT;
663 }
664
665 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
666 val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
667
668 dev_info(pci->dev, "PCIe Gen.%u x%u link up\n",
669 FIELD_GET(PCI_EXP_LNKSTA_CLS, val),
670 FIELD_GET(PCI_EXP_LNKSTA_NLW, val));
671
672 return 0;
673 }
674 EXPORT_SYMBOL_GPL(dw_pcie_wait_for_link);
675
dw_pcie_link_up(struct dw_pcie * pci)676 int dw_pcie_link_up(struct dw_pcie *pci)
677 {
678 u32 val;
679
680 if (pci->ops && pci->ops->link_up)
681 return pci->ops->link_up(pci);
682
683 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1);
684 return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
685 (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
686 }
687 EXPORT_SYMBOL_GPL(dw_pcie_link_up);
688
dw_pcie_upconfig_setup(struct dw_pcie * pci)689 void dw_pcie_upconfig_setup(struct dw_pcie *pci)
690 {
691 u32 val;
692
693 val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL);
694 val |= PORT_MLTI_UPCFG_SUPPORT;
695 dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val);
696 }
697 EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup);
698
dw_pcie_link_set_max_speed(struct dw_pcie * pci,u32 link_gen)699 static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
700 {
701 u32 cap, ctrl2, link_speed;
702 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
703
704 cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
705 ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
706 ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;
707
708 switch (pcie_link_speed[link_gen]) {
709 case PCIE_SPEED_2_5GT:
710 link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT;
711 break;
712 case PCIE_SPEED_5_0GT:
713 link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT;
714 break;
715 case PCIE_SPEED_8_0GT:
716 link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT;
717 break;
718 case PCIE_SPEED_16_0GT:
719 link_speed = PCI_EXP_LNKCTL2_TLS_16_0GT;
720 break;
721 default:
722 /* Use hardware capability */
723 link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);
724 ctrl2 &= ~PCI_EXP_LNKCTL2_HASD;
725 break;
726 }
727
728 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed);
729
730 cap &= ~((u32)PCI_EXP_LNKCAP_SLS);
731 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed);
732
733 }
734
dw_pcie_link_set_max_link_width(struct dw_pcie * pci,u32 num_lanes)735 static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
736 {
737 u32 lnkcap, lwsc, plc;
738 u8 cap;
739
740 if (!num_lanes)
741 return;
742
743 /* Set the number of lanes */
744 plc = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
745 plc &= ~PORT_LINK_FAST_LINK_MODE;
746 plc &= ~PORT_LINK_MODE_MASK;
747
748 /* Set link width speed control register */
749 lwsc = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
750 lwsc &= ~PORT_LOGIC_LINK_WIDTH_MASK;
751 switch (num_lanes) {
752 case 1:
753 plc |= PORT_LINK_MODE_1_LANES;
754 lwsc |= PORT_LOGIC_LINK_WIDTH_1_LANES;
755 break;
756 case 2:
757 plc |= PORT_LINK_MODE_2_LANES;
758 lwsc |= PORT_LOGIC_LINK_WIDTH_2_LANES;
759 break;
760 case 4:
761 plc |= PORT_LINK_MODE_4_LANES;
762 lwsc |= PORT_LOGIC_LINK_WIDTH_4_LANES;
763 break;
764 case 8:
765 plc |= PORT_LINK_MODE_8_LANES;
766 lwsc |= PORT_LOGIC_LINK_WIDTH_8_LANES;
767 break;
768 default:
769 dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes);
770 return;
771 }
772 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
773 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
774
775 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
776 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
777 lnkcap &= ~PCI_EXP_LNKCAP_MLW;
778 lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes);
779 dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);
780 }
781
dw_pcie_iatu_detect(struct dw_pcie * pci)782 void dw_pcie_iatu_detect(struct dw_pcie *pci)
783 {
784 int max_region, ob, ib;
785 u32 val, min, dir;
786 u64 max;
787
788 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
789 if (val == 0xFFFFFFFF) {
790 dw_pcie_cap_set(pci, IATU_UNROLL);
791
792 max_region = min((int)pci->atu_size / 512, 256);
793 } else {
794 pci->atu_base = pci->dbi_base + PCIE_ATU_VIEWPORT_BASE;
795 pci->atu_size = PCIE_ATU_VIEWPORT_SIZE;
796
797 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, 0xFF);
798 max_region = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT) + 1;
799 }
800
801 for (ob = 0; ob < max_region; ob++) {
802 dw_pcie_writel_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET, 0x11110000);
803 val = dw_pcie_readl_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET);
804 if (val != 0x11110000)
805 break;
806 }
807
808 for (ib = 0; ib < max_region; ib++) {
809 dw_pcie_writel_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET, 0x11110000);
810 val = dw_pcie_readl_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET);
811 if (val != 0x11110000)
812 break;
813 }
814
815 if (ob) {
816 dir = PCIE_ATU_REGION_DIR_OB;
817 } else if (ib) {
818 dir = PCIE_ATU_REGION_DIR_IB;
819 } else {
820 dev_err(pci->dev, "No iATU regions found\n");
821 return;
822 }
823
824 dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_LIMIT, 0x0);
825 min = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_LIMIT);
826
827 if (dw_pcie_ver_is_ge(pci, 460A)) {
828 dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT, 0xFFFFFFFF);
829 max = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT);
830 } else {
831 max = 0;
832 }
833
834 pci->num_ob_windows = ob;
835 pci->num_ib_windows = ib;
836 pci->region_align = 1 << fls(min);
837 pci->region_limit = (max << 32) | (SZ_4G - 1);
838
839 dev_info(pci->dev, "iATU: unroll %s, %u ob, %u ib, align %uK, limit %lluG\n",
840 dw_pcie_cap_is(pci, IATU_UNROLL) ? "T" : "F",
841 pci->num_ob_windows, pci->num_ib_windows,
842 pci->region_align / SZ_1K, (pci->region_limit + 1) / SZ_1G);
843 }
844
dw_pcie_readl_dma(struct dw_pcie * pci,u32 reg)845 static u32 dw_pcie_readl_dma(struct dw_pcie *pci, u32 reg)
846 {
847 u32 val = 0;
848 int ret;
849
850 if (pci->ops && pci->ops->read_dbi)
851 return pci->ops->read_dbi(pci, pci->edma.reg_base, reg, 4);
852
853 ret = dw_pcie_read(pci->edma.reg_base + reg, 4, &val);
854 if (ret)
855 dev_err(pci->dev, "Read DMA address failed\n");
856
857 return val;
858 }
859
dw_pcie_edma_irq_vector(struct device * dev,unsigned int nr)860 static int dw_pcie_edma_irq_vector(struct device *dev, unsigned int nr)
861 {
862 struct platform_device *pdev = to_platform_device(dev);
863 char name[6];
864 int ret;
865
866 if (nr >= EDMA_MAX_WR_CH + EDMA_MAX_RD_CH)
867 return -EINVAL;
868
869 ret = platform_get_irq_byname_optional(pdev, "dma");
870 if (ret > 0)
871 return ret;
872
873 snprintf(name, sizeof(name), "dma%u", nr);
874
875 return platform_get_irq_byname_optional(pdev, name);
876 }
877
878 static struct dw_edma_plat_ops dw_pcie_edma_ops = {
879 .irq_vector = dw_pcie_edma_irq_vector,
880 };
881
dw_pcie_edma_find_chip(struct dw_pcie * pci)882 static int dw_pcie_edma_find_chip(struct dw_pcie *pci)
883 {
884 u32 val;
885
886 /*
887 * Indirect eDMA CSRs access has been completely removed since v5.40a
888 * thus no space is now reserved for the eDMA channels viewport and
889 * former DMA CTRL register is no longer fixed to FFs.
890 */
891 if (dw_pcie_ver_is_ge(pci, 540A))
892 val = 0xFFFFFFFF;
893 else
894 val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL);
895
896 if (val == 0xFFFFFFFF && pci->edma.reg_base) {
897 pci->edma.mf = EDMA_MF_EDMA_UNROLL;
898
899 val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL);
900 } else if (val != 0xFFFFFFFF) {
901 pci->edma.mf = EDMA_MF_EDMA_LEGACY;
902
903 pci->edma.reg_base = pci->dbi_base + PCIE_DMA_VIEWPORT_BASE;
904 } else {
905 return -ENODEV;
906 }
907
908 pci->edma.dev = pci->dev;
909
910 if (!pci->edma.ops)
911 pci->edma.ops = &dw_pcie_edma_ops;
912
913 pci->edma.flags |= DW_EDMA_CHIP_LOCAL;
914
915 pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val);
916 pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val);
917
918 /* Sanity check the channels count if the mapping was incorrect */
919 if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > EDMA_MAX_WR_CH ||
920 !pci->edma.ll_rd_cnt || pci->edma.ll_rd_cnt > EDMA_MAX_RD_CH)
921 return -EINVAL;
922
923 return 0;
924 }
925
dw_pcie_edma_irq_verify(struct dw_pcie * pci)926 static int dw_pcie_edma_irq_verify(struct dw_pcie *pci)
927 {
928 struct platform_device *pdev = to_platform_device(pci->dev);
929 u16 ch_cnt = pci->edma.ll_wr_cnt + pci->edma.ll_rd_cnt;
930 char name[6];
931 int ret;
932
933 if (pci->edma.nr_irqs == 1)
934 return 0;
935 else if (pci->edma.nr_irqs > 1)
936 return pci->edma.nr_irqs != ch_cnt ? -EINVAL : 0;
937
938 ret = platform_get_irq_byname_optional(pdev, "dma");
939 if (ret > 0) {
940 pci->edma.nr_irqs = 1;
941 return 0;
942 }
943
944 for (; pci->edma.nr_irqs < ch_cnt; pci->edma.nr_irqs++) {
945 snprintf(name, sizeof(name), "dma%d", pci->edma.nr_irqs);
946
947 ret = platform_get_irq_byname_optional(pdev, name);
948 if (ret <= 0)
949 return -EINVAL;
950 }
951
952 return 0;
953 }
954
dw_pcie_edma_ll_alloc(struct dw_pcie * pci)955 static int dw_pcie_edma_ll_alloc(struct dw_pcie *pci)
956 {
957 struct dw_edma_region *ll;
958 dma_addr_t paddr;
959 int i;
960
961 for (i = 0; i < pci->edma.ll_wr_cnt; i++) {
962 ll = &pci->edma.ll_region_wr[i];
963 ll->sz = DMA_LLP_MEM_SIZE;
964 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz,
965 &paddr, GFP_KERNEL);
966 if (!ll->vaddr.mem)
967 return -ENOMEM;
968
969 ll->paddr = paddr;
970 }
971
972 for (i = 0; i < pci->edma.ll_rd_cnt; i++) {
973 ll = &pci->edma.ll_region_rd[i];
974 ll->sz = DMA_LLP_MEM_SIZE;
975 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz,
976 &paddr, GFP_KERNEL);
977 if (!ll->vaddr.mem)
978 return -ENOMEM;
979
980 ll->paddr = paddr;
981 }
982
983 return 0;
984 }
985
dw_pcie_edma_detect(struct dw_pcie * pci)986 int dw_pcie_edma_detect(struct dw_pcie *pci)
987 {
988 int ret;
989
990 /* Don't fail if no eDMA was found (for the backward compatibility) */
991 ret = dw_pcie_edma_find_chip(pci);
992 if (ret)
993 return 0;
994
995 /* Don't fail on the IRQs verification (for the backward compatibility) */
996 ret = dw_pcie_edma_irq_verify(pci);
997 if (ret) {
998 dev_err(pci->dev, "Invalid eDMA IRQs found\n");
999 return 0;
1000 }
1001
1002 ret = dw_pcie_edma_ll_alloc(pci);
1003 if (ret) {
1004 dev_err(pci->dev, "Couldn't allocate LLP memory\n");
1005 return ret;
1006 }
1007
1008 /* Don't fail if the DW eDMA driver can't find the device */
1009 ret = dw_edma_probe(&pci->edma);
1010 if (ret && ret != -ENODEV) {
1011 dev_err(pci->dev, "Couldn't register eDMA device\n");
1012 return ret;
1013 }
1014
1015 dev_info(pci->dev, "eDMA: unroll %s, %hu wr, %hu rd\n",
1016 pci->edma.mf == EDMA_MF_EDMA_UNROLL ? "T" : "F",
1017 pci->edma.ll_wr_cnt, pci->edma.ll_rd_cnt);
1018
1019 return 0;
1020 }
1021
dw_pcie_edma_remove(struct dw_pcie * pci)1022 void dw_pcie_edma_remove(struct dw_pcie *pci)
1023 {
1024 dw_edma_remove(&pci->edma);
1025 }
1026
dw_pcie_setup(struct dw_pcie * pci)1027 void dw_pcie_setup(struct dw_pcie *pci)
1028 {
1029 u32 val;
1030
1031 if (pci->link_gen > 0)
1032 dw_pcie_link_set_max_speed(pci, pci->link_gen);
1033
1034 /* Configure Gen1 N_FTS */
1035 if (pci->n_fts[0]) {
1036 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
1037 val &= ~(PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK);
1038 val |= PORT_AFR_N_FTS(pci->n_fts[0]);
1039 val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]);
1040 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
1041 }
1042
1043 /* Configure Gen2+ N_FTS */
1044 if (pci->n_fts[1]) {
1045 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
1046 val &= ~PORT_LOGIC_N_FTS_MASK;
1047 val |= pci->n_fts[1];
1048 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
1049 }
1050
1051 if (dw_pcie_cap_is(pci, CDM_CHECK)) {
1052 val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
1053 val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |
1054 PCIE_PL_CHK_REG_CHK_REG_START;
1055 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
1056 }
1057
1058 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
1059 val &= ~PORT_LINK_FAST_LINK_MODE;
1060 val |= PORT_LINK_DLL_LINK_EN;
1061 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
1062
1063 dw_pcie_link_set_max_link_width(pci, pci->num_lanes);
1064 }
1065