1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Synopsys DesignWare PCIe host controller driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * https://www.samsung.com
7 *
8 * Author: Jingoo Han <jg1.han@samsung.com>
9 */
10
11 #include <linux/iopoll.h>
12 #include <linux/irqchip/chained_irq.h>
13 #include <linux/irqdomain.h>
14 #include <linux/msi.h>
15 #include <linux/of_address.h>
16 #include <linux/of_pci.h>
17 #include <linux/pci_regs.h>
18 #include <linux/platform_device.h>
19
20 #include "../../pci.h"
21 #include "pcie-designware.h"
22
23 static struct pci_ops dw_pcie_ops;
24 static struct pci_ops dw_child_pcie_ops;
25
dw_msi_ack_irq(struct irq_data * d)26 static void dw_msi_ack_irq(struct irq_data *d)
27 {
28 irq_chip_ack_parent(d);
29 }
30
dw_msi_mask_irq(struct irq_data * d)31 static void dw_msi_mask_irq(struct irq_data *d)
32 {
33 pci_msi_mask_irq(d);
34 irq_chip_mask_parent(d);
35 }
36
dw_msi_unmask_irq(struct irq_data * d)37 static void dw_msi_unmask_irq(struct irq_data *d)
38 {
39 pci_msi_unmask_irq(d);
40 irq_chip_unmask_parent(d);
41 }
42
43 static struct irq_chip dw_pcie_msi_irq_chip = {
44 .name = "PCI-MSI",
45 .irq_ack = dw_msi_ack_irq,
46 .irq_mask = dw_msi_mask_irq,
47 .irq_unmask = dw_msi_unmask_irq,
48 };
49
50 static struct msi_domain_info dw_pcie_msi_domain_info = {
51 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
52 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
53 .chip = &dw_pcie_msi_irq_chip,
54 };
55
56 /* MSI int handler */
dw_handle_msi_irq(struct dw_pcie_rp * pp)57 irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp)
58 {
59 int i, pos;
60 unsigned long val;
61 u32 status, num_ctrls;
62 irqreturn_t ret = IRQ_NONE;
63 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
64
65 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
66
67 for (i = 0; i < num_ctrls; i++) {
68 status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
69 (i * MSI_REG_CTRL_BLOCK_SIZE));
70 if (!status)
71 continue;
72
73 ret = IRQ_HANDLED;
74 val = status;
75 pos = 0;
76 while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL,
77 pos)) != MAX_MSI_IRQS_PER_CTRL) {
78 generic_handle_domain_irq(pp->irq_domain,
79 (i * MAX_MSI_IRQS_PER_CTRL) +
80 pos);
81 pos++;
82 }
83 }
84
85 return ret;
86 }
87 EXPORT_SYMBOL_GPL(dw_handle_msi_irq);
88
89 /* Chained MSI interrupt service routine */
dw_chained_msi_isr(struct irq_desc * desc)90 static void dw_chained_msi_isr(struct irq_desc *desc)
91 {
92 struct irq_chip *chip = irq_desc_get_chip(desc);
93 struct dw_pcie_rp *pp;
94
95 chained_irq_enter(chip, desc);
96
97 pp = irq_desc_get_handler_data(desc);
98 dw_handle_msi_irq(pp);
99
100 chained_irq_exit(chip, desc);
101 }
102
dw_pci_setup_msi_msg(struct irq_data * d,struct msi_msg * msg)103 static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
104 {
105 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
106 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
107 u64 msi_target;
108
109 msi_target = (u64)pp->msi_data;
110
111 msg->address_lo = lower_32_bits(msi_target);
112 msg->address_hi = upper_32_bits(msi_target);
113
114 msg->data = d->hwirq;
115
116 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
117 (int)d->hwirq, msg->address_hi, msg->address_lo);
118 }
119
dw_pci_msi_set_affinity(struct irq_data * d,const struct cpumask * mask,bool force)120 static int dw_pci_msi_set_affinity(struct irq_data *d,
121 const struct cpumask *mask, bool force)
122 {
123 return -EINVAL;
124 }
125
dw_pci_bottom_mask(struct irq_data * d)126 static void dw_pci_bottom_mask(struct irq_data *d)
127 {
128 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
129 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
130 unsigned int res, bit, ctrl;
131 unsigned long flags;
132
133 raw_spin_lock_irqsave(&pp->lock, flags);
134
135 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
136 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
137 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
138
139 pp->irq_mask[ctrl] |= BIT(bit);
140 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
141
142 raw_spin_unlock_irqrestore(&pp->lock, flags);
143 }
144
dw_pci_bottom_unmask(struct irq_data * d)145 static void dw_pci_bottom_unmask(struct irq_data *d)
146 {
147 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
148 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
149 unsigned int res, bit, ctrl;
150 unsigned long flags;
151
152 raw_spin_lock_irqsave(&pp->lock, flags);
153
154 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
155 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
156 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
157
158 pp->irq_mask[ctrl] &= ~BIT(bit);
159 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
160
161 raw_spin_unlock_irqrestore(&pp->lock, flags);
162 }
163
dw_pci_bottom_ack(struct irq_data * d)164 static void dw_pci_bottom_ack(struct irq_data *d)
165 {
166 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
167 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
168 unsigned int res, bit, ctrl;
169
170 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
171 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
172 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
173
174 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit));
175 }
176
177 static struct irq_chip dw_pci_msi_bottom_irq_chip = {
178 .name = "DWPCI-MSI",
179 .irq_ack = dw_pci_bottom_ack,
180 .irq_compose_msi_msg = dw_pci_setup_msi_msg,
181 .irq_set_affinity = dw_pci_msi_set_affinity,
182 .irq_mask = dw_pci_bottom_mask,
183 .irq_unmask = dw_pci_bottom_unmask,
184 };
185
dw_pcie_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * args)186 static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
187 unsigned int virq, unsigned int nr_irqs,
188 void *args)
189 {
190 struct dw_pcie_rp *pp = domain->host_data;
191 unsigned long flags;
192 u32 i;
193 int bit;
194
195 raw_spin_lock_irqsave(&pp->lock, flags);
196
197 bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors,
198 order_base_2(nr_irqs));
199
200 raw_spin_unlock_irqrestore(&pp->lock, flags);
201
202 if (bit < 0)
203 return -ENOSPC;
204
205 for (i = 0; i < nr_irqs; i++)
206 irq_domain_set_info(domain, virq + i, bit + i,
207 pp->msi_irq_chip,
208 pp, handle_edge_irq,
209 NULL, NULL);
210
211 return 0;
212 }
213
dw_pcie_irq_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)214 static void dw_pcie_irq_domain_free(struct irq_domain *domain,
215 unsigned int virq, unsigned int nr_irqs)
216 {
217 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
218 struct dw_pcie_rp *pp = domain->host_data;
219 unsigned long flags;
220
221 raw_spin_lock_irqsave(&pp->lock, flags);
222
223 bitmap_release_region(pp->msi_irq_in_use, d->hwirq,
224 order_base_2(nr_irqs));
225
226 raw_spin_unlock_irqrestore(&pp->lock, flags);
227 }
228
229 static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
230 .alloc = dw_pcie_irq_domain_alloc,
231 .free = dw_pcie_irq_domain_free,
232 };
233
dw_pcie_allocate_domains(struct dw_pcie_rp * pp)234 int dw_pcie_allocate_domains(struct dw_pcie_rp *pp)
235 {
236 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
237 struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
238
239 pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors,
240 &dw_pcie_msi_domain_ops, pp);
241 if (!pp->irq_domain) {
242 dev_err(pci->dev, "Failed to create IRQ domain\n");
243 return -ENOMEM;
244 }
245
246 irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS);
247
248 pp->msi_domain = pci_msi_create_irq_domain(fwnode,
249 &dw_pcie_msi_domain_info,
250 pp->irq_domain);
251 if (!pp->msi_domain) {
252 dev_err(pci->dev, "Failed to create MSI domain\n");
253 irq_domain_remove(pp->irq_domain);
254 return -ENOMEM;
255 }
256
257 return 0;
258 }
259
dw_pcie_free_msi(struct dw_pcie_rp * pp)260 static void dw_pcie_free_msi(struct dw_pcie_rp *pp)
261 {
262 u32 ctrl;
263
264 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {
265 if (pp->msi_irq[ctrl] > 0)
266 irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
267 NULL, NULL);
268 }
269
270 irq_domain_remove(pp->msi_domain);
271 irq_domain_remove(pp->irq_domain);
272 }
273
dw_pcie_msi_init(struct dw_pcie_rp * pp)274 static void dw_pcie_msi_init(struct dw_pcie_rp *pp)
275 {
276 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
277 u64 msi_target = (u64)pp->msi_data;
278
279 if (!pci_msi_enabled() || !pp->has_msi_ctrl)
280 return;
281
282 /* Program the msi_data */
283 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target));
284 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
285 }
286
dw_pcie_parse_split_msi_irq(struct dw_pcie_rp * pp)287 static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp)
288 {
289 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
290 struct device *dev = pci->dev;
291 struct platform_device *pdev = to_platform_device(dev);
292 u32 ctrl, max_vectors;
293 int irq;
294
295 /* Parse any "msiX" IRQs described in the devicetree */
296 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {
297 char msi_name[] = "msiX";
298
299 msi_name[3] = '0' + ctrl;
300 irq = platform_get_irq_byname_optional(pdev, msi_name);
301 if (irq == -ENXIO)
302 break;
303 if (irq < 0)
304 return dev_err_probe(dev, irq,
305 "Failed to parse MSI IRQ '%s'\n",
306 msi_name);
307
308 pp->msi_irq[ctrl] = irq;
309 }
310
311 /* If no "msiX" IRQs, caller should fallback to "msi" IRQ */
312 if (ctrl == 0)
313 return -ENXIO;
314
315 max_vectors = ctrl * MAX_MSI_IRQS_PER_CTRL;
316 if (pp->num_vectors > max_vectors) {
317 dev_warn(dev, "Exceeding number of MSI vectors, limiting to %u\n",
318 max_vectors);
319 pp->num_vectors = max_vectors;
320 }
321 if (!pp->num_vectors)
322 pp->num_vectors = max_vectors;
323
324 return 0;
325 }
326
dw_pcie_msi_host_init(struct dw_pcie_rp * pp)327 static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
328 {
329 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
330 struct device *dev = pci->dev;
331 struct platform_device *pdev = to_platform_device(dev);
332 u64 *msi_vaddr = NULL;
333 int ret;
334 u32 ctrl, num_ctrls;
335
336 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++)
337 pp->irq_mask[ctrl] = ~0;
338
339 if (!pp->msi_irq[0]) {
340 ret = dw_pcie_parse_split_msi_irq(pp);
341 if (ret < 0 && ret != -ENXIO)
342 return ret;
343 }
344
345 if (!pp->num_vectors)
346 pp->num_vectors = MSI_DEF_NUM_VECTORS;
347 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
348
349 if (!pp->msi_irq[0]) {
350 pp->msi_irq[0] = platform_get_irq_byname_optional(pdev, "msi");
351 if (pp->msi_irq[0] < 0) {
352 pp->msi_irq[0] = platform_get_irq(pdev, 0);
353 if (pp->msi_irq[0] < 0)
354 return pp->msi_irq[0];
355 }
356 }
357
358 dev_dbg(dev, "Using %d MSI vectors\n", pp->num_vectors);
359
360 pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
361
362 ret = dw_pcie_allocate_domains(pp);
363 if (ret)
364 return ret;
365
366 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
367 if (pp->msi_irq[ctrl] > 0)
368 irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
369 dw_chained_msi_isr, pp);
370 }
371
372 /*
373 * Even though the iMSI-RX Module supports 64-bit addresses some
374 * peripheral PCIe devices may lack 64-bit message support. In
375 * order not to miss MSI TLPs from those devices the MSI target
376 * address has to be within the lowest 4GB.
377 *
378 * Note until there is a better alternative found the reservation is
379 * done by allocating from the artificially limited DMA-coherent
380 * memory.
381 */
382 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
383 if (!ret)
384 msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data,
385 GFP_KERNEL);
386
387 if (!msi_vaddr) {
388 dev_warn(dev, "Failed to allocate 32-bit MSI address\n");
389 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
390 msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data,
391 GFP_KERNEL);
392 if (!msi_vaddr) {
393 dev_err(dev, "Failed to allocate MSI address\n");
394 dw_pcie_free_msi(pp);
395 return -ENOMEM;
396 }
397 }
398
399 return 0;
400 }
401
dw_pcie_host_init(struct dw_pcie_rp * pp)402 int dw_pcie_host_init(struct dw_pcie_rp *pp)
403 {
404 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
405 struct device *dev = pci->dev;
406 struct device_node *np = dev->of_node;
407 struct platform_device *pdev = to_platform_device(dev);
408 struct resource_entry *win;
409 struct pci_host_bridge *bridge;
410 struct resource *res;
411 int ret;
412
413 raw_spin_lock_init(&pp->lock);
414
415 ret = dw_pcie_get_resources(pci);
416 if (ret)
417 return ret;
418
419 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
420 if (res) {
421 pp->cfg0_size = resource_size(res);
422 pp->cfg0_base = res->start;
423
424 pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res);
425 if (IS_ERR(pp->va_cfg0_base))
426 return PTR_ERR(pp->va_cfg0_base);
427 } else {
428 dev_err(dev, "Missing *config* reg space\n");
429 return -ENODEV;
430 }
431
432 bridge = devm_pci_alloc_host_bridge(dev, 0);
433 if (!bridge)
434 return -ENOMEM;
435
436 pp->bridge = bridge;
437
438 /* Get the I/O range from DT */
439 win = resource_list_first_type(&bridge->windows, IORESOURCE_IO);
440 if (win) {
441 pp->io_size = resource_size(win->res);
442 pp->io_bus_addr = win->res->start - win->offset;
443 pp->io_base = pci_pio_to_address(win->res->start);
444 }
445
446 /* Set default bus ops */
447 bridge->ops = &dw_pcie_ops;
448 bridge->child_ops = &dw_child_pcie_ops;
449
450 if (pp->ops->host_init) {
451 ret = pp->ops->host_init(pp);
452 if (ret)
453 return ret;
454 }
455
456 if (pci_msi_enabled()) {
457 pp->has_msi_ctrl = !(pp->ops->msi_host_init ||
458 of_property_read_bool(np, "msi-parent") ||
459 of_property_read_bool(np, "msi-map"));
460
461 /*
462 * For the has_msi_ctrl case the default assignment is handled
463 * in the dw_pcie_msi_host_init().
464 */
465 if (!pp->has_msi_ctrl && !pp->num_vectors) {
466 pp->num_vectors = MSI_DEF_NUM_VECTORS;
467 } else if (pp->num_vectors > MAX_MSI_IRQS) {
468 dev_err(dev, "Invalid number of vectors\n");
469 ret = -EINVAL;
470 goto err_deinit_host;
471 }
472
473 if (pp->ops->msi_host_init) {
474 ret = pp->ops->msi_host_init(pp);
475 if (ret < 0)
476 goto err_deinit_host;
477 } else if (pp->has_msi_ctrl) {
478 ret = dw_pcie_msi_host_init(pp);
479 if (ret < 0)
480 goto err_deinit_host;
481 }
482 }
483
484 dw_pcie_version_detect(pci);
485
486 dw_pcie_iatu_detect(pci);
487
488 ret = dw_pcie_edma_detect(pci);
489 if (ret)
490 goto err_free_msi;
491
492 ret = dw_pcie_setup_rc(pp);
493 if (ret)
494 goto err_remove_edma;
495
496 if (!dw_pcie_link_up(pci)) {
497 ret = dw_pcie_start_link(pci);
498 if (ret)
499 goto err_remove_edma;
500 }
501
502 /* Ignore errors, the link may come up later */
503 dw_pcie_wait_for_link(pci);
504
505 bridge->sysdata = pp;
506
507 ret = pci_host_probe(bridge);
508 if (ret)
509 goto err_stop_link;
510
511 return 0;
512
513 err_stop_link:
514 dw_pcie_stop_link(pci);
515
516 err_remove_edma:
517 dw_pcie_edma_remove(pci);
518
519 err_free_msi:
520 if (pp->has_msi_ctrl)
521 dw_pcie_free_msi(pp);
522
523 err_deinit_host:
524 if (pp->ops->host_deinit)
525 pp->ops->host_deinit(pp);
526
527 return ret;
528 }
529 EXPORT_SYMBOL_GPL(dw_pcie_host_init);
530
dw_pcie_host_deinit(struct dw_pcie_rp * pp)531 void dw_pcie_host_deinit(struct dw_pcie_rp *pp)
532 {
533 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
534
535 pci_stop_root_bus(pp->bridge->bus);
536 pci_remove_root_bus(pp->bridge->bus);
537
538 dw_pcie_stop_link(pci);
539
540 dw_pcie_edma_remove(pci);
541
542 if (pp->has_msi_ctrl)
543 dw_pcie_free_msi(pp);
544
545 if (pp->ops->host_deinit)
546 pp->ops->host_deinit(pp);
547 }
548 EXPORT_SYMBOL_GPL(dw_pcie_host_deinit);
549
dw_pcie_other_conf_map_bus(struct pci_bus * bus,unsigned int devfn,int where)550 static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
551 unsigned int devfn, int where)
552 {
553 struct dw_pcie_rp *pp = bus->sysdata;
554 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
555 int type, ret;
556 u32 busdev;
557
558 /*
559 * Checking whether the link is up here is a last line of defense
560 * against platforms that forward errors on the system bus as
561 * SError upon PCI configuration transactions issued when the link
562 * is down. This check is racy by definition and does not stop
563 * the system from triggering an SError if the link goes down
564 * after this check is performed.
565 */
566 if (!dw_pcie_link_up(pci))
567 return NULL;
568
569 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
570 PCIE_ATU_FUNC(PCI_FUNC(devfn));
571
572 if (pci_is_root_bus(bus->parent))
573 type = PCIE_ATU_TYPE_CFG0;
574 else
575 type = PCIE_ATU_TYPE_CFG1;
576
577 ret = dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev,
578 pp->cfg0_size);
579 if (ret)
580 return NULL;
581
582 return pp->va_cfg0_base + where;
583 }
584
dw_pcie_rd_other_conf(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * val)585 static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
586 int where, int size, u32 *val)
587 {
588 struct dw_pcie_rp *pp = bus->sysdata;
589 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
590 int ret;
591
592 ret = pci_generic_config_read(bus, devfn, where, size, val);
593 if (ret != PCIBIOS_SUCCESSFUL)
594 return ret;
595
596 if (pp->cfg0_io_shared) {
597 ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
598 pp->io_base, pp->io_bus_addr,
599 pp->io_size);
600 if (ret)
601 return PCIBIOS_SET_FAILED;
602 }
603
604 return PCIBIOS_SUCCESSFUL;
605 }
606
dw_pcie_wr_other_conf(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 val)607 static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
608 int where, int size, u32 val)
609 {
610 struct dw_pcie_rp *pp = bus->sysdata;
611 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
612 int ret;
613
614 ret = pci_generic_config_write(bus, devfn, where, size, val);
615 if (ret != PCIBIOS_SUCCESSFUL)
616 return ret;
617
618 if (pp->cfg0_io_shared) {
619 ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
620 pp->io_base, pp->io_bus_addr,
621 pp->io_size);
622 if (ret)
623 return PCIBIOS_SET_FAILED;
624 }
625
626 return PCIBIOS_SUCCESSFUL;
627 }
628
629 static struct pci_ops dw_child_pcie_ops = {
630 .map_bus = dw_pcie_other_conf_map_bus,
631 .read = dw_pcie_rd_other_conf,
632 .write = dw_pcie_wr_other_conf,
633 };
634
dw_pcie_own_conf_map_bus(struct pci_bus * bus,unsigned int devfn,int where)635 void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where)
636 {
637 struct dw_pcie_rp *pp = bus->sysdata;
638 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
639
640 if (PCI_SLOT(devfn) > 0)
641 return NULL;
642
643 return pci->dbi_base + where;
644 }
645 EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus);
646
647 static struct pci_ops dw_pcie_ops = {
648 .map_bus = dw_pcie_own_conf_map_bus,
649 .read = pci_generic_config_read,
650 .write = pci_generic_config_write,
651 };
652
dw_pcie_iatu_setup(struct dw_pcie_rp * pp)653 static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
654 {
655 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
656 struct resource_entry *entry;
657 int i, ret;
658
659 /* Note the very first outbound ATU is used for CFG IOs */
660 if (!pci->num_ob_windows) {
661 dev_err(pci->dev, "No outbound iATU found\n");
662 return -EINVAL;
663 }
664
665 /*
666 * Ensure all out/inbound windows are disabled before proceeding with
667 * the MEM/IO (dma-)ranges setups.
668 */
669 for (i = 0; i < pci->num_ob_windows; i++)
670 dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_OB, i);
671
672 for (i = 0; i < pci->num_ib_windows; i++)
673 dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, i);
674
675 i = 0;
676 resource_list_for_each_entry(entry, &pp->bridge->windows) {
677 if (resource_type(entry->res) != IORESOURCE_MEM)
678 continue;
679
680 if (pci->num_ob_windows <= ++i)
681 break;
682
683 ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM,
684 entry->res->start,
685 entry->res->start - entry->offset,
686 resource_size(entry->res));
687 if (ret) {
688 dev_err(pci->dev, "Failed to set MEM range %pr\n",
689 entry->res);
690 return ret;
691 }
692 }
693
694 if (pp->io_size) {
695 if (pci->num_ob_windows > ++i) {
696 ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_IO,
697 pp->io_base,
698 pp->io_bus_addr,
699 pp->io_size);
700 if (ret) {
701 dev_err(pci->dev, "Failed to set IO range %pr\n",
702 entry->res);
703 return ret;
704 }
705 } else {
706 pp->cfg0_io_shared = true;
707 }
708 }
709
710 if (pci->num_ob_windows <= i)
711 dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n",
712 pci->num_ob_windows);
713
714 i = 0;
715 resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) {
716 if (resource_type(entry->res) != IORESOURCE_MEM)
717 continue;
718
719 if (pci->num_ib_windows <= i)
720 break;
721
722 ret = dw_pcie_prog_inbound_atu(pci, i++, PCIE_ATU_TYPE_MEM,
723 entry->res->start,
724 entry->res->start - entry->offset,
725 resource_size(entry->res));
726 if (ret) {
727 dev_err(pci->dev, "Failed to set DMA range %pr\n",
728 entry->res);
729 return ret;
730 }
731 }
732
733 if (pci->num_ib_windows <= i)
734 dev_warn(pci->dev, "Dma-ranges exceed inbound iATU size (%u)\n",
735 pci->num_ib_windows);
736
737 return 0;
738 }
739
dw_pcie_setup_rc(struct dw_pcie_rp * pp)740 int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
741 {
742 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
743 u32 val, ctrl, num_ctrls;
744 int ret;
745
746 /*
747 * Enable DBI read-only registers for writing/updating configuration.
748 * Write permission gets disabled towards the end of this function.
749 */
750 dw_pcie_dbi_ro_wr_en(pci);
751
752 dw_pcie_setup(pci);
753
754 if (pp->has_msi_ctrl) {
755 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
756
757 /* Initialize IRQ Status array */
758 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
759 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
760 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
761 pp->irq_mask[ctrl]);
762 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
763 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
764 ~0);
765 }
766 }
767
768 dw_pcie_msi_init(pp);
769
770 /* Setup RC BARs */
771 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
772 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
773
774 /* Setup interrupt pins */
775 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
776 val &= 0xffff00ff;
777 val |= 0x00000100;
778 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
779
780 /* Setup bus numbers */
781 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
782 val &= 0xff000000;
783 val |= 0x00ff0100;
784 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
785
786 /* Setup command register */
787 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
788 val &= 0xffff0000;
789 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
790 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
791 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
792
793 /*
794 * If the platform provides its own child bus config accesses, it means
795 * the platform uses its own address translation component rather than
796 * ATU, so we should not program the ATU here.
797 */
798 if (pp->bridge->child_ops == &dw_child_pcie_ops) {
799 ret = dw_pcie_iatu_setup(pp);
800 if (ret)
801 return ret;
802 }
803
804 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
805
806 /* Program correct class for RC */
807 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
808
809 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
810 val |= PORT_LOGIC_SPEED_CHANGE;
811 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
812
813 dw_pcie_dbi_ro_wr_dis(pci);
814
815 return 0;
816 }
817 EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);
818
dw_pcie_suspend_noirq(struct dw_pcie * pci)819 int dw_pcie_suspend_noirq(struct dw_pcie *pci)
820 {
821 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
822 u32 val;
823 int ret;
824
825 /*
826 * If L1SS is supported, then do not put the link into L2 as some
827 * devices such as NVMe expect low resume latency.
828 */
829 if (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM_L1)
830 return 0;
831
832 if (dw_pcie_get_ltssm(pci) <= DW_PCIE_LTSSM_DETECT_ACT)
833 return 0;
834
835 if (!pci->pp.ops->pme_turn_off)
836 return 0;
837
838 pci->pp.ops->pme_turn_off(&pci->pp);
839
840 ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE,
841 PCIE_PME_TO_L2_TIMEOUT_US/10,
842 PCIE_PME_TO_L2_TIMEOUT_US, false, pci);
843 if (ret) {
844 dev_err(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val);
845 return ret;
846 }
847
848 if (pci->pp.ops->host_deinit)
849 pci->pp.ops->host_deinit(&pci->pp);
850
851 pci->suspended = true;
852
853 return ret;
854 }
855 EXPORT_SYMBOL_GPL(dw_pcie_suspend_noirq);
856
dw_pcie_resume_noirq(struct dw_pcie * pci)857 int dw_pcie_resume_noirq(struct dw_pcie *pci)
858 {
859 int ret;
860
861 if (!pci->suspended)
862 return 0;
863
864 pci->suspended = false;
865
866 if (pci->pp.ops->host_init) {
867 ret = pci->pp.ops->host_init(&pci->pp);
868 if (ret) {
869 dev_err(pci->dev, "Host init failed: %d\n", ret);
870 return ret;
871 }
872 }
873
874 dw_pcie_setup_rc(&pci->pp);
875
876 ret = dw_pcie_start_link(pci);
877 if (ret)
878 return ret;
879
880 ret = dw_pcie_wait_for_link(pci);
881 if (ret)
882 return ret;
883
884 return ret;
885 }
886 EXPORT_SYMBOL_GPL(dw_pcie_resume_noirq);
887