| /drivers/clk/starfive/ |
| D | clk-starfive-jh7110-pll.c | 83 unsigned fbdiv : 12; /* fbdiv value should be 8 to 4095 */ member
95 unsigned int fbdiv; member
102 u32 fbdiv; member
107 char fbdiv; member
149 u32 fbdiv; member
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| /drivers/clk/zynqmp/ |
| D | pll.c | 104 u32 fbdiv; in zynqmp_pll_round_rate() local
139 u32 fbdiv, data; in zynqmp_pll_recalc_rate() local
183 u32 fbdiv; in zynqmp_pll_set_rate() local
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| /drivers/clk/analogbits/ |
| D | wrpll-cln28hpc.c | 231 u8 fbdiv, divq, best_r, r; in wrpll_configure_for_rate() local
337 u8 fbdiv; in wrpll_calc_output_rate() local
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| /drivers/clk/zynq/ |
| D | pll.c | 54 u32 fbdiv; in zynq_pll_round_rate() local
75 u32 fbdiv; in zynq_pll_recalc_rate() local
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| /drivers/clk/axs10x/ |
| D | i2s_pll_clock.c | 27 unsigned int fbdiv; member
102 unsigned int idiv, fbdiv, odiv; in i2s_pll_recalc_rate() local
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| D | pll_clock.c | 69 u32 fbdiv; member
139 u32 idiv, fbdiv, odiv; in axs10x_pll_recalc_rate() local
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| /drivers/clk/ |
| D | clk-sp7021.c | 405 u32 fbdiv; in sp_pll_calc_div() local
473 u32 fbdiv = ((reg >> clk->div_shift) & ((1 << clk->div_width) - 1)) + 1; in sp_pll_recalc_rate() local
497 u32 fbdiv = sp_pll_calc_div(clk, rate); in sp_pll_set_rate() local
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| D | clk-hsdk-pll.c | 49 u32 fbdiv; member
172 u32 idiv, fbdiv, odiv; in hsdk_pll_recalc_rate() local
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| D | clk-axm5516.c | 52 unsigned long rate, fbdiv, refdiv, postdiv; in axxia_pllclk_recalc() local
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| D | clk-bm1880.c | 477 u32 fbdiv, refdiv; in bm1880_pll_rate_calc() local
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| /drivers/clk/berlin/ |
| D | berlin2-pll.c | 46 u32 val, fbdiv, rfdiv, vcodivsel, vcodiv; in berlin2_pll_recalc_rate() local
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| D | berlin2-avpll.c | 159 u32 reg, refdiv, fbdiv; in berlin2_avpll_vco_recalc_rate() local
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| /drivers/clk/pistachio/ |
| D | clk-pll.c | 273 u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; in pll_gf40lp_frac_recalc_rate() local
413 u32 val, prediv, fbdiv, postdiv1, postdiv2; in pll_gf40lp_laint_recalc_rate() local
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| D | clk.h | 98 unsigned long long fbdiv; member
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| /drivers/clk/mmp/ |
| D | clk-pll.c | 49 u32 fbdiv, refdiv, postdiv; in mmp_clk_pll_recalc_rate() local
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| /drivers/gpu/drm/radeon/ |
| D | rv740_dpm.c | 132 u32 fbdiv; in rv740_populate_sclk_value() local
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| D | rv730_dpm.c | 51 u32 fbdiv; in rv730_populate_sclk_value() local
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| D | rs780_dpm.c | 212 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in rs780_preset_starting_fbdiv() local
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| /drivers/phy/rockchip/ |
| D | phy-rockchip-inno-dsidphy.c | 221 u16 fbdiv; member
530 u16 fbdiv = 28; in inno_dsidphy_lvds_mode_enable() local
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| D | phy-rockchip-inno-hdmi.c | 254 u16 fbdiv; member
269 u16 fbdiv; member
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| /drivers/clk/xilinx/ |
| D | xlnx_vcu.c | 90 u32 fbdiv; member
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| /drivers/clk/ralink/ |
| D | clk-mt7621.c | 262 u32 pll, prediv, fbdiv; in mt7621_cpu_recalc_rate() local
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| /drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| D | fiji_smumgr.c | 867 uint32_t fbdiv; in fiji_calculate_sclk_params() local
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| D | iceland_smumgr.c | 807 uint32_t fbdiv; in iceland_calculate_sclk_params() local
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| D | tonga_smumgr.c | 550 uint32_t fbdiv; in tonga_calculate_sclk_params() local
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