1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 */
5
6 /*
7 * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
8 * the CPU frequency subset and voltage value of each OPP varies
9 * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
10 * defines the voltage and frequency value based on the msm-id in SMEM
11 * and speedbin blown in the efuse combination.
12 * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
13 * to provide the OPP framework with required information.
14 * This is used to determine the voltage and frequency value for each OPP of
15 * operating-points-v2 table when it is parsed by the OPP framework.
16 */
17
18 #include <linux/cpu.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/nvmem-consumer.h>
24 #include <linux/of.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_domain.h>
27 #include <linux/pm_opp.h>
28 #include <linux/slab.h>
29 #include <linux/soc/qcom/smem.h>
30
31 #include <dt-bindings/arm/qcom,ids.h>
32
33 struct qcom_cpufreq_drv;
34
35 struct qcom_cpufreq_match_data {
36 int (*get_version)(struct device *cpu_dev,
37 struct nvmem_cell *speedbin_nvmem,
38 char **pvs_name,
39 struct qcom_cpufreq_drv *drv);
40 const char **genpd_names;
41 };
42
43 struct qcom_cpufreq_drv_cpu {
44 int opp_token;
45 };
46
47 struct qcom_cpufreq_drv {
48 u32 versions;
49 const struct qcom_cpufreq_match_data *data;
50 struct qcom_cpufreq_drv_cpu cpus[];
51 };
52
53 static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
54
get_krait_bin_format_a(struct device * cpu_dev,int * speed,int * pvs,int * pvs_ver,u8 * buf)55 static void get_krait_bin_format_a(struct device *cpu_dev,
56 int *speed, int *pvs, int *pvs_ver,
57 u8 *buf)
58 {
59 u32 pte_efuse;
60
61 pte_efuse = *((u32 *)buf);
62
63 *speed = pte_efuse & 0xf;
64 if (*speed == 0xf)
65 *speed = (pte_efuse >> 4) & 0xf;
66
67 if (*speed == 0xf) {
68 *speed = 0;
69 dev_warn(cpu_dev, "Speed bin: Defaulting to %d\n", *speed);
70 } else {
71 dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
72 }
73
74 *pvs = (pte_efuse >> 10) & 0x7;
75 if (*pvs == 0x7)
76 *pvs = (pte_efuse >> 13) & 0x7;
77
78 if (*pvs == 0x7) {
79 *pvs = 0;
80 dev_warn(cpu_dev, "PVS bin: Defaulting to %d\n", *pvs);
81 } else {
82 dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
83 }
84 }
85
get_krait_bin_format_b(struct device * cpu_dev,int * speed,int * pvs,int * pvs_ver,u8 * buf)86 static void get_krait_bin_format_b(struct device *cpu_dev,
87 int *speed, int *pvs, int *pvs_ver,
88 u8 *buf)
89 {
90 u32 pte_efuse, redundant_sel;
91
92 pte_efuse = *((u32 *)buf);
93 redundant_sel = (pte_efuse >> 24) & 0x7;
94
95 *pvs_ver = (pte_efuse >> 4) & 0x3;
96
97 switch (redundant_sel) {
98 case 1:
99 *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
100 *speed = (pte_efuse >> 27) & 0xf;
101 break;
102 case 2:
103 *pvs = (pte_efuse >> 27) & 0xf;
104 *speed = pte_efuse & 0x7;
105 break;
106 default:
107 /* 4 bits of PVS are in efuse register bits 31, 8-6. */
108 *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
109 *speed = pte_efuse & 0x7;
110 }
111
112 /* Check SPEED_BIN_BLOW_STATUS */
113 if (pte_efuse & BIT(3)) {
114 dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
115 } else {
116 dev_warn(cpu_dev, "Speed bin not set. Defaulting to 0!\n");
117 *speed = 0;
118 }
119
120 /* Check PVS_BLOW_STATUS */
121 pte_efuse = *(((u32 *)buf) + 1);
122 pte_efuse &= BIT(21);
123 if (pte_efuse) {
124 dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
125 } else {
126 dev_warn(cpu_dev, "PVS bin not set. Defaulting to 0!\n");
127 *pvs = 0;
128 }
129
130 dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver);
131 }
132
qcom_cpufreq_kryo_name_version(struct device * cpu_dev,struct nvmem_cell * speedbin_nvmem,char ** pvs_name,struct qcom_cpufreq_drv * drv)133 static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
134 struct nvmem_cell *speedbin_nvmem,
135 char **pvs_name,
136 struct qcom_cpufreq_drv *drv)
137 {
138 size_t len;
139 u32 msm_id;
140 u8 *speedbin;
141 int ret;
142 *pvs_name = NULL;
143
144 ret = qcom_smem_get_soc_id(&msm_id);
145 if (ret)
146 return ret;
147
148 speedbin = nvmem_cell_read(speedbin_nvmem, &len);
149 if (IS_ERR(speedbin))
150 return PTR_ERR(speedbin);
151
152 switch (msm_id) {
153 case QCOM_ID_MSM8996:
154 case QCOM_ID_APQ8096:
155 drv->versions = 1 << (unsigned int)(*speedbin);
156 break;
157 case QCOM_ID_MSM8996SG:
158 case QCOM_ID_APQ8096SG:
159 drv->versions = 1 << ((unsigned int)(*speedbin) + 4);
160 break;
161 default:
162 BUG();
163 break;
164 }
165
166 kfree(speedbin);
167 return 0;
168 }
169
qcom_cpufreq_krait_name_version(struct device * cpu_dev,struct nvmem_cell * speedbin_nvmem,char ** pvs_name,struct qcom_cpufreq_drv * drv)170 static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
171 struct nvmem_cell *speedbin_nvmem,
172 char **pvs_name,
173 struct qcom_cpufreq_drv *drv)
174 {
175 int speed = 0, pvs = 0, pvs_ver = 0;
176 u8 *speedbin;
177 size_t len;
178 int ret = 0;
179
180 speedbin = nvmem_cell_read(speedbin_nvmem, &len);
181
182 if (IS_ERR(speedbin))
183 return PTR_ERR(speedbin);
184
185 switch (len) {
186 case 4:
187 get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver,
188 speedbin);
189 break;
190 case 8:
191 get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver,
192 speedbin);
193 break;
194 default:
195 dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
196 ret = -ENODEV;
197 goto len_error;
198 }
199
200 snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d",
201 speed, pvs, pvs_ver);
202
203 drv->versions = (1 << speed);
204
205 len_error:
206 kfree(speedbin);
207 return ret;
208 }
209
210 static const struct qcom_cpufreq_match_data match_data_kryo = {
211 .get_version = qcom_cpufreq_kryo_name_version,
212 };
213
214 static const struct qcom_cpufreq_match_data match_data_krait = {
215 .get_version = qcom_cpufreq_krait_name_version,
216 };
217
218 static const char *qcs404_genpd_names[] = { "cpr", NULL };
219
220 static const struct qcom_cpufreq_match_data match_data_qcs404 = {
221 .genpd_names = qcs404_genpd_names,
222 };
223
qcom_cpufreq_probe(struct platform_device * pdev)224 static int qcom_cpufreq_probe(struct platform_device *pdev)
225 {
226 struct qcom_cpufreq_drv *drv;
227 struct nvmem_cell *speedbin_nvmem;
228 struct device_node *np;
229 struct device *cpu_dev;
230 char pvs_name_buffer[] = "speedXX-pvsXX-vXX";
231 char *pvs_name = pvs_name_buffer;
232 unsigned cpu;
233 const struct of_device_id *match;
234 int ret;
235
236 cpu_dev = get_cpu_device(0);
237 if (!cpu_dev)
238 return -ENODEV;
239
240 np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
241 if (!np)
242 return -ENOENT;
243
244 ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
245 if (!ret) {
246 of_node_put(np);
247 return -ENOENT;
248 }
249
250 drv = devm_kzalloc(&pdev->dev, struct_size(drv, cpus, num_possible_cpus()),
251 GFP_KERNEL);
252 if (!drv) {
253 of_node_put(np);
254 return -ENOMEM;
255 }
256
257 match = pdev->dev.platform_data;
258 drv->data = match->data;
259 if (!drv->data) {
260 of_node_put(np);
261 return -ENODEV;
262 }
263
264 if (drv->data->get_version) {
265 speedbin_nvmem = of_nvmem_cell_get(np, NULL);
266 if (IS_ERR(speedbin_nvmem)) {
267 of_node_put(np);
268 return dev_err_probe(cpu_dev, PTR_ERR(speedbin_nvmem),
269 "Could not get nvmem cell\n");
270 }
271
272 ret = drv->data->get_version(cpu_dev,
273 speedbin_nvmem, &pvs_name, drv);
274 if (ret) {
275 of_node_put(np);
276 nvmem_cell_put(speedbin_nvmem);
277 return ret;
278 }
279 nvmem_cell_put(speedbin_nvmem);
280 }
281 of_node_put(np);
282
283 for_each_possible_cpu(cpu) {
284 struct dev_pm_opp_config config = {
285 .supported_hw = NULL,
286 };
287
288 cpu_dev = get_cpu_device(cpu);
289 if (NULL == cpu_dev) {
290 ret = -ENODEV;
291 goto free_opp;
292 }
293
294 if (drv->data->get_version) {
295 config.supported_hw = &drv->versions;
296 config.supported_hw_count = 1;
297
298 if (pvs_name)
299 config.prop_name = pvs_name;
300 }
301
302 if (drv->data->genpd_names) {
303 config.genpd_names = drv->data->genpd_names;
304 config.virt_devs = NULL;
305 }
306
307 if (config.supported_hw || config.genpd_names) {
308 drv->cpus[cpu].opp_token = dev_pm_opp_set_config(cpu_dev, &config);
309 if (drv->cpus[cpu].opp_token < 0) {
310 ret = drv->cpus[cpu].opp_token;
311 dev_err(cpu_dev, "Failed to set OPP config\n");
312 goto free_opp;
313 }
314 }
315 }
316
317 cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1,
318 NULL, 0);
319 if (!IS_ERR(cpufreq_dt_pdev)) {
320 platform_set_drvdata(pdev, drv);
321 return 0;
322 }
323
324 ret = PTR_ERR(cpufreq_dt_pdev);
325 dev_err(cpu_dev, "Failed to register platform device\n");
326
327 free_opp:
328 for_each_possible_cpu(cpu)
329 dev_pm_opp_clear_config(drv->cpus[cpu].opp_token);
330 return ret;
331 }
332
qcom_cpufreq_remove(struct platform_device * pdev)333 static void qcom_cpufreq_remove(struct platform_device *pdev)
334 {
335 struct qcom_cpufreq_drv *drv = platform_get_drvdata(pdev);
336 unsigned int cpu;
337
338 platform_device_unregister(cpufreq_dt_pdev);
339
340 for_each_possible_cpu(cpu)
341 dev_pm_opp_clear_config(drv->cpus[cpu].opp_token);
342 }
343
344 static struct platform_driver qcom_cpufreq_driver = {
345 .probe = qcom_cpufreq_probe,
346 .remove_new = qcom_cpufreq_remove,
347 .driver = {
348 .name = "qcom-cpufreq-nvmem",
349 },
350 };
351
352 static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
353 { .compatible = "qcom,apq8096", .data = &match_data_kryo },
354 { .compatible = "qcom,msm8996", .data = &match_data_kryo },
355 { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
356 { .compatible = "qcom,ipq8064", .data = &match_data_krait },
357 { .compatible = "qcom,apq8064", .data = &match_data_krait },
358 { .compatible = "qcom,msm8974", .data = &match_data_krait },
359 { .compatible = "qcom,msm8960", .data = &match_data_krait },
360 {},
361 };
362 MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list);
363
364 /*
365 * Since the driver depends on smem and nvmem drivers, which may
366 * return EPROBE_DEFER, all the real activity is done in the probe,
367 * which may be defered as well. The init here is only registering
368 * the driver and the platform device.
369 */
qcom_cpufreq_init(void)370 static int __init qcom_cpufreq_init(void)
371 {
372 struct device_node *np = of_find_node_by_path("/");
373 const struct of_device_id *match;
374 int ret;
375
376 if (!np)
377 return -ENODEV;
378
379 match = of_match_node(qcom_cpufreq_match_list, np);
380 of_node_put(np);
381 if (!match)
382 return -ENODEV;
383
384 ret = platform_driver_register(&qcom_cpufreq_driver);
385 if (unlikely(ret < 0))
386 return ret;
387
388 cpufreq_pdev = platform_device_register_data(NULL, "qcom-cpufreq-nvmem",
389 -1, match, sizeof(*match));
390 ret = PTR_ERR_OR_ZERO(cpufreq_pdev);
391 if (0 == ret)
392 return 0;
393
394 platform_driver_unregister(&qcom_cpufreq_driver);
395 return ret;
396 }
397 module_init(qcom_cpufreq_init);
398
qcom_cpufreq_exit(void)399 static void __exit qcom_cpufreq_exit(void)
400 {
401 platform_device_unregister(cpufreq_pdev);
402 platform_driver_unregister(&qcom_cpufreq_driver);
403 }
404 module_exit(qcom_cpufreq_exit);
405
406 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. CPUfreq driver");
407 MODULE_LICENSE("GPL v2");
408