1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "priv.h"
25 #include "chan.h"
26 #include "head.h"
27 #include "ior.h"
28
29 #include <nvif/class.h>
30
31 void
gm107_sor_dp_pattern(struct nvkm_ior * sor,int pattern)32 gm107_sor_dp_pattern(struct nvkm_ior *sor, int pattern)
33 {
34 struct nvkm_device *device = sor->disp->engine.subdev.device;
35 const u32 soff = nv50_ior_base(sor);
36 u32 mask = 0x1f1f1f1f, data;
37
38 switch (pattern) {
39 case 0: data = 0x10101010; break;
40 case 1: data = 0x01010101; break;
41 case 2: data = 0x02020202; break;
42 case 3: data = 0x03030303; break;
43 case 4: data = 0x1b1b1b1b; break;
44 default:
45 WARN_ON(1);
46 return;
47 }
48
49 if (sor->asy.link & 1)
50 nvkm_mask(device, 0x61c110 + soff, mask, data);
51 else
52 nvkm_mask(device, 0x61c12c + soff, mask, data);
53 }
54
55 static const struct nvkm_ior_func_dp
56 gm107_sor_dp = {
57 .lanes = { 0, 1, 2, 3 },
58 .links = gf119_sor_dp_links,
59 .power = g94_sor_dp_power,
60 .pattern = gm107_sor_dp_pattern,
61 .drive = gf119_sor_dp_drive,
62 .vcpi = gf119_sor_dp_vcpi,
63 .audio = gf119_sor_dp_audio,
64 .audio_sym = gf119_sor_dp_audio_sym,
65 .watermark = gf119_sor_dp_watermark,
66 };
67
68 static const struct nvkm_ior_func
69 gm107_sor = {
70 .state = gf119_sor_state,
71 .power = nv50_sor_power,
72 .clock = gf119_sor_clock,
73 .hdmi = &gk104_sor_hdmi,
74 .dp = &gm107_sor_dp,
75 .hda = &gf119_sor_hda,
76 };
77
78 static int
gm107_sor_new(struct nvkm_disp * disp,int id)79 gm107_sor_new(struct nvkm_disp *disp, int id)
80 {
81 return nvkm_ior_new_(&gm107_sor, disp, SOR, id, true);
82 }
83
84 static const struct nvkm_disp_func
85 gm107_disp = {
86 .oneinit = nv50_disp_oneinit,
87 .init = gf119_disp_init,
88 .fini = gf119_disp_fini,
89 .intr = gf119_disp_intr,
90 .intr_error = gf119_disp_intr_error,
91 .super = gf119_disp_super,
92 .uevent = &gf119_disp_chan_uevent,
93 .head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
94 .dac = { .cnt = gf119_dac_cnt, .new = gf119_dac_new },
95 .sor = { .cnt = gf119_sor_cnt, .new = gm107_sor_new },
96 .root = { 0,0,GM107_DISP },
97 .user = {
98 {{0,0,GK104_DISP_CURSOR }, nvkm_disp_chan_new, &gf119_disp_curs },
99 {{0,0,GK104_DISP_OVERLAY }, nvkm_disp_chan_new, &gf119_disp_oimm },
100 {{0,0,GK110_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, &gf119_disp_base },
101 {{0,0,GM107_DISP_CORE_CHANNEL_DMA }, nvkm_disp_core_new, &gk104_disp_core },
102 {{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, nvkm_disp_chan_new, &gk104_disp_ovly },
103 {}
104 },
105 };
106
107 int
gm107_disp_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_disp ** pdisp)108 gm107_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
109 struct nvkm_disp **pdisp)
110 {
111 return nvkm_disp_new_(&gm107_disp, device, type, inst, pdisp);
112 }
113