1 /*
2 * Copyright 2019 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 #include "priv.h"
23
24 #include <subdev/mmu.h>
25
26 #include <nvfw/flcn.h>
27
28 int
gp108_acr_hsfw_load_bld(struct nvkm_falcon_fw * fw)29 gp108_acr_hsfw_load_bld(struct nvkm_falcon_fw *fw)
30 {
31 struct flcn_bl_dmem_desc_v2 hsdesc = {
32 .ctx_dma = FALCON_DMAIDX_VIRT,
33 .code_dma_base = fw->vma->addr,
34 .non_sec_code_off = fw->nmem_base,
35 .non_sec_code_size = fw->nmem_size,
36 .sec_code_off = fw->imem_base,
37 .sec_code_size = fw->imem_size,
38 .code_entry_point = 0,
39 .data_dma_base = fw->vma->addr + fw->dmem_base_img,
40 .data_size = fw->dmem_size,
41 .argc = 0,
42 .argv = 0,
43 };
44
45 flcn_bl_dmem_desc_v2_dump(fw->falcon->user, &hsdesc);
46
47 return nvkm_falcon_pio_wr(fw->falcon, (u8 *)&hsdesc, 0, 0, DMEM, 0, sizeof(hsdesc), 0, 0);
48 }
49
50 const struct nvkm_falcon_fw_func
51 gp108_acr_hsfw_0 = {
52 .signature = gm200_flcn_fw_signature,
53 .reset = gm200_flcn_fw_reset,
54 .load = gm200_flcn_fw_load,
55 .load_bld = gp108_acr_hsfw_load_bld,
56 .boot = gm200_flcn_fw_boot,
57 };
58
59 MODULE_FIRMWARE("nvidia/gp108/acr/unload_bl.bin");
60 MODULE_FIRMWARE("nvidia/gp108/acr/ucode_unload.bin");
61
62 static const struct nvkm_acr_hsf_fwif
63 gp108_acr_unload_fwif[] = {
64 { 0, gm200_acr_hsfw_ctor, &gp108_acr_hsfw_0, NVKM_ACR_HSF_PMU, 0x1d, 0x00000010 },
65 {}
66 };
67
68 const struct nvkm_falcon_fw_func
69 gp108_acr_load_0 = {
70 .signature = gm200_flcn_fw_signature,
71 .reset = gm200_flcn_fw_reset,
72 .setup = gp102_acr_load_setup,
73 .load = gm200_flcn_fw_load,
74 .load_bld = gp108_acr_hsfw_load_bld,
75 .boot = gm200_flcn_fw_boot,
76 };
77
78 MODULE_FIRMWARE("nvidia/gp108/acr/bl.bin");
79 MODULE_FIRMWARE("nvidia/gp108/acr/ucode_load.bin");
80
81 static const struct nvkm_acr_hsf_fwif
82 gp108_acr_load_fwif[] = {
83 { 0, gm200_acr_hsfw_ctor, &gp108_acr_load_0, NVKM_ACR_HSF_SEC2, 0, 0x00000010 },
84 {}
85 };
86
87 static const struct nvkm_acr_func
88 gp108_acr = {
89 .load = gp108_acr_load_fwif,
90 .unload = gp108_acr_unload_fwif,
91 .wpr_parse = gp102_acr_wpr_parse,
92 .wpr_layout = gp102_acr_wpr_layout,
93 .wpr_alloc = gp102_acr_wpr_alloc,
94 .wpr_build = gp102_acr_wpr_build,
95 .wpr_patch = gp102_acr_wpr_patch,
96 .wpr_check = gm200_acr_wpr_check,
97 .init = gm200_acr_init,
98 };
99
100 static const struct nvkm_acr_fwif
101 gp108_acr_fwif[] = {
102 { 0, gp102_acr_load, &gp108_acr },
103 { -1, gm200_acr_nofw, &gm200_acr },
104 {}
105 };
106
107 int
gp108_acr_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_acr ** pacr)108 gp108_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
109 struct nvkm_acr **pacr)
110 {
111 return nvkm_acr_new_(gp108_acr_fwif, device, type, inst, pacr);
112 }
113