| /drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_resource.h | 197 #define ABM_DCN32_REG_LIST_RI(id) \ argument
214 #define AUD_COMMON_REG_LIST_RI(id) \ argument
228 #define VPG_DCN3_REG_LIST_RI(id) \ argument
238 #define AFMT_DCN3_REG_LIST_RI(id) \ argument
250 #define APG_DCN31_REG_LIST_RI(id) \ argument
257 #define SE_DCN32_REG_LIST_RI(id) \ argument
307 #define AUX_REG_LIST_RI(id) \ argument
313 #define DCN2_AUX_REG_LIST_RI(id) \ argument
319 #define HPD_REG_LIST_RI(id) SRI_ARR(DC_HPD_CONTROL, HPD, id) argument
322 #define LE_DCN3_REG_LIST_RI(id) \ argument
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| D | dcn32_resource.c | 115 #define SR_ARR(reg_name, id) \ argument
118 #define SR_ARR_INIT(reg_name, id, value) \ argument
121 #define SRI(reg_name, block, id)\ argument
125 #define SRI_ARR(reg_name, block, id)\ argument
129 #define SR_ARR_I2C(reg_name, id) \ argument
132 #define SRI_ARR_I2C(reg_name, block, id)\ argument
136 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ argument
140 #define SRI2(reg_name, block, id)\ argument
143 #define SRI2_ARR(reg_name, block, id)\ argument
147 #define SRIR(var_name, reg_name, block, id)\ argument
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| /drivers/gpu/drm/i915/display/ |
| D | intel_dsb_regs.h | 13 #define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \ argument
15 #define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0) argument
16 #define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4) argument
17 #define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8) argument
25 #define DSB_MMIOCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0xc) argument
31 #define DSB_POLLFUNC(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x10) argument
37 #define DSB_DEBUG(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x14) argument
38 #define DSB_POLLMASK(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x1c) argument
39 #define DSB_STATUS(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x24) argument
40 #define DSB_INTERRUPT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x28) argument
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| /drivers/media/platform/samsung/s3c-camif/ |
| D | camif-regs.h | 65 #define CIGCTRL_IRQ_CLR(id) BIT(19 - (id)) argument
71 #define S3C_CAMIF_REG_CIYSA(id, n) (0x18 + (id) * 0x54 + (n) * 4) argument
73 #define S3C_CAMIF_REG_CICBSA(id, n) (0x28 + (id) * 0x54 + (n) * 4) argument
75 #define S3C_CAMIF_REG_CICRSA(id, n) (0x38 + (id) * 0x54 + (n) * 4) argument
78 #define S3C_CAMIF_REG_CITRGFMT(id, _offs) (0x48 + (id) * (0x34 + (_offs))) argument
98 #define S3C_CAMIF_REG_CICTRL(id, _offs) (0x4c + (id) * (0x34 + (_offs))) argument
111 #define S3C_CAMIF_REG_CISCPRERATIO(id, _offs) (0x50 + (id) * (0x34 + (_offs))) argument
114 #define S3C_CAMIF_REG_CISCPREDST(id, _offs) (0x54 + (id) * (0x34 + (_offs))) argument
117 #define S3C_CAMIF_REG_CISCCTRL(id, _offs) (0x58 + (id) * (0x34 + (_offs))) argument
147 #define S3C_CAMIF_REG_CITAREA(id, _offs) (0x5c + (id) * (0x34 + (_offs))) argument
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| /drivers/gpu/drm/amd/display/dc/dcn321/ |
| D | dcn321_resource.c | 118 #define SR_ARR(reg_name, id)\ argument
121 #define SR_ARR_INIT(reg_name, id, value)\ argument
124 #define SRI(reg_name, block, id)\ argument
128 #define SRI_ARR(reg_name, block, id)\ argument
132 #define SR_ARR_I2C(reg_name, id) \ argument
135 #define SRI_ARR_I2C(reg_name, block, id)\ argument
139 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ argument
143 #define SRI2(reg_name, block, id)\ argument
146 #define SRI2_ARR(reg_name, block, id)\ argument
150 #define SRIR(var_name, reg_name, block, id)\ argument
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| /drivers/reset/ |
| D | reset-uniphier.c | 15 unsigned int id; member
157 #define UNIPHIER_MIO_RESET_SD(id, ch) \ argument
160 #define UNIPHIER_MIO_RESET_SD_BRIDGE(id, ch) \ argument
163 #define UNIPHIER_MIO_RESET_EMMC_HW_RESET(id, ch) \ argument
166 #define UNIPHIER_MIO_RESET_USB2(id, ch) \ argument
169 #define UNIPHIER_MIO_RESET_USB2_BRIDGE(id, ch) \ argument
172 #define UNIPHIER_MIO_RESET_DMAC(id) \ argument
201 #define UNIPHIER_PERI_RESET_UART(id, ch) \ argument
204 #define UNIPHIER_PERI_RESET_I2C(id, ch) \ argument
207 #define UNIPHIER_PERI_RESET_FI2C(id, ch) \ argument
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| /drivers/net/ethernet/microchip/sparx5/ |
| D | sparx5_psfp.c | 23 static int sparx5_psfp_sf_get(u32 *id) in sparx5_psfp_sf_get()
28 static int sparx5_psfp_sf_put(u32 id) in sparx5_psfp_sf_put()
33 static int sparx5_psfp_sg_get(u32 idx, u32 *id) in sparx5_psfp_sg_get()
39 static int sparx5_psfp_sg_put(u32 id) in sparx5_psfp_sg_put()
44 static int sparx5_psfp_fm_get(u32 idx, u32 *id) in sparx5_psfp_fm_get()
50 static int sparx5_psfp_fm_put(u32 id) in sparx5_psfp_fm_put()
103 static void sparx5_psfp_sg_config_change(struct sparx5 *sparx5, u32 id) in sparx5_psfp_sg_config_change()
117 static void sparx5_psfp_sf_set(struct sparx5 *sparx5, u32 id, in sparx5_psfp_sf_set()
131 static int sparx5_psfp_sg_set(struct sparx5 *sparx5, u32 id, in sparx5_psfp_sg_set()
204 u32 *id) in sparx5_psfp_sf_add()
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| /drivers/gpu/host1x/hw/ |
| D | hw_host1x02_sync.h | 44 static inline u32 host1x_sync_syncpt_r(unsigned int id) in host1x_sync_syncpt_r()
48 #define HOST1X_SYNC_SYNCPT(id) \ argument
50 static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) in host1x_sync_syncpt_thresh_cpu0_int_status_r()
54 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ argument
56 static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) in host1x_sync_syncpt_thresh_int_disable_r()
60 #define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \ argument
62 static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id) in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
66 #define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \ argument
116 static inline u32 host1x_sync_mlock_owner_r(unsigned int id) in host1x_sync_mlock_owner_r()
120 #define HOST1X_SYNC_MLOCK_OWNER(id) \ argument
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| D | hw_host1x05_sync.h | 44 static inline u32 host1x_sync_syncpt_r(unsigned int id) in host1x_sync_syncpt_r()
48 #define HOST1X_SYNC_SYNCPT(id) \ argument
50 static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) in host1x_sync_syncpt_thresh_cpu0_int_status_r()
54 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ argument
56 static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) in host1x_sync_syncpt_thresh_int_disable_r()
60 #define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \ argument
62 static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id) in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
66 #define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \ argument
116 static inline u32 host1x_sync_mlock_owner_r(unsigned int id) in host1x_sync_mlock_owner_r()
120 #define HOST1X_SYNC_MLOCK_OWNER(id) \ argument
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| D | hw_host1x01_sync.h | 44 static inline u32 host1x_sync_syncpt_r(unsigned int id) in host1x_sync_syncpt_r()
48 #define HOST1X_SYNC_SYNCPT(id) \ argument
50 static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) in host1x_sync_syncpt_thresh_cpu0_int_status_r()
54 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ argument
56 static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) in host1x_sync_syncpt_thresh_int_disable_r()
60 #define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \ argument
62 static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id) in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
66 #define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \ argument
116 static inline u32 host1x_sync_mlock_owner_r(unsigned int id) in host1x_sync_mlock_owner_r()
120 #define HOST1X_SYNC_MLOCK_OWNER(id) \ argument
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| D | hw_host1x04_sync.h | 44 static inline u32 host1x_sync_syncpt_r(unsigned int id) in host1x_sync_syncpt_r()
48 #define HOST1X_SYNC_SYNCPT(id) \ argument
50 static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) in host1x_sync_syncpt_thresh_cpu0_int_status_r()
54 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ argument
56 static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) in host1x_sync_syncpt_thresh_int_disable_r()
60 #define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \ argument
62 static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id) in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
66 #define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \ argument
116 static inline u32 host1x_sync_mlock_owner_r(unsigned int id) in host1x_sync_mlock_owner_r()
120 #define HOST1X_SYNC_MLOCK_OWNER(id) \ argument
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| /drivers/gpu/drm/msm/dsi/ |
| D | dsi_manager.c | 35 #define IS_MASTER_DSI_LINK(id) (msm_dsim_glb.master_dsi_link_id == id) argument
37 static inline struct msm_dsi *dsi_mgr_get_dsi(int id) in dsi_mgr_get_dsi()
42 static inline struct msm_dsi *dsi_mgr_get_other_dsi(int id) in dsi_mgr_get_other_dsi()
47 static int dsi_mgr_parse_of(struct device_node *np, int id) in dsi_mgr_parse_of()
68 static int dsi_mgr_setup_components(int id) in dsi_mgr_setup_components()
126 dsi_mgr_phy_enable(int id, in dsi_mgr_phy_enable()
167 static void dsi_mgr_phy_disable(int id) in dsi_mgr_phy_disable()
190 int id; member
201 static void msm_dsi_manager_set_split_display(u8 id) in msm_dsi_manager_set_split_display()
233 int id = dsi_mgr_bridge_get_id(bridge); in dsi_mgr_bridge_power_on() local
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| /drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 118 #define SRI(reg_name, block, id)\ argument
122 #define SRI2(reg_name, block, id)\ argument
126 #define SRIR(var_name, reg_name, block, id)\ argument
130 #define SRII(reg_name, block, id)\ argument
134 #define SRII2(reg_name_pre, reg_name_post, id)\ argument
139 #define SRII_MPC_RMU(reg_name, block, id)\ argument
143 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
147 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ argument
150 #define DCCG_SRII(reg_name, block, id)\ argument
154 #define VUPDATE_SRII(reg_name, block, id)\ argument
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| /drivers/hwtracing/coresight/ |
| D | coresight-trace-id.c | 38 #define DUMP_ID_CPU(cpu, id) pr_debug("%s called; cpu=%d, id=%d\n", __func__, cpu, id) argument
39 #define DUMP_ID(id) pr_debug("%s called; id=%d\n", __func__, id) argument
43 #define DUMP_ID(id) argument
44 #define DUMP_ID_CPU(cpu, id) argument
85 int id = 0; in coresight_trace_id_alloc_new_id() local
113 static void coresight_trace_id_free(int id, struct coresight_trace_id_map *id_map) in coresight_trace_id_free()
122 static void coresight_trace_id_set_pend_rel(int id, struct coresight_trace_id_map *id_map) in coresight_trace_id_set_pend_rel()
157 int id; in coresight_trace_id_map_get_cpu_id() local
201 int id; in coresight_trace_id_map_put_cpu_id() local
228 int id; in coresight_trace_id_map_get_system_id() local
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| /drivers/gpu/drm/amd/display/dc/dcn316/ |
| D | dcn316_resource.c | 153 #define SRI(reg_name, block, id)\ argument
157 #define SRI2(reg_name, block, id)\ argument
161 #define SRIR(var_name, reg_name, block, id)\ argument
165 #define SRII(reg_name, block, id)\ argument
169 #define SRII_MPC_RMU(reg_name, block, id)\ argument
173 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
177 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ argument
180 #define DCCG_SRII(reg_name, block, id)\ argument
184 #define VUPDATE_SRII(reg_name, block, id)\ argument
225 #define abm_regs(id)\ argument
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| /drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_resource.c | 157 #define SRI(reg_name, block, id)\ argument
160 #define SRI2(reg_name, block, id)\ argument
163 #define SRII(reg_name, block, id)\ argument
167 #define DCCG_SRII(reg_name, block, id)\ argument
171 #define VUPDATE_SRII(reg_name, block, id)\ argument
175 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
179 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ argument
182 #define SRII_MPC_RMU(reg_name, block, id)\ argument
198 #define vmid_regs(id)\ argument
252 #define vpg_regs(id)\ argument
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| /drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_resource.c | 179 #define SRI(reg_name, block, id)\ argument
182 #define SRI2(reg_name, block, id)\ argument
185 #define SRII(reg_name, block, id)\ argument
189 #define DCCG_SRII(reg_name, block, id)\ argument
193 #define VUPDATE_SRII(reg_name, block, id)\ argument
197 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
201 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ argument
204 #define SRII_MPC_RMU(reg_name, block, id)\ argument
220 #define vmid_regs(id)\ argument
274 #define vpg_regs(id)\ argument
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| /drivers/gpu/drm/amd/display/dc/dcn314/ |
| D | dcn314_resource.c | 147 #define SRI(reg_name, block, id)\ argument
151 #define SRI2(reg_name, block, id)\ argument
155 #define SRIR(var_name, reg_name, block, id)\ argument
159 #define SRII(reg_name, block, id)\ argument
163 #define SRII_MPC_RMU(reg_name, block, id)\ argument
167 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
171 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ argument
174 #define DCCG_SRII(reg_name, block, id)\ argument
178 #define VUPDATE_SRII(reg_name, block, id)\ argument
242 #define abm_regs(id)\ argument
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_resource.c | 131 #define SRI(reg_name, block, id)\ argument
135 #define SRI2(reg_name, block, id)\ argument
139 #define SRIR(var_name, reg_name, block, id)\ argument
143 #define SRII(reg_name, block, id)\ argument
147 #define SRII_MPC_RMU(reg_name, block, id)\ argument
151 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
155 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ argument
158 #define DCCG_SRII(reg_name, block, id)\ argument
162 #define VUPDATE_SRII(reg_name, block, id)\ argument
234 #define abm_regs(id)\ argument
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| /drivers/net/ethernet/intel/fm10k/ |
| D | fm10k_tlv.h | 62 unsigned int id; member
67 #define FM10K_TLV_ATTR_NULL_STRING(id, len) { id, FM10K_TLV_NULL_STRING, len } argument
68 #define FM10K_TLV_ATTR_MAC_ADDR(id) { id, FM10K_TLV_MAC_ADDR, 6 } argument
69 #define FM10K_TLV_ATTR_BOOL(id) { id, FM10K_TLV_BOOL, 0 } argument
70 #define FM10K_TLV_ATTR_U8(id) { id, FM10K_TLV_UNSIGNED, 1 } argument
71 #define FM10K_TLV_ATTR_U16(id) { id, FM10K_TLV_UNSIGNED, 2 } argument
72 #define FM10K_TLV_ATTR_U32(id) { id, FM10K_TLV_UNSIGNED, 4 } argument
73 #define FM10K_TLV_ATTR_U64(id) { id, FM10K_TLV_UNSIGNED, 8 } argument
74 #define FM10K_TLV_ATTR_S8(id) { id, FM10K_TLV_SIGNED, 1 } argument
75 #define FM10K_TLV_ATTR_S16(id) { id, FM10K_TLV_SIGNED, 2 } argument
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| /drivers/gpu/drm/amd/display/dc/dcn315/ |
| D | dcn315_resource.c | 165 #define SRI(reg_name, block, id)\ argument
169 #define SRI2(reg_name, block, id)\ argument
173 #define SRIR(var_name, reg_name, block, id)\ argument
177 #define SRII(reg_name, block, id)\ argument
181 #define SRII_MPC_RMU(reg_name, block, id)\ argument
185 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
189 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ argument
192 #define DCCG_SRII(reg_name, block, id)\ argument
196 #define VUPDATE_SRII(reg_name, block, id)\ argument
237 #define abm_regs(id)\ argument
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| /drivers/gpu/drm/amd/display/dc/gpio/ |
| D | gpio_service.c | 131 enum gpio_id id; in dal_gpio_service_create_irq() local
147 enum gpio_id id; in dal_gpio_service_create_generic_mux() local
178 enum gpio_id id, in dal_gpio_get_generic_pin_info()
239 enum gpio_id id, in is_pin_busy()
247 enum gpio_id id, in set_pin_busy()
255 enum gpio_id id, in set_pin_free()
263 enum gpio_id id, in dal_gpio_service_lock()
277 enum gpio_id id, in dal_gpio_service_unlock()
293 enum gpio_id id = gpio->id; in dal_gpio_service_open() local
377 enum gpio_id id = dal_gpio_get_id(irq); in dal_irq_get_source() local
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| /drivers/macintosh/ |
| D | adbhid.c | 212 int id; member
268 int id = (data[0] >> 4) & 0x0f; in adbhid_keyboard_input() local
285 adbhid_input_keycode(int id, int scancode, int repeat) in adbhid_input_keycode()
407 int id = (data[0] >> 4) & 0x0f; in adbhid_mouse_input() local
505 int id = (data[0] >> 4) & 0x0f; in adbhid_buttons_input() local
753 adbhid_input_register(int id, int default_id, int original_handler_id, in adbhid_input_register()
914 static void adbhid_input_unregister(int id) in adbhid_input_unregister()
924 adbhid_input_reregister(int id, int default_id, int org_handler_id, in adbhid_input_reregister()
961 int id = keyboard_ids.id[i]; in adbhid_probe() local
985 int id = buttons_ids.id[i]; in adbhid_probe() local
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| /drivers/i2c/busses/ |
| D | i2c-cadence.c | 237 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id) in cdns_i2c_clear_bus_hold()
244 static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround) in cdns_is_holdquirk()
251 static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id) in cdns_i2c_set_mode()
294 static void cdns_i2c_slave_rcv_data(struct cdns_i2c *id) in cdns_i2c_slave_rcv_data()
315 static void cdns_i2c_slave_send_data(struct cdns_i2c *id) in cdns_i2c_slave_send_data()
342 struct cdns_i2c *id = ptr; in cdns_i2c_slave_isr() local
403 struct cdns_i2c *id = ptr; in cdns_i2c_master_isr() local
556 struct cdns_i2c *id = ptr; in cdns_i2c_isr() local
568 static void cdns_i2c_mrecv(struct cdns_i2c *id) in cdns_i2c_mrecv()
665 static void cdns_i2c_msend(struct cdns_i2c *id) in cdns_i2c_msend()
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| /drivers/gpu/drm/amd/display/dc/dcn201/ |
| D | dcn201_resource.c | 255 #define SRI(reg_name, block, id)\ argument
259 #define SRIR(var_name, reg_name, block, id)\ argument
263 #define SRII(reg_name, block, id)\ argument
267 #define SRI_IX(reg_name, block, id)\ argument
270 #define DCCG_SRII(reg_name, block, id)\ argument
274 #define VUPDATE_SRII(reg_name, block, id)\ argument
323 #define audio_regs(id)\ argument
346 #define stream_enc_regs(id)\ argument
372 #define aux_regs(id)\ argument
382 #define hpd_regs(id)\ argument
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