1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2018 Intel Corporation
4 *
5 * Author: Gaurav K Singh <gaurav.k.singh@intel.com>
6 * Manasi Navare <manasi.d.navare@intel.com>
7 */
8 #include <linux/limits.h>
9
10 #include <drm/display/drm_dsc_helper.h>
11
12 #include "i915_drv.h"
13 #include "i915_reg.h"
14 #include "intel_crtc.h"
15 #include "intel_de.h"
16 #include "intel_display_types.h"
17 #include "intel_dsi.h"
18 #include "intel_qp_tables.h"
19 #include "intel_vdsc.h"
20 #include "intel_vdsc_regs.h"
21
intel_dsc_source_support(const struct intel_crtc_state * crtc_state)22 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
23 {
24 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
25 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
26 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
27
28 if (!HAS_DSC(i915))
29 return false;
30
31 if (DISPLAY_VER(i915) == 11 && cpu_transcoder == TRANSCODER_A)
32 return false;
33
34 return true;
35 }
36
is_pipe_dsc(struct intel_crtc * crtc,enum transcoder cpu_transcoder)37 static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
38 {
39 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
40
41 if (DISPLAY_VER(i915) >= 12)
42 return true;
43
44 if (cpu_transcoder == TRANSCODER_EDP ||
45 cpu_transcoder == TRANSCODER_DSI_0 ||
46 cpu_transcoder == TRANSCODER_DSI_1)
47 return false;
48
49 /* There's no pipe A DSC engine on ICL */
50 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A);
51
52 return true;
53 }
54
55 static void
intel_vdsc_set_min_max_qp(struct drm_dsc_config * vdsc_cfg,int buf,int bpp)56 intel_vdsc_set_min_max_qp(struct drm_dsc_config *vdsc_cfg, int buf,
57 int bpp)
58 {
59 int bpc = vdsc_cfg->bits_per_component;
60
61 /* Read range_minqp and range_max_qp from qp tables */
62 vdsc_cfg->rc_range_params[buf].range_min_qp =
63 intel_lookup_range_min_qp(bpc, buf, bpp, vdsc_cfg->native_420);
64 vdsc_cfg->rc_range_params[buf].range_max_qp =
65 intel_lookup_range_max_qp(bpc, buf, bpp, vdsc_cfg->native_420);
66 }
67
68 /*
69 * We are using the method provided in DSC 1.2a C-Model in codec_main.c
70 * Above method use a common formula to derive values for any combination of DSC
71 * variables. The formula approach may yield slight differences in the derived PPS
72 * parameters from the original parameter sets. These differences are not consequential
73 * to the coding performance because all parameter sets have been shown to produce
74 * visually lossless quality (provides the same PPS values as
75 * DSCParameterValuesVESA V1-2 spreadsheet).
76 */
77 static void
calculate_rc_params(struct drm_dsc_config * vdsc_cfg)78 calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
79 {
80 int bpc = vdsc_cfg->bits_per_component;
81 int bpp = vdsc_cfg->bits_per_pixel >> 4;
82 int qp_bpc_modifier = (bpc - 8) * 2;
83 u32 res, buf_i, bpp_i;
84
85 if (vdsc_cfg->slice_height >= 8)
86 vdsc_cfg->first_line_bpg_offset =
87 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
88 else
89 vdsc_cfg->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
90
91 /*
92 * According to DSC 1.2 spec in Section 4.1 if native_420 is set:
93 * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice
94 * height < 8.
95 * -second_line_offset_adj is 512 as shown by emperical values to yield best chroma
96 * preservation in second line.
97 * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded
98 * up to 16 fractional bits, we left shift second line offset by 11 to preserve 11
99 * fractional bits.
100 */
101 if (vdsc_cfg->native_420) {
102 if (vdsc_cfg->slice_height >= 8)
103 vdsc_cfg->second_line_bpg_offset = 12;
104 else
105 vdsc_cfg->second_line_bpg_offset =
106 2 * (vdsc_cfg->slice_height - 1);
107
108 vdsc_cfg->second_line_offset_adj = 512;
109 vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11,
110 vdsc_cfg->slice_height - 1);
111 }
112
113 /* Our hw supports only 444 modes as of today */
114 if (bpp >= 12)
115 vdsc_cfg->initial_offset = 2048;
116 else if (bpp >= 10)
117 vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
118 else if (bpp >= 8)
119 vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
120 else
121 vdsc_cfg->initial_offset = 6144;
122
123 /* initial_xmit_delay = rc_model_size/2/compression_bpp */
124 vdsc_cfg->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
125
126 vdsc_cfg->flatness_min_qp = 3 + qp_bpc_modifier;
127 vdsc_cfg->flatness_max_qp = 12 + qp_bpc_modifier;
128
129 vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
130 vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
131
132 if (vdsc_cfg->native_420) {
133 static const s8 ofs_und4[] = {
134 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
135 };
136 static const s8 ofs_und5[] = {
137 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
138 };
139 static const s8 ofs_und6[] = {
140 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
141 };
142 static const s8 ofs_und8[] = {
143 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
144 };
145
146 bpp_i = bpp - 8;
147 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
148 u8 range_bpg_offset;
149
150 intel_vdsc_set_min_max_qp(vdsc_cfg, buf_i, bpp_i);
151
152 /* Calculate range_bpg_offset */
153 if (bpp <= 8) {
154 range_bpg_offset = ofs_und4[buf_i];
155 } else if (bpp <= 10) {
156 res = DIV_ROUND_UP(((bpp - 8) *
157 (ofs_und5[buf_i] - ofs_und4[buf_i])), 2);
158 range_bpg_offset = ofs_und4[buf_i] + res;
159 } else if (bpp <= 12) {
160 res = DIV_ROUND_UP(((bpp - 10) *
161 (ofs_und6[buf_i] - ofs_und5[buf_i])), 2);
162 range_bpg_offset = ofs_und5[buf_i] + res;
163 } else if (bpp <= 16) {
164 res = DIV_ROUND_UP(((bpp - 12) *
165 (ofs_und8[buf_i] - ofs_und6[buf_i])), 4);
166 range_bpg_offset = ofs_und6[buf_i] + res;
167 } else {
168 range_bpg_offset = ofs_und8[buf_i];
169 }
170
171 vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
172 range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
173 }
174 } else {
175 static const s8 ofs_und6[] = {
176 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
177 };
178 static const s8 ofs_und8[] = {
179 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
180 };
181 static const s8 ofs_und12[] = {
182 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
183 };
184 static const s8 ofs_und15[] = {
185 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
186 };
187
188 bpp_i = (2 * (bpp - 6));
189 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
190 u8 range_bpg_offset;
191
192 intel_vdsc_set_min_max_qp(vdsc_cfg, buf_i, bpp_i);
193
194 /* Calculate range_bpg_offset */
195 if (bpp <= 6) {
196 range_bpg_offset = ofs_und6[buf_i];
197 } else if (bpp <= 8) {
198 res = DIV_ROUND_UP(((bpp - 6) *
199 (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
200 range_bpg_offset = ofs_und6[buf_i] + res;
201 } else if (bpp <= 12) {
202 range_bpg_offset = ofs_und8[buf_i];
203 } else if (bpp <= 15) {
204 res = DIV_ROUND_UP(((bpp - 12) *
205 (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
206 range_bpg_offset = ofs_und12[buf_i] + res;
207 } else {
208 range_bpg_offset = ofs_und15[buf_i];
209 }
210
211 vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
212 range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
213 }
214 }
215 }
216
intel_dsc_slice_dimensions_valid(struct intel_crtc_state * pipe_config,struct drm_dsc_config * vdsc_cfg)217 static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config,
218 struct drm_dsc_config *vdsc_cfg)
219 {
220 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB ||
221 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
222 if (vdsc_cfg->slice_height > 4095)
223 return -EINVAL;
224 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 15000)
225 return -EINVAL;
226 } else if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
227 if (vdsc_cfg->slice_width % 2)
228 return -EINVAL;
229 if (vdsc_cfg->slice_height % 2)
230 return -EINVAL;
231 if (vdsc_cfg->slice_height > 4094)
232 return -EINVAL;
233 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 30000)
234 return -EINVAL;
235 }
236
237 return 0;
238 }
239
intel_dsc_compute_params(struct intel_crtc_state * pipe_config)240 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
241 {
242 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
243 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
244 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
245 u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
246 int err;
247 int ret;
248
249 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
250 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
251 pipe_config->dsc.slice_count);
252
253 err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg);
254
255 if (err) {
256 drm_dbg_kms(&dev_priv->drm, "Slice dimension requirements not met\n");
257 return err;
258 }
259
260 /*
261 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
262 * else 1
263 */
264 vdsc_cfg->convert_rgb = pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 &&
265 pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR444;
266
267 if (DISPLAY_VER(dev_priv) >= 14 &&
268 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
269 vdsc_cfg->native_420 = true;
270 /* We do not support YcBCr422 as of now */
271 vdsc_cfg->native_422 = false;
272 vdsc_cfg->simple_422 = false;
273 /* Gen 11 does not support VBR */
274 vdsc_cfg->vbr_enable = false;
275
276 /* Gen 11 only supports integral values of bpp */
277 vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
278
279 /*
280 * According to DSC 1.2 specs in Section 4.1 if native_420 is set
281 * we need to double the current bpp.
282 */
283 if (vdsc_cfg->native_420)
284 vdsc_cfg->bits_per_pixel <<= 1;
285
286 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
287
288 drm_dsc_set_rc_buf_thresh(vdsc_cfg);
289
290 /*
291 * From XE_LPD onwards we supports compression bpps in steps of 1
292 * upto uncompressed bpp-1, hence add calculations for all the rc
293 * parameters
294 */
295 if (DISPLAY_VER(dev_priv) >= 13) {
296 calculate_rc_params(vdsc_cfg);
297 } else {
298 if ((compressed_bpp == 8 ||
299 compressed_bpp == 12) &&
300 (vdsc_cfg->bits_per_component == 8 ||
301 vdsc_cfg->bits_per_component == 10 ||
302 vdsc_cfg->bits_per_component == 12))
303 ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
304 else
305 ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
306
307 if (ret)
308 return ret;
309 }
310
311 /*
312 * BitsPerComponent value determines mux_word_size:
313 * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
314 * 48 bits otherwise 64
315 */
316 if (vdsc_cfg->bits_per_component <= 10)
317 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
318 else
319 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
320
321 /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
322 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
323 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
324
325 return 0;
326 }
327
328 enum intel_display_power_domain
intel_dsc_power_domain(struct intel_crtc * crtc,enum transcoder cpu_transcoder)329 intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
330 {
331 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
332 enum pipe pipe = crtc->pipe;
333
334 /*
335 * VDSC/joining uses a separate power well, PW2, and requires
336 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases:
337 *
338 * - ICL eDP/DSI transcoder
339 * - Display version 12 (except RKL) pipe A
340 *
341 * For any other pipe, VDSC/joining uses the power well associated with
342 * the pipe in use. Hence another reference on the pipe power domain
343 * will suffice. (Except no VDSC/joining on ICL pipe A.)
344 */
345 if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
346 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
347 else if (is_pipe_dsc(crtc, cpu_transcoder))
348 return POWER_DOMAIN_PIPE(pipe);
349 else
350 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
351 }
352
intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state * crtc_state)353 int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
354 {
355 int num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;
356
357 if (crtc_state->bigjoiner_pipes)
358 num_vdsc_instances *= 2;
359
360 return num_vdsc_instances;
361 }
362
intel_dsc_pps_configure(const struct intel_crtc_state * crtc_state)363 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
364 {
365 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
366 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
367 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
368 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
369 enum pipe pipe = crtc->pipe;
370 u32 pps_val = 0;
371 u32 rc_buf_thresh_dword[4];
372 u32 rc_range_params_dword[8];
373 int i = 0;
374 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
375
376 /* Populate PICTURE_PARAMETER_SET_0 registers */
377 pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
378 DSC_VER_MIN_SHIFT |
379 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
380 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
381 if (vdsc_cfg->dsc_version_minor == 2) {
382 pps_val |= DSC_ALT_ICH_SEL;
383 if (vdsc_cfg->native_420)
384 pps_val |= DSC_NATIVE_420_ENABLE;
385 if (vdsc_cfg->native_422)
386 pps_val |= DSC_NATIVE_422_ENABLE;
387 }
388 if (vdsc_cfg->block_pred_enable)
389 pps_val |= DSC_BLOCK_PREDICTION;
390 if (vdsc_cfg->convert_rgb)
391 pps_val |= DSC_COLOR_SPACE_CONVERSION;
392 if (vdsc_cfg->simple_422)
393 pps_val |= DSC_422_ENABLE;
394 if (vdsc_cfg->vbr_enable)
395 pps_val |= DSC_VBR_ENABLE;
396 drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
397 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
398 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0,
399 pps_val);
400 /*
401 * If 2 VDSC instances are needed, configure PPS for second
402 * VDSC
403 */
404 if (crtc_state->dsc.dsc_split)
405 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0,
406 pps_val);
407 } else {
408 intel_de_write(dev_priv,
409 ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe),
410 pps_val);
411 if (crtc_state->dsc.dsc_split)
412 intel_de_write(dev_priv,
413 ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
414 pps_val);
415 }
416
417 /* Populate PICTURE_PARAMETER_SET_1 registers */
418 pps_val = 0;
419 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
420 drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
421 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
422 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1,
423 pps_val);
424 /*
425 * If 2 VDSC instances are needed, configure PPS for second
426 * VDSC
427 */
428 if (crtc_state->dsc.dsc_split)
429 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1,
430 pps_val);
431 } else {
432 intel_de_write(dev_priv,
433 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe),
434 pps_val);
435 if (crtc_state->dsc.dsc_split)
436 intel_de_write(dev_priv,
437 ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
438 pps_val);
439 }
440
441 /* Populate PICTURE_PARAMETER_SET_2 registers */
442 pps_val = 0;
443 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
444 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
445 drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
446 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
447 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2,
448 pps_val);
449 /*
450 * If 2 VDSC instances are needed, configure PPS for second
451 * VDSC
452 */
453 if (crtc_state->dsc.dsc_split)
454 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2,
455 pps_val);
456 } else {
457 intel_de_write(dev_priv,
458 ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe),
459 pps_val);
460 if (crtc_state->dsc.dsc_split)
461 intel_de_write(dev_priv,
462 ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
463 pps_val);
464 }
465
466 /* Populate PICTURE_PARAMETER_SET_3 registers */
467 pps_val = 0;
468 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
469 DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
470 drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
471 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
472 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3,
473 pps_val);
474 /*
475 * If 2 VDSC instances are needed, configure PPS for second
476 * VDSC
477 */
478 if (crtc_state->dsc.dsc_split)
479 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3,
480 pps_val);
481 } else {
482 intel_de_write(dev_priv,
483 ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe),
484 pps_val);
485 if (crtc_state->dsc.dsc_split)
486 intel_de_write(dev_priv,
487 ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
488 pps_val);
489 }
490
491 /* Populate PICTURE_PARAMETER_SET_4 registers */
492 pps_val = 0;
493 pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
494 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
495 drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
496 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
497 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4,
498 pps_val);
499 /*
500 * If 2 VDSC instances are needed, configure PPS for second
501 * VDSC
502 */
503 if (crtc_state->dsc.dsc_split)
504 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4,
505 pps_val);
506 } else {
507 intel_de_write(dev_priv,
508 ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe),
509 pps_val);
510 if (crtc_state->dsc.dsc_split)
511 intel_de_write(dev_priv,
512 ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
513 pps_val);
514 }
515
516 /* Populate PICTURE_PARAMETER_SET_5 registers */
517 pps_val = 0;
518 pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
519 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
520 drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
521 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
522 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5,
523 pps_val);
524 /*
525 * If 2 VDSC instances are needed, configure PPS for second
526 * VDSC
527 */
528 if (crtc_state->dsc.dsc_split)
529 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5,
530 pps_val);
531 } else {
532 intel_de_write(dev_priv,
533 ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe),
534 pps_val);
535 if (crtc_state->dsc.dsc_split)
536 intel_de_write(dev_priv,
537 ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
538 pps_val);
539 }
540
541 /* Populate PICTURE_PARAMETER_SET_6 registers */
542 pps_val = 0;
543 pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
544 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
545 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
546 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
547 drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
548 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
549 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6,
550 pps_val);
551 /*
552 * If 2 VDSC instances are needed, configure PPS for second
553 * VDSC
554 */
555 if (crtc_state->dsc.dsc_split)
556 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6,
557 pps_val);
558 } else {
559 intel_de_write(dev_priv,
560 ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe),
561 pps_val);
562 if (crtc_state->dsc.dsc_split)
563 intel_de_write(dev_priv,
564 ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
565 pps_val);
566 }
567
568 /* Populate PICTURE_PARAMETER_SET_7 registers */
569 pps_val = 0;
570 pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
571 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
572 drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
573 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
574 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7,
575 pps_val);
576 /*
577 * If 2 VDSC instances are needed, configure PPS for second
578 * VDSC
579 */
580 if (crtc_state->dsc.dsc_split)
581 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7,
582 pps_val);
583 } else {
584 intel_de_write(dev_priv,
585 ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe),
586 pps_val);
587 if (crtc_state->dsc.dsc_split)
588 intel_de_write(dev_priv,
589 ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
590 pps_val);
591 }
592
593 /* Populate PICTURE_PARAMETER_SET_8 registers */
594 pps_val = 0;
595 pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
596 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
597 drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
598 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
599 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8,
600 pps_val);
601 /*
602 * If 2 VDSC instances are needed, configure PPS for second
603 * VDSC
604 */
605 if (crtc_state->dsc.dsc_split)
606 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8,
607 pps_val);
608 } else {
609 intel_de_write(dev_priv,
610 ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe),
611 pps_val);
612 if (crtc_state->dsc.dsc_split)
613 intel_de_write(dev_priv,
614 ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
615 pps_val);
616 }
617
618 /* Populate PICTURE_PARAMETER_SET_9 registers */
619 pps_val = 0;
620 pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
621 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
622 drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
623 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
624 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9,
625 pps_val);
626 /*
627 * If 2 VDSC instances are needed, configure PPS for second
628 * VDSC
629 */
630 if (crtc_state->dsc.dsc_split)
631 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9,
632 pps_val);
633 } else {
634 intel_de_write(dev_priv,
635 ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe),
636 pps_val);
637 if (crtc_state->dsc.dsc_split)
638 intel_de_write(dev_priv,
639 ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
640 pps_val);
641 }
642
643 /* Populate PICTURE_PARAMETER_SET_10 registers */
644 pps_val = 0;
645 pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
646 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
647 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
648 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
649 drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
650 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
651 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10,
652 pps_val);
653 /*
654 * If 2 VDSC instances are needed, configure PPS for second
655 * VDSC
656 */
657 if (crtc_state->dsc.dsc_split)
658 intel_de_write(dev_priv,
659 DSCC_PICTURE_PARAMETER_SET_10, pps_val);
660 } else {
661 intel_de_write(dev_priv,
662 ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe),
663 pps_val);
664 if (crtc_state->dsc.dsc_split)
665 intel_de_write(dev_priv,
666 ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
667 pps_val);
668 }
669
670 /* Populate Picture parameter set 16 */
671 pps_val = 0;
672 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
673 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
674 vdsc_cfg->slice_width) |
675 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
676 vdsc_cfg->slice_height);
677 drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
678 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
679 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16,
680 pps_val);
681 /*
682 * If 2 VDSC instances are needed, configure PPS for second
683 * VDSC
684 */
685 if (crtc_state->dsc.dsc_split)
686 intel_de_write(dev_priv,
687 DSCC_PICTURE_PARAMETER_SET_16, pps_val);
688 } else {
689 intel_de_write(dev_priv,
690 ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe),
691 pps_val);
692 if (crtc_state->dsc.dsc_split)
693 intel_de_write(dev_priv,
694 ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
695 pps_val);
696 }
697
698 if (DISPLAY_VER(dev_priv) >= 14) {
699 /* Populate PICTURE_PARAMETER_SET_17 registers */
700 pps_val = 0;
701 pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
702 drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
703 intel_de_write(dev_priv,
704 MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe),
705 pps_val);
706 if (crtc_state->dsc.dsc_split)
707 intel_de_write(dev_priv,
708 MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe),
709 pps_val);
710
711 /* Populate PICTURE_PARAMETER_SET_18 registers */
712 pps_val = 0;
713 pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
714 DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
715 drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
716 intel_de_write(dev_priv,
717 MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe),
718 pps_val);
719 if (crtc_state->dsc.dsc_split)
720 intel_de_write(dev_priv,
721 MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe),
722 pps_val);
723 }
724
725 /* Populate the RC_BUF_THRESH registers */
726 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
727 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
728 rc_buf_thresh_dword[i / 4] |=
729 (u32)(vdsc_cfg->rc_buf_thresh[i] <<
730 BITS_PER_BYTE * (i % 4));
731 drm_dbg_kms(&dev_priv->drm, "RC_BUF_THRESH_%d = 0x%08x\n", i,
732 rc_buf_thresh_dword[i / 4]);
733 }
734 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
735 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,
736 rc_buf_thresh_dword[0]);
737 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW,
738 rc_buf_thresh_dword[1]);
739 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1,
740 rc_buf_thresh_dword[2]);
741 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW,
742 rc_buf_thresh_dword[3]);
743 if (crtc_state->dsc.dsc_split) {
744 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0,
745 rc_buf_thresh_dword[0]);
746 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW,
747 rc_buf_thresh_dword[1]);
748 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1,
749 rc_buf_thresh_dword[2]);
750 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW,
751 rc_buf_thresh_dword[3]);
752 }
753 } else {
754 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe),
755 rc_buf_thresh_dword[0]);
756 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
757 rc_buf_thresh_dword[1]);
758 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe),
759 rc_buf_thresh_dword[2]);
760 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
761 rc_buf_thresh_dword[3]);
762 if (crtc_state->dsc.dsc_split) {
763 intel_de_write(dev_priv,
764 ICL_DSC1_RC_BUF_THRESH_0(pipe),
765 rc_buf_thresh_dword[0]);
766 intel_de_write(dev_priv,
767 ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
768 rc_buf_thresh_dword[1]);
769 intel_de_write(dev_priv,
770 ICL_DSC1_RC_BUF_THRESH_1(pipe),
771 rc_buf_thresh_dword[2]);
772 intel_de_write(dev_priv,
773 ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
774 rc_buf_thresh_dword[3]);
775 }
776 }
777
778 /* Populate the RC_RANGE_PARAMETERS registers */
779 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));
780 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
781 rc_range_params_dword[i / 2] |=
782 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
783 RC_BPG_OFFSET_SHIFT) |
784 (vdsc_cfg->rc_range_params[i].range_max_qp <<
785 RC_MAX_QP_SHIFT) |
786 (vdsc_cfg->rc_range_params[i].range_min_qp <<
787 RC_MIN_QP_SHIFT)) << 16 * (i % 2));
788 drm_dbg_kms(&dev_priv->drm, "RC_RANGE_PARAM_%d = 0x%08x\n", i,
789 rc_range_params_dword[i / 2]);
790 }
791 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
792 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,
793 rc_range_params_dword[0]);
794 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW,
795 rc_range_params_dword[1]);
796 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1,
797 rc_range_params_dword[2]);
798 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW,
799 rc_range_params_dword[3]);
800 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2,
801 rc_range_params_dword[4]);
802 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW,
803 rc_range_params_dword[5]);
804 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3,
805 rc_range_params_dword[6]);
806 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW,
807 rc_range_params_dword[7]);
808 if (crtc_state->dsc.dsc_split) {
809 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0,
810 rc_range_params_dword[0]);
811 intel_de_write(dev_priv,
812 DSCC_RC_RANGE_PARAMETERS_0_UDW,
813 rc_range_params_dword[1]);
814 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1,
815 rc_range_params_dword[2]);
816 intel_de_write(dev_priv,
817 DSCC_RC_RANGE_PARAMETERS_1_UDW,
818 rc_range_params_dword[3]);
819 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2,
820 rc_range_params_dword[4]);
821 intel_de_write(dev_priv,
822 DSCC_RC_RANGE_PARAMETERS_2_UDW,
823 rc_range_params_dword[5]);
824 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3,
825 rc_range_params_dword[6]);
826 intel_de_write(dev_priv,
827 DSCC_RC_RANGE_PARAMETERS_3_UDW,
828 rc_range_params_dword[7]);
829 }
830 } else {
831 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
832 rc_range_params_dword[0]);
833 intel_de_write(dev_priv,
834 ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
835 rc_range_params_dword[1]);
836 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
837 rc_range_params_dword[2]);
838 intel_de_write(dev_priv,
839 ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
840 rc_range_params_dword[3]);
841 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
842 rc_range_params_dword[4]);
843 intel_de_write(dev_priv,
844 ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
845 rc_range_params_dword[5]);
846 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
847 rc_range_params_dword[6]);
848 intel_de_write(dev_priv,
849 ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
850 rc_range_params_dword[7]);
851 if (crtc_state->dsc.dsc_split) {
852 intel_de_write(dev_priv,
853 ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
854 rc_range_params_dword[0]);
855 intel_de_write(dev_priv,
856 ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
857 rc_range_params_dword[1]);
858 intel_de_write(dev_priv,
859 ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
860 rc_range_params_dword[2]);
861 intel_de_write(dev_priv,
862 ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
863 rc_range_params_dword[3]);
864 intel_de_write(dev_priv,
865 ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
866 rc_range_params_dword[4]);
867 intel_de_write(dev_priv,
868 ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
869 rc_range_params_dword[5]);
870 intel_de_write(dev_priv,
871 ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
872 rc_range_params_dword[6]);
873 intel_de_write(dev_priv,
874 ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
875 rc_range_params_dword[7]);
876 }
877 }
878 }
879
intel_dsc_dsi_pps_write(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)880 void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
881 const struct intel_crtc_state *crtc_state)
882 {
883 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
884 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
885 struct mipi_dsi_device *dsi;
886 struct drm_dsc_picture_parameter_set pps;
887 enum port port;
888
889 if (!crtc_state->dsc.compression_enable)
890 return;
891
892 drm_dsc_pps_payload_pack(&pps, vdsc_cfg);
893
894 for_each_dsi_port(port, intel_dsi->ports) {
895 dsi = intel_dsi->dsi_hosts[port]->device;
896
897 mipi_dsi_picture_parameter_set(dsi, &pps);
898 mipi_dsi_compression_mode(dsi, true);
899 }
900 }
901
intel_dsc_dp_pps_write(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)902 void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
903 const struct intel_crtc_state *crtc_state)
904 {
905 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
906 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
907 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
908
909 if (!crtc_state->dsc.compression_enable)
910 return;
911
912 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
913 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header);
914
915 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
916 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg);
917
918 dig_port->write_infoframe(encoder, crtc_state,
919 DP_SDP_PPS, &dp_dsc_pps_sdp,
920 sizeof(dp_dsc_pps_sdp));
921 }
922
dss_ctl1_reg(struct intel_crtc * crtc,enum transcoder cpu_transcoder)923 static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
924 {
925 return is_pipe_dsc(crtc, cpu_transcoder) ?
926 ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1;
927 }
928
dss_ctl2_reg(struct intel_crtc * crtc,enum transcoder cpu_transcoder)929 static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
930 {
931 return is_pipe_dsc(crtc, cpu_transcoder) ?
932 ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2;
933 }
934
intel_uncompressed_joiner_enable(const struct intel_crtc_state * crtc_state)935 void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
936 {
937 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
938 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
939 u32 dss_ctl1_val = 0;
940
941 if (crtc_state->bigjoiner_pipes && !crtc_state->dsc.compression_enable) {
942 if (intel_crtc_is_bigjoiner_slave(crtc_state))
943 dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE;
944 else
945 dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER;
946
947 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
948 }
949 }
950
intel_dsc_enable(const struct intel_crtc_state * crtc_state)951 void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
952 {
953 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
954 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
955 u32 dss_ctl1_val = 0;
956 u32 dss_ctl2_val = 0;
957
958 if (!crtc_state->dsc.compression_enable)
959 return;
960
961 intel_dsc_pps_configure(crtc_state);
962
963 dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
964 if (crtc_state->dsc.dsc_split) {
965 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
966 dss_ctl1_val |= JOINER_ENABLE;
967 }
968 if (crtc_state->bigjoiner_pipes) {
969 dss_ctl1_val |= BIG_JOINER_ENABLE;
970 if (!intel_crtc_is_bigjoiner_slave(crtc_state))
971 dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE;
972 }
973 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
974 intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);
975 }
976
intel_dsc_disable(const struct intel_crtc_state * old_crtc_state)977 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
978 {
979 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
980 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
981
982 /* Disable only if either of them is enabled */
983 if (old_crtc_state->dsc.compression_enable ||
984 old_crtc_state->bigjoiner_pipes) {
985 intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);
986 intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);
987 }
988 }
989
intel_dsc_get_config(struct intel_crtc_state * crtc_state)990 void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
991 {
992 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
993 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
994 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
995 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
996 enum pipe pipe = crtc->pipe;
997 enum intel_display_power_domain power_domain;
998 intel_wakeref_t wakeref;
999 u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0;
1000
1001 if (!intel_dsc_source_support(crtc_state))
1002 return;
1003
1004 power_domain = intel_dsc_power_domain(crtc, cpu_transcoder);
1005
1006 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1007 if (!wakeref)
1008 return;
1009
1010 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder));
1011 dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder));
1012
1013 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
1014 if (!crtc_state->dsc.compression_enable)
1015 goto out;
1016
1017 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
1018 (dss_ctl1 & JOINER_ENABLE);
1019
1020 /* FIXME: add more state readout as needed */
1021
1022 /* PPS0 & PPS1 */
1023 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
1024 pps1 = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
1025 } else {
1026 pps0 = intel_de_read(dev_priv,
1027 ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
1028 pps1 = intel_de_read(dev_priv,
1029 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
1030 }
1031
1032 vdsc_cfg->bits_per_pixel = pps1;
1033
1034 if (pps0 & DSC_NATIVE_420_ENABLE)
1035 vdsc_cfg->bits_per_pixel >>= 1;
1036
1037 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
1038 out:
1039 intel_display_power_put(dev_priv, power_domain, wakeref);
1040 }
1041