1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Intel I/OAT DMA Linux driver
4 * Copyright(c) 2004 - 2015 Intel Corporation.
5 */
6
7 #include <linux/init.h>
8 #include <linux/module.h>
9 #include <linux/slab.h>
10 #include <linux/pci.h>
11 #include <linux/interrupt.h>
12 #include <linux/dmaengine.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/workqueue.h>
16 #include <linux/prefetch.h>
17 #include <linux/dca.h>
18 #include <linux/sizes.h>
19 #include "dma.h"
20 #include "registers.h"
21 #include "hw.h"
22
23 #include "../dmaengine.h"
24
25 MODULE_VERSION(IOAT_DMA_VERSION);
26 MODULE_LICENSE("Dual BSD/GPL");
27 MODULE_AUTHOR("Intel Corporation");
28
29 static const struct pci_device_id ioat_pci_tbl[] = {
30 /* I/OAT v3 platforms */
31 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG0) },
32 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG1) },
33 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG2) },
34 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG3) },
35 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG4) },
36 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) },
37 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) },
38 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) },
39
40 /* I/OAT v3.2 platforms */
41 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF0) },
42 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF1) },
43 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF2) },
44 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF3) },
45 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF4) },
46 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF5) },
47 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF6) },
48 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF7) },
49 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF8) },
50 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF9) },
51
52 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB0) },
53 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB1) },
54 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB2) },
55 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB3) },
56 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB4) },
57 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB5) },
58 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB6) },
59 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB7) },
60 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8) },
61 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB9) },
62
63 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB0) },
64 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB1) },
65 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB2) },
66 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB3) },
67 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB4) },
68 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB5) },
69 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB6) },
70 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB7) },
71 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB8) },
72 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB9) },
73
74 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW0) },
75 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW1) },
76 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW2) },
77 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW3) },
78 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW4) },
79 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW5) },
80 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW6) },
81 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW7) },
82 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW8) },
83 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW9) },
84
85 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX0) },
86 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX1) },
87 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX2) },
88 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX3) },
89 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX4) },
90 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX5) },
91 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX6) },
92 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX7) },
93 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX8) },
94 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX9) },
95
96 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SKX) },
97
98 /* I/OAT v3.3 platforms */
99 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD0) },
100 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD1) },
101 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD2) },
102 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD3) },
103
104 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE0) },
105 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE1) },
106 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE2) },
107 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE3) },
108
109 /* I/OAT v3.4 platforms */
110 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_ICX) },
111
112 { 0, }
113 };
114 MODULE_DEVICE_TABLE(pci, ioat_pci_tbl);
115
116 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
117 static void ioat_remove(struct pci_dev *pdev);
118 static void
119 ioat_init_channel(struct ioatdma_device *ioat_dma,
120 struct ioatdma_chan *ioat_chan, int idx);
121 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma);
122 static void ioat_enumerate_channels(struct ioatdma_device *ioat_dma);
123 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma);
124
125 static int ioat_dca_enabled = 1;
126 module_param(ioat_dca_enabled, int, 0644);
127 MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)");
128 int ioat_pending_level = 7;
129 module_param(ioat_pending_level, int, 0644);
130 MODULE_PARM_DESC(ioat_pending_level,
131 "high-water mark for pushing ioat descriptors (default: 7)");
132 static char ioat_interrupt_style[32] = "msix";
133 module_param_string(ioat_interrupt_style, ioat_interrupt_style,
134 sizeof(ioat_interrupt_style), 0644);
135 MODULE_PARM_DESC(ioat_interrupt_style,
136 "set ioat interrupt style: msix (default), msi, intx");
137
138 struct kmem_cache *ioat_cache;
139 struct kmem_cache *ioat_sed_cache;
140
is_jf_ioat(struct pci_dev * pdev)141 static bool is_jf_ioat(struct pci_dev *pdev)
142 {
143 switch (pdev->device) {
144 case PCI_DEVICE_ID_INTEL_IOAT_JSF0:
145 case PCI_DEVICE_ID_INTEL_IOAT_JSF1:
146 case PCI_DEVICE_ID_INTEL_IOAT_JSF2:
147 case PCI_DEVICE_ID_INTEL_IOAT_JSF3:
148 case PCI_DEVICE_ID_INTEL_IOAT_JSF4:
149 case PCI_DEVICE_ID_INTEL_IOAT_JSF5:
150 case PCI_DEVICE_ID_INTEL_IOAT_JSF6:
151 case PCI_DEVICE_ID_INTEL_IOAT_JSF7:
152 case PCI_DEVICE_ID_INTEL_IOAT_JSF8:
153 case PCI_DEVICE_ID_INTEL_IOAT_JSF9:
154 return true;
155 default:
156 return false;
157 }
158 }
159
is_snb_ioat(struct pci_dev * pdev)160 static bool is_snb_ioat(struct pci_dev *pdev)
161 {
162 switch (pdev->device) {
163 case PCI_DEVICE_ID_INTEL_IOAT_SNB0:
164 case PCI_DEVICE_ID_INTEL_IOAT_SNB1:
165 case PCI_DEVICE_ID_INTEL_IOAT_SNB2:
166 case PCI_DEVICE_ID_INTEL_IOAT_SNB3:
167 case PCI_DEVICE_ID_INTEL_IOAT_SNB4:
168 case PCI_DEVICE_ID_INTEL_IOAT_SNB5:
169 case PCI_DEVICE_ID_INTEL_IOAT_SNB6:
170 case PCI_DEVICE_ID_INTEL_IOAT_SNB7:
171 case PCI_DEVICE_ID_INTEL_IOAT_SNB8:
172 case PCI_DEVICE_ID_INTEL_IOAT_SNB9:
173 return true;
174 default:
175 return false;
176 }
177 }
178
is_ivb_ioat(struct pci_dev * pdev)179 static bool is_ivb_ioat(struct pci_dev *pdev)
180 {
181 switch (pdev->device) {
182 case PCI_DEVICE_ID_INTEL_IOAT_IVB0:
183 case PCI_DEVICE_ID_INTEL_IOAT_IVB1:
184 case PCI_DEVICE_ID_INTEL_IOAT_IVB2:
185 case PCI_DEVICE_ID_INTEL_IOAT_IVB3:
186 case PCI_DEVICE_ID_INTEL_IOAT_IVB4:
187 case PCI_DEVICE_ID_INTEL_IOAT_IVB5:
188 case PCI_DEVICE_ID_INTEL_IOAT_IVB6:
189 case PCI_DEVICE_ID_INTEL_IOAT_IVB7:
190 case PCI_DEVICE_ID_INTEL_IOAT_IVB8:
191 case PCI_DEVICE_ID_INTEL_IOAT_IVB9:
192 return true;
193 default:
194 return false;
195 }
196
197 }
198
is_hsw_ioat(struct pci_dev * pdev)199 static bool is_hsw_ioat(struct pci_dev *pdev)
200 {
201 switch (pdev->device) {
202 case PCI_DEVICE_ID_INTEL_IOAT_HSW0:
203 case PCI_DEVICE_ID_INTEL_IOAT_HSW1:
204 case PCI_DEVICE_ID_INTEL_IOAT_HSW2:
205 case PCI_DEVICE_ID_INTEL_IOAT_HSW3:
206 case PCI_DEVICE_ID_INTEL_IOAT_HSW4:
207 case PCI_DEVICE_ID_INTEL_IOAT_HSW5:
208 case PCI_DEVICE_ID_INTEL_IOAT_HSW6:
209 case PCI_DEVICE_ID_INTEL_IOAT_HSW7:
210 case PCI_DEVICE_ID_INTEL_IOAT_HSW8:
211 case PCI_DEVICE_ID_INTEL_IOAT_HSW9:
212 return true;
213 default:
214 return false;
215 }
216
217 }
218
is_bdx_ioat(struct pci_dev * pdev)219 static bool is_bdx_ioat(struct pci_dev *pdev)
220 {
221 switch (pdev->device) {
222 case PCI_DEVICE_ID_INTEL_IOAT_BDX0:
223 case PCI_DEVICE_ID_INTEL_IOAT_BDX1:
224 case PCI_DEVICE_ID_INTEL_IOAT_BDX2:
225 case PCI_DEVICE_ID_INTEL_IOAT_BDX3:
226 case PCI_DEVICE_ID_INTEL_IOAT_BDX4:
227 case PCI_DEVICE_ID_INTEL_IOAT_BDX5:
228 case PCI_DEVICE_ID_INTEL_IOAT_BDX6:
229 case PCI_DEVICE_ID_INTEL_IOAT_BDX7:
230 case PCI_DEVICE_ID_INTEL_IOAT_BDX8:
231 case PCI_DEVICE_ID_INTEL_IOAT_BDX9:
232 return true;
233 default:
234 return false;
235 }
236 }
237
is_skx_ioat(struct pci_dev * pdev)238 static inline bool is_skx_ioat(struct pci_dev *pdev)
239 {
240 return (pdev->device == PCI_DEVICE_ID_INTEL_IOAT_SKX) ? true : false;
241 }
242
is_xeon_cb32(struct pci_dev * pdev)243 static bool is_xeon_cb32(struct pci_dev *pdev)
244 {
245 return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) ||
246 is_hsw_ioat(pdev) || is_bdx_ioat(pdev) || is_skx_ioat(pdev);
247 }
248
is_bwd_ioat(struct pci_dev * pdev)249 bool is_bwd_ioat(struct pci_dev *pdev)
250 {
251 switch (pdev->device) {
252 case PCI_DEVICE_ID_INTEL_IOAT_BWD0:
253 case PCI_DEVICE_ID_INTEL_IOAT_BWD1:
254 case PCI_DEVICE_ID_INTEL_IOAT_BWD2:
255 case PCI_DEVICE_ID_INTEL_IOAT_BWD3:
256 /* even though not Atom, BDX-DE has same DMA silicon */
257 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0:
258 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1:
259 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2:
260 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3:
261 return true;
262 default:
263 return false;
264 }
265 }
266
is_bwd_noraid(struct pci_dev * pdev)267 static bool is_bwd_noraid(struct pci_dev *pdev)
268 {
269 switch (pdev->device) {
270 case PCI_DEVICE_ID_INTEL_IOAT_BWD2:
271 case PCI_DEVICE_ID_INTEL_IOAT_BWD3:
272 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0:
273 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1:
274 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2:
275 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3:
276 return true;
277 default:
278 return false;
279 }
280
281 }
282
283 /*
284 * Perform a IOAT transaction to verify the HW works.
285 */
286 #define IOAT_TEST_SIZE 2000
287
ioat_dma_test_callback(void * dma_async_param)288 static void ioat_dma_test_callback(void *dma_async_param)
289 {
290 struct completion *cmp = dma_async_param;
291
292 complete(cmp);
293 }
294
295 /**
296 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
297 * @ioat_dma: dma device to be tested
298 */
ioat_dma_self_test(struct ioatdma_device * ioat_dma)299 static int ioat_dma_self_test(struct ioatdma_device *ioat_dma)
300 {
301 int i;
302 u8 *src;
303 u8 *dest;
304 struct dma_device *dma = &ioat_dma->dma_dev;
305 struct device *dev = &ioat_dma->pdev->dev;
306 struct dma_chan *dma_chan;
307 struct dma_async_tx_descriptor *tx;
308 dma_addr_t dma_dest, dma_src;
309 dma_cookie_t cookie;
310 int err = 0;
311 struct completion cmp;
312 unsigned long tmo;
313 unsigned long flags;
314
315 src = kzalloc(IOAT_TEST_SIZE, GFP_KERNEL);
316 if (!src)
317 return -ENOMEM;
318 dest = kzalloc(IOAT_TEST_SIZE, GFP_KERNEL);
319 if (!dest) {
320 kfree(src);
321 return -ENOMEM;
322 }
323
324 /* Fill in src buffer */
325 for (i = 0; i < IOAT_TEST_SIZE; i++)
326 src[i] = (u8)i;
327
328 /* Start copy, using first DMA channel */
329 dma_chan = container_of(dma->channels.next, struct dma_chan,
330 device_node);
331 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
332 dev_err(dev, "selftest cannot allocate chan resource\n");
333 err = -ENODEV;
334 goto out;
335 }
336
337 dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
338 if (dma_mapping_error(dev, dma_src)) {
339 dev_err(dev, "mapping src buffer failed\n");
340 err = -ENOMEM;
341 goto free_resources;
342 }
343 dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
344 if (dma_mapping_error(dev, dma_dest)) {
345 dev_err(dev, "mapping dest buffer failed\n");
346 err = -ENOMEM;
347 goto unmap_src;
348 }
349 flags = DMA_PREP_INTERRUPT;
350 tx = ioat_dma->dma_dev.device_prep_dma_memcpy(dma_chan, dma_dest,
351 dma_src, IOAT_TEST_SIZE,
352 flags);
353 if (!tx) {
354 dev_err(dev, "Self-test prep failed, disabling\n");
355 err = -ENODEV;
356 goto unmap_dma;
357 }
358
359 async_tx_ack(tx);
360 init_completion(&cmp);
361 tx->callback = ioat_dma_test_callback;
362 tx->callback_param = &cmp;
363 cookie = tx->tx_submit(tx);
364 if (cookie < 0) {
365 dev_err(dev, "Self-test setup failed, disabling\n");
366 err = -ENODEV;
367 goto unmap_dma;
368 }
369 dma->device_issue_pending(dma_chan);
370
371 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
372
373 if (tmo == 0 ||
374 dma->device_tx_status(dma_chan, cookie, NULL)
375 != DMA_COMPLETE) {
376 dev_err(dev, "Self-test copy timed out, disabling\n");
377 err = -ENODEV;
378 goto unmap_dma;
379 }
380 if (memcmp(src, dest, IOAT_TEST_SIZE)) {
381 dev_err(dev, "Self-test copy failed compare, disabling\n");
382 err = -ENODEV;
383 goto unmap_dma;
384 }
385
386 unmap_dma:
387 dma_unmap_single(dev, dma_dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
388 unmap_src:
389 dma_unmap_single(dev, dma_src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
390 free_resources:
391 dma->device_free_chan_resources(dma_chan);
392 out:
393 kfree(src);
394 kfree(dest);
395 return err;
396 }
397
398 /**
399 * ioat_dma_setup_interrupts - setup interrupt handler
400 * @ioat_dma: ioat dma device
401 */
ioat_dma_setup_interrupts(struct ioatdma_device * ioat_dma)402 int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma)
403 {
404 struct ioatdma_chan *ioat_chan;
405 struct pci_dev *pdev = ioat_dma->pdev;
406 struct device *dev = &pdev->dev;
407 struct msix_entry *msix;
408 int i, j, msixcnt;
409 int err = -EINVAL;
410 u8 intrctrl = 0;
411
412 if (!strcmp(ioat_interrupt_style, "msix"))
413 goto msix;
414 if (!strcmp(ioat_interrupt_style, "msi"))
415 goto msi;
416 if (!strcmp(ioat_interrupt_style, "intx"))
417 goto intx;
418 dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style);
419 goto err_no_irq;
420
421 msix:
422 /* The number of MSI-X vectors should equal the number of channels */
423 msixcnt = ioat_dma->chancnt;
424 for (i = 0; i < msixcnt; i++)
425 ioat_dma->msix_entries[i].entry = i;
426
427 err = pci_enable_msix_exact(pdev, ioat_dma->msix_entries, msixcnt);
428 if (err)
429 goto msi;
430
431 for (i = 0; i < msixcnt; i++) {
432 msix = &ioat_dma->msix_entries[i];
433 ioat_chan = ioat_chan_by_index(ioat_dma, i);
434 err = devm_request_irq(dev, msix->vector,
435 ioat_dma_do_interrupt_msix, 0,
436 "ioat-msix", ioat_chan);
437 if (err) {
438 for (j = 0; j < i; j++) {
439 msix = &ioat_dma->msix_entries[j];
440 ioat_chan = ioat_chan_by_index(ioat_dma, j);
441 devm_free_irq(dev, msix->vector, ioat_chan);
442 }
443 goto msi;
444 }
445 }
446 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
447 ioat_dma->irq_mode = IOAT_MSIX;
448 goto done;
449
450 msi:
451 err = pci_enable_msi(pdev);
452 if (err)
453 goto intx;
454
455 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0,
456 "ioat-msi", ioat_dma);
457 if (err) {
458 pci_disable_msi(pdev);
459 goto intx;
460 }
461 ioat_dma->irq_mode = IOAT_MSI;
462 goto done;
463
464 intx:
465 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt,
466 IRQF_SHARED, "ioat-intx", ioat_dma);
467 if (err)
468 goto err_no_irq;
469
470 ioat_dma->irq_mode = IOAT_INTX;
471 done:
472 if (is_bwd_ioat(pdev))
473 ioat_intr_quirk(ioat_dma);
474 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
475 writeb(intrctrl, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);
476 return 0;
477
478 err_no_irq:
479 /* Disable all interrupt generation */
480 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);
481 ioat_dma->irq_mode = IOAT_NOIRQ;
482 dev_err(dev, "no usable interrupts\n");
483 return err;
484 }
485
ioat_disable_interrupts(struct ioatdma_device * ioat_dma)486 static void ioat_disable_interrupts(struct ioatdma_device *ioat_dma)
487 {
488 /* Disable all interrupt generation */
489 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);
490 }
491
ioat_probe(struct ioatdma_device * ioat_dma)492 static int ioat_probe(struct ioatdma_device *ioat_dma)
493 {
494 int err = -ENODEV;
495 struct dma_device *dma = &ioat_dma->dma_dev;
496 struct pci_dev *pdev = ioat_dma->pdev;
497 struct device *dev = &pdev->dev;
498
499 ioat_dma->completion_pool = dma_pool_create("completion_pool", dev,
500 sizeof(u64),
501 SMP_CACHE_BYTES,
502 SMP_CACHE_BYTES);
503
504 if (!ioat_dma->completion_pool) {
505 err = -ENOMEM;
506 goto err_out;
507 }
508
509 ioat_enumerate_channels(ioat_dma);
510
511 dma_cap_set(DMA_MEMCPY, dma->cap_mask);
512 dma->dev = &pdev->dev;
513
514 if (!ioat_dma->chancnt) {
515 dev_err(dev, "channel enumeration error\n");
516 goto err_setup_interrupts;
517 }
518
519 err = ioat_dma_setup_interrupts(ioat_dma);
520 if (err)
521 goto err_setup_interrupts;
522
523 err = ioat3_dma_self_test(ioat_dma);
524 if (err)
525 goto err_self_test;
526
527 return 0;
528
529 err_self_test:
530 ioat_disable_interrupts(ioat_dma);
531 err_setup_interrupts:
532 dma_pool_destroy(ioat_dma->completion_pool);
533 err_out:
534 return err;
535 }
536
ioat_dma_remove(struct ioatdma_device * ioat_dma)537 static void ioat_dma_remove(struct ioatdma_device *ioat_dma)
538 {
539 struct dma_device *dma = &ioat_dma->dma_dev;
540
541 ioat_disable_interrupts(ioat_dma);
542
543 ioat_kobject_del(ioat_dma);
544
545 dma_async_device_unregister(dma);
546 }
547
548 /**
549 * ioat_enumerate_channels - find and initialize the device's channels
550 * @ioat_dma: the ioat dma device to be enumerated
551 */
ioat_enumerate_channels(struct ioatdma_device * ioat_dma)552 static void ioat_enumerate_channels(struct ioatdma_device *ioat_dma)
553 {
554 struct ioatdma_chan *ioat_chan;
555 struct device *dev = &ioat_dma->pdev->dev;
556 struct dma_device *dma = &ioat_dma->dma_dev;
557 u8 xfercap_log;
558 int chancnt;
559 int i;
560
561 INIT_LIST_HEAD(&dma->channels);
562 chancnt = readb(ioat_dma->reg_base + IOAT_CHANCNT_OFFSET);
563 chancnt &= 0x1f; /* bits [4:0] valid */
564 if (chancnt > ARRAY_SIZE(ioat_dma->idx)) {
565 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
566 chancnt, ARRAY_SIZE(ioat_dma->idx));
567 chancnt = ARRAY_SIZE(ioat_dma->idx);
568 }
569 xfercap_log = readb(ioat_dma->reg_base + IOAT_XFERCAP_OFFSET);
570 xfercap_log &= 0x1f; /* bits [4:0] valid */
571 if (xfercap_log == 0)
572 return;
573 dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log);
574
575 for (i = 0; i < chancnt; i++) {
576 ioat_chan = kzalloc(sizeof(*ioat_chan), GFP_KERNEL);
577 if (!ioat_chan)
578 break;
579
580 ioat_init_channel(ioat_dma, ioat_chan, i);
581 ioat_chan->xfercap_log = xfercap_log;
582 spin_lock_init(&ioat_chan->prep_lock);
583 if (ioat_reset_hw(ioat_chan)) {
584 i = 0;
585 break;
586 }
587 }
588 ioat_dma->chancnt = i;
589 }
590
591 /**
592 * ioat_free_chan_resources - release all the descriptors
593 * @c: the channel to be cleaned
594 */
ioat_free_chan_resources(struct dma_chan * c)595 static void ioat_free_chan_resources(struct dma_chan *c)
596 {
597 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
598 struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma;
599 struct ioat_ring_ent *desc;
600 const int total_descs = 1 << ioat_chan->alloc_order;
601 int descs;
602 int i;
603
604 /* Before freeing channel resources first check
605 * if they have been previously allocated for this channel.
606 */
607 if (!ioat_chan->ring)
608 return;
609
610 ioat_stop(ioat_chan);
611
612 if (!test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) {
613 ioat_reset_hw(ioat_chan);
614
615 /* Put LTR to idle */
616 if (ioat_dma->version >= IOAT_VER_3_4)
617 writeb(IOAT_CHAN_LTR_SWSEL_IDLE,
618 ioat_chan->reg_base +
619 IOAT_CHAN_LTR_SWSEL_OFFSET);
620 }
621
622 spin_lock_bh(&ioat_chan->cleanup_lock);
623 spin_lock_bh(&ioat_chan->prep_lock);
624 descs = ioat_ring_space(ioat_chan);
625 dev_dbg(to_dev(ioat_chan), "freeing %d idle descriptors\n", descs);
626 for (i = 0; i < descs; i++) {
627 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head + i);
628 ioat_free_ring_ent(desc, c);
629 }
630
631 if (descs < total_descs)
632 dev_err(to_dev(ioat_chan), "Freeing %d in use descriptors!\n",
633 total_descs - descs);
634
635 for (i = 0; i < total_descs - descs; i++) {
636 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail + i);
637 dump_desc_dbg(ioat_chan, desc);
638 ioat_free_ring_ent(desc, c);
639 }
640
641 for (i = 0; i < ioat_chan->desc_chunks; i++) {
642 dma_free_coherent(to_dev(ioat_chan), IOAT_CHUNK_SIZE,
643 ioat_chan->descs[i].virt,
644 ioat_chan->descs[i].hw);
645 ioat_chan->descs[i].virt = NULL;
646 ioat_chan->descs[i].hw = 0;
647 }
648 ioat_chan->desc_chunks = 0;
649
650 kfree(ioat_chan->ring);
651 ioat_chan->ring = NULL;
652 ioat_chan->alloc_order = 0;
653 dma_pool_free(ioat_dma->completion_pool, ioat_chan->completion,
654 ioat_chan->completion_dma);
655 spin_unlock_bh(&ioat_chan->prep_lock);
656 spin_unlock_bh(&ioat_chan->cleanup_lock);
657
658 ioat_chan->last_completion = 0;
659 ioat_chan->completion_dma = 0;
660 ioat_chan->dmacount = 0;
661 }
662
663 /* ioat_alloc_chan_resources - allocate/initialize ioat descriptor ring
664 * @chan: channel to be initialized
665 */
ioat_alloc_chan_resources(struct dma_chan * c)666 static int ioat_alloc_chan_resources(struct dma_chan *c)
667 {
668 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
669 struct ioat_ring_ent **ring;
670 u64 status;
671 int order;
672 int i = 0;
673 u32 chanerr;
674
675 /* have we already been set up? */
676 if (ioat_chan->ring)
677 return 1 << ioat_chan->alloc_order;
678
679 /* Setup register to interrupt and write completion status on error */
680 writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET);
681
682 /* allocate a completion writeback area */
683 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
684 ioat_chan->completion =
685 dma_pool_zalloc(ioat_chan->ioat_dma->completion_pool,
686 GFP_NOWAIT, &ioat_chan->completion_dma);
687 if (!ioat_chan->completion)
688 return -ENOMEM;
689
690 writel(((u64)ioat_chan->completion_dma) & 0x00000000FFFFFFFF,
691 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
692 writel(((u64)ioat_chan->completion_dma) >> 32,
693 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
694
695 order = IOAT_MAX_ORDER;
696 ring = ioat_alloc_ring(c, order, GFP_NOWAIT);
697 if (!ring)
698 return -ENOMEM;
699
700 spin_lock_bh(&ioat_chan->cleanup_lock);
701 spin_lock_bh(&ioat_chan->prep_lock);
702 ioat_chan->ring = ring;
703 ioat_chan->head = 0;
704 ioat_chan->issued = 0;
705 ioat_chan->tail = 0;
706 ioat_chan->alloc_order = order;
707 set_bit(IOAT_RUN, &ioat_chan->state);
708 spin_unlock_bh(&ioat_chan->prep_lock);
709 spin_unlock_bh(&ioat_chan->cleanup_lock);
710
711 /* Setting up LTR values for 3.4 or later */
712 if (ioat_chan->ioat_dma->version >= IOAT_VER_3_4) {
713 u32 lat_val;
714
715 lat_val = IOAT_CHAN_LTR_ACTIVE_SNVAL |
716 IOAT_CHAN_LTR_ACTIVE_SNLATSCALE |
717 IOAT_CHAN_LTR_ACTIVE_SNREQMNT;
718 writel(lat_val, ioat_chan->reg_base +
719 IOAT_CHAN_LTR_ACTIVE_OFFSET);
720
721 lat_val = IOAT_CHAN_LTR_IDLE_SNVAL |
722 IOAT_CHAN_LTR_IDLE_SNLATSCALE |
723 IOAT_CHAN_LTR_IDLE_SNREQMNT;
724 writel(lat_val, ioat_chan->reg_base +
725 IOAT_CHAN_LTR_IDLE_OFFSET);
726
727 /* Select to active */
728 writeb(IOAT_CHAN_LTR_SWSEL_ACTIVE,
729 ioat_chan->reg_base +
730 IOAT_CHAN_LTR_SWSEL_OFFSET);
731 }
732
733 ioat_start_null_desc(ioat_chan);
734
735 /* check that we got off the ground */
736 do {
737 udelay(1);
738 status = ioat_chansts(ioat_chan);
739 } while (i++ < 20 && !is_ioat_active(status) && !is_ioat_idle(status));
740
741 if (is_ioat_active(status) || is_ioat_idle(status))
742 return 1 << ioat_chan->alloc_order;
743
744 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
745
746 dev_WARN(to_dev(ioat_chan),
747 "failed to start channel chanerr: %#x\n", chanerr);
748 ioat_free_chan_resources(c);
749 return -EFAULT;
750 }
751
752 /* common channel initialization */
753 static void
ioat_init_channel(struct ioatdma_device * ioat_dma,struct ioatdma_chan * ioat_chan,int idx)754 ioat_init_channel(struct ioatdma_device *ioat_dma,
755 struct ioatdma_chan *ioat_chan, int idx)
756 {
757 struct dma_device *dma = &ioat_dma->dma_dev;
758
759 ioat_chan->ioat_dma = ioat_dma;
760 ioat_chan->reg_base = ioat_dma->reg_base + (0x80 * (idx + 1));
761 spin_lock_init(&ioat_chan->cleanup_lock);
762 ioat_chan->dma_chan.device = dma;
763 dma_cookie_init(&ioat_chan->dma_chan);
764 list_add_tail(&ioat_chan->dma_chan.device_node, &dma->channels);
765 ioat_dma->idx[idx] = ioat_chan;
766 timer_setup(&ioat_chan->timer, ioat_timer_event, 0);
767 tasklet_setup(&ioat_chan->cleanup_task, ioat_cleanup_event);
768 }
769
770 #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */
ioat_xor_val_self_test(struct ioatdma_device * ioat_dma)771 static int ioat_xor_val_self_test(struct ioatdma_device *ioat_dma)
772 {
773 int i, src_idx;
774 struct page *dest;
775 struct page *xor_srcs[IOAT_NUM_SRC_TEST];
776 struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1];
777 dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1];
778 dma_addr_t dest_dma;
779 struct dma_async_tx_descriptor *tx;
780 struct dma_chan *dma_chan;
781 dma_cookie_t cookie;
782 u8 cmp_byte = 0;
783 u32 cmp_word;
784 u32 xor_val_result;
785 int err = 0;
786 struct completion cmp;
787 unsigned long tmo;
788 struct device *dev = &ioat_dma->pdev->dev;
789 struct dma_device *dma = &ioat_dma->dma_dev;
790 u8 op = 0;
791
792 dev_dbg(dev, "%s\n", __func__);
793
794 if (!dma_has_cap(DMA_XOR, dma->cap_mask))
795 return 0;
796
797 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
798 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
799 if (!xor_srcs[src_idx]) {
800 while (src_idx--)
801 __free_page(xor_srcs[src_idx]);
802 return -ENOMEM;
803 }
804 }
805
806 dest = alloc_page(GFP_KERNEL);
807 if (!dest) {
808 while (src_idx--)
809 __free_page(xor_srcs[src_idx]);
810 return -ENOMEM;
811 }
812
813 /* Fill in src buffers */
814 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
815 u8 *ptr = page_address(xor_srcs[src_idx]);
816
817 for (i = 0; i < PAGE_SIZE; i++)
818 ptr[i] = (1 << src_idx);
819 }
820
821 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++)
822 cmp_byte ^= (u8) (1 << src_idx);
823
824 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
825 (cmp_byte << 8) | cmp_byte;
826
827 memset(page_address(dest), 0, PAGE_SIZE);
828
829 dma_chan = container_of(dma->channels.next, struct dma_chan,
830 device_node);
831 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
832 err = -ENODEV;
833 goto out;
834 }
835
836 /* test xor */
837 op = IOAT_OP_XOR;
838
839 dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE);
840 if (dma_mapping_error(dev, dest_dma)) {
841 err = -ENOMEM;
842 goto free_resources;
843 }
844
845 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) {
846 dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE,
847 DMA_TO_DEVICE);
848 if (dma_mapping_error(dev, dma_srcs[i])) {
849 err = -ENOMEM;
850 goto dma_unmap;
851 }
852 }
853 tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
854 IOAT_NUM_SRC_TEST, PAGE_SIZE,
855 DMA_PREP_INTERRUPT);
856
857 if (!tx) {
858 dev_err(dev, "Self-test xor prep failed\n");
859 err = -ENODEV;
860 goto dma_unmap;
861 }
862
863 async_tx_ack(tx);
864 init_completion(&cmp);
865 tx->callback = ioat_dma_test_callback;
866 tx->callback_param = &cmp;
867 cookie = tx->tx_submit(tx);
868 if (cookie < 0) {
869 dev_err(dev, "Self-test xor setup failed\n");
870 err = -ENODEV;
871 goto dma_unmap;
872 }
873 dma->device_issue_pending(dma_chan);
874
875 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
876
877 if (tmo == 0 ||
878 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
879 dev_err(dev, "Self-test xor timed out\n");
880 err = -ENODEV;
881 goto dma_unmap;
882 }
883
884 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
885 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
886
887 dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
888 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
889 u32 *ptr = page_address(dest);
890
891 if (ptr[i] != cmp_word) {
892 dev_err(dev, "Self-test xor failed compare\n");
893 err = -ENODEV;
894 goto free_resources;
895 }
896 }
897 dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
898
899 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
900
901 /* skip validate if the capability is not present */
902 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask))
903 goto free_resources;
904
905 op = IOAT_OP_XOR_VAL;
906
907 /* validate the sources with the destintation page */
908 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
909 xor_val_srcs[i] = xor_srcs[i];
910 xor_val_srcs[i] = dest;
911
912 xor_val_result = 1;
913
914 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) {
915 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
916 DMA_TO_DEVICE);
917 if (dma_mapping_error(dev, dma_srcs[i])) {
918 err = -ENOMEM;
919 goto dma_unmap;
920 }
921 }
922 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
923 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
924 &xor_val_result, DMA_PREP_INTERRUPT);
925 if (!tx) {
926 dev_err(dev, "Self-test zero prep failed\n");
927 err = -ENODEV;
928 goto dma_unmap;
929 }
930
931 async_tx_ack(tx);
932 init_completion(&cmp);
933 tx->callback = ioat_dma_test_callback;
934 tx->callback_param = &cmp;
935 cookie = tx->tx_submit(tx);
936 if (cookie < 0) {
937 dev_err(dev, "Self-test zero setup failed\n");
938 err = -ENODEV;
939 goto dma_unmap;
940 }
941 dma->device_issue_pending(dma_chan);
942
943 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
944
945 if (tmo == 0 ||
946 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
947 dev_err(dev, "Self-test validate timed out\n");
948 err = -ENODEV;
949 goto dma_unmap;
950 }
951
952 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
953 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
954
955 if (xor_val_result != 0) {
956 dev_err(dev, "Self-test validate failed compare\n");
957 err = -ENODEV;
958 goto free_resources;
959 }
960
961 memset(page_address(dest), 0, PAGE_SIZE);
962
963 /* test for non-zero parity sum */
964 op = IOAT_OP_XOR_VAL;
965
966 xor_val_result = 0;
967 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) {
968 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
969 DMA_TO_DEVICE);
970 if (dma_mapping_error(dev, dma_srcs[i])) {
971 err = -ENOMEM;
972 goto dma_unmap;
973 }
974 }
975 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
976 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
977 &xor_val_result, DMA_PREP_INTERRUPT);
978 if (!tx) {
979 dev_err(dev, "Self-test 2nd zero prep failed\n");
980 err = -ENODEV;
981 goto dma_unmap;
982 }
983
984 async_tx_ack(tx);
985 init_completion(&cmp);
986 tx->callback = ioat_dma_test_callback;
987 tx->callback_param = &cmp;
988 cookie = tx->tx_submit(tx);
989 if (cookie < 0) {
990 dev_err(dev, "Self-test 2nd zero setup failed\n");
991 err = -ENODEV;
992 goto dma_unmap;
993 }
994 dma->device_issue_pending(dma_chan);
995
996 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
997
998 if (tmo == 0 ||
999 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
1000 dev_err(dev, "Self-test 2nd validate timed out\n");
1001 err = -ENODEV;
1002 goto dma_unmap;
1003 }
1004
1005 if (xor_val_result != SUM_CHECK_P_RESULT) {
1006 dev_err(dev, "Self-test validate failed compare\n");
1007 err = -ENODEV;
1008 goto dma_unmap;
1009 }
1010
1011 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1012 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
1013
1014 goto free_resources;
1015 dma_unmap:
1016 if (op == IOAT_OP_XOR) {
1017 while (--i >= 0)
1018 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE,
1019 DMA_TO_DEVICE);
1020 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
1021 } else if (op == IOAT_OP_XOR_VAL) {
1022 while (--i >= 0)
1023 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE,
1024 DMA_TO_DEVICE);
1025 }
1026 free_resources:
1027 dma->device_free_chan_resources(dma_chan);
1028 out:
1029 src_idx = IOAT_NUM_SRC_TEST;
1030 while (src_idx--)
1031 __free_page(xor_srcs[src_idx]);
1032 __free_page(dest);
1033 return err;
1034 }
1035
ioat3_dma_self_test(struct ioatdma_device * ioat_dma)1036 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma)
1037 {
1038 int rc;
1039
1040 rc = ioat_dma_self_test(ioat_dma);
1041 if (rc)
1042 return rc;
1043
1044 rc = ioat_xor_val_self_test(ioat_dma);
1045
1046 return rc;
1047 }
1048
ioat_intr_quirk(struct ioatdma_device * ioat_dma)1049 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma)
1050 {
1051 struct dma_device *dma;
1052 struct dma_chan *c;
1053 struct ioatdma_chan *ioat_chan;
1054 u32 errmask;
1055
1056 dma = &ioat_dma->dma_dev;
1057
1058 /*
1059 * if we have descriptor write back error status, we mask the
1060 * error interrupts
1061 */
1062 if (ioat_dma->cap & IOAT_CAP_DWBES) {
1063 list_for_each_entry(c, &dma->channels, device_node) {
1064 ioat_chan = to_ioat_chan(c);
1065 errmask = readl(ioat_chan->reg_base +
1066 IOAT_CHANERR_MASK_OFFSET);
1067 errmask |= IOAT_CHANERR_XOR_P_OR_CRC_ERR |
1068 IOAT_CHANERR_XOR_Q_ERR;
1069 writel(errmask, ioat_chan->reg_base +
1070 IOAT_CHANERR_MASK_OFFSET);
1071 }
1072 }
1073 }
1074
ioat3_dma_probe(struct ioatdma_device * ioat_dma,int dca)1075 static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca)
1076 {
1077 struct pci_dev *pdev = ioat_dma->pdev;
1078 int dca_en = system_has_dca_enabled(pdev);
1079 struct dma_device *dma;
1080 struct dma_chan *c;
1081 struct ioatdma_chan *ioat_chan;
1082 int err;
1083 u16 val16;
1084
1085 dma = &ioat_dma->dma_dev;
1086 dma->device_prep_dma_memcpy = ioat_dma_prep_memcpy_lock;
1087 dma->device_issue_pending = ioat_issue_pending;
1088 dma->device_alloc_chan_resources = ioat_alloc_chan_resources;
1089 dma->device_free_chan_resources = ioat_free_chan_resources;
1090
1091 dma_cap_set(DMA_INTERRUPT, dma->cap_mask);
1092 dma->device_prep_dma_interrupt = ioat_prep_interrupt_lock;
1093
1094 ioat_dma->cap = readl(ioat_dma->reg_base + IOAT_DMA_CAP_OFFSET);
1095
1096 if (is_xeon_cb32(pdev) || is_bwd_noraid(pdev))
1097 ioat_dma->cap &=
1098 ~(IOAT_CAP_XOR | IOAT_CAP_PQ | IOAT_CAP_RAID16SS);
1099
1100 /* dca is incompatible with raid operations */
1101 if (dca_en && (ioat_dma->cap & (IOAT_CAP_XOR|IOAT_CAP_PQ)))
1102 ioat_dma->cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ);
1103
1104 if (ioat_dma->cap & IOAT_CAP_XOR) {
1105 dma->max_xor = 8;
1106
1107 dma_cap_set(DMA_XOR, dma->cap_mask);
1108 dma->device_prep_dma_xor = ioat_prep_xor;
1109
1110 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1111 dma->device_prep_dma_xor_val = ioat_prep_xor_val;
1112 }
1113
1114 if (ioat_dma->cap & IOAT_CAP_PQ) {
1115
1116 dma->device_prep_dma_pq = ioat_prep_pq;
1117 dma->device_prep_dma_pq_val = ioat_prep_pq_val;
1118 dma_cap_set(DMA_PQ, dma->cap_mask);
1119 dma_cap_set(DMA_PQ_VAL, dma->cap_mask);
1120
1121 if (ioat_dma->cap & IOAT_CAP_RAID16SS)
1122 dma_set_maxpq(dma, 16, 0);
1123 else
1124 dma_set_maxpq(dma, 8, 0);
1125
1126 if (!(ioat_dma->cap & IOAT_CAP_XOR)) {
1127 dma->device_prep_dma_xor = ioat_prep_pqxor;
1128 dma->device_prep_dma_xor_val = ioat_prep_pqxor_val;
1129 dma_cap_set(DMA_XOR, dma->cap_mask);
1130 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1131
1132 if (ioat_dma->cap & IOAT_CAP_RAID16SS)
1133 dma->max_xor = 16;
1134 else
1135 dma->max_xor = 8;
1136 }
1137 }
1138
1139 dma->device_tx_status = ioat_tx_status;
1140
1141 /* starting with CB3.3 super extended descriptors are supported */
1142 if (ioat_dma->cap & IOAT_CAP_RAID16SS) {
1143 char pool_name[14];
1144 int i;
1145
1146 for (i = 0; i < MAX_SED_POOLS; i++) {
1147 snprintf(pool_name, 14, "ioat_hw%d_sed", i);
1148
1149 /* allocate SED DMA pool */
1150 ioat_dma->sed_hw_pool[i] = dmam_pool_create(pool_name,
1151 &pdev->dev,
1152 SED_SIZE * (i + 1), 64, 0);
1153 if (!ioat_dma->sed_hw_pool[i])
1154 return -ENOMEM;
1155
1156 }
1157 }
1158
1159 if (!(ioat_dma->cap & (IOAT_CAP_XOR | IOAT_CAP_PQ)))
1160 dma_cap_set(DMA_PRIVATE, dma->cap_mask);
1161
1162 err = ioat_probe(ioat_dma);
1163 if (err)
1164 return err;
1165
1166 list_for_each_entry(c, &dma->channels, device_node) {
1167 ioat_chan = to_ioat_chan(c);
1168 writel(IOAT_DMA_DCA_ANY_CPU,
1169 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET);
1170 }
1171
1172 err = dma_async_device_register(&ioat_dma->dma_dev);
1173 if (err)
1174 goto err_disable_interrupts;
1175
1176 ioat_kobject_add(ioat_dma, &ioat_ktype);
1177
1178 if (dca)
1179 ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base);
1180
1181 /* disable relaxed ordering */
1182 err = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &val16);
1183 if (err) {
1184 err = pcibios_err_to_errno(err);
1185 goto err_disable_interrupts;
1186 }
1187
1188 /* clear relaxed ordering enable */
1189 val16 &= ~PCI_EXP_DEVCTL_RELAX_EN;
1190 err = pcie_capability_write_word(pdev, PCI_EXP_DEVCTL, val16);
1191 if (err) {
1192 err = pcibios_err_to_errno(err);
1193 goto err_disable_interrupts;
1194 }
1195
1196 if (ioat_dma->cap & IOAT_CAP_DPS)
1197 writeb(ioat_pending_level + 1,
1198 ioat_dma->reg_base + IOAT_PREFETCH_LIMIT_OFFSET);
1199
1200 return 0;
1201
1202 err_disable_interrupts:
1203 ioat_disable_interrupts(ioat_dma);
1204 dma_pool_destroy(ioat_dma->completion_pool);
1205 return err;
1206 }
1207
ioat_shutdown(struct pci_dev * pdev)1208 static void ioat_shutdown(struct pci_dev *pdev)
1209 {
1210 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev);
1211 struct ioatdma_chan *ioat_chan;
1212 int i;
1213
1214 if (!ioat_dma)
1215 return;
1216
1217 for (i = 0; i < IOAT_MAX_CHANS; i++) {
1218 ioat_chan = ioat_dma->idx[i];
1219 if (!ioat_chan)
1220 continue;
1221
1222 spin_lock_bh(&ioat_chan->prep_lock);
1223 set_bit(IOAT_CHAN_DOWN, &ioat_chan->state);
1224 spin_unlock_bh(&ioat_chan->prep_lock);
1225 /*
1226 * Synchronization rule for del_timer_sync():
1227 * - The caller must not hold locks which would prevent
1228 * completion of the timer's handler.
1229 * So prep_lock cannot be held before calling it.
1230 */
1231 del_timer_sync(&ioat_chan->timer);
1232
1233 /* this should quiesce then reset */
1234 ioat_reset_hw(ioat_chan);
1235 }
1236
1237 ioat_disable_interrupts(ioat_dma);
1238 }
1239
ioat_resume(struct ioatdma_device * ioat_dma)1240 static void ioat_resume(struct ioatdma_device *ioat_dma)
1241 {
1242 struct ioatdma_chan *ioat_chan;
1243 u32 chanerr;
1244 int i;
1245
1246 for (i = 0; i < IOAT_MAX_CHANS; i++) {
1247 ioat_chan = ioat_dma->idx[i];
1248 if (!ioat_chan)
1249 continue;
1250
1251 spin_lock_bh(&ioat_chan->prep_lock);
1252 clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state);
1253 spin_unlock_bh(&ioat_chan->prep_lock);
1254
1255 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
1256 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
1257
1258 /* no need to reset as shutdown already did that */
1259 }
1260 }
1261
1262 #define DRV_NAME "ioatdma"
1263
ioat_pcie_error_detected(struct pci_dev * pdev,pci_channel_state_t error)1264 static pci_ers_result_t ioat_pcie_error_detected(struct pci_dev *pdev,
1265 pci_channel_state_t error)
1266 {
1267 dev_dbg(&pdev->dev, "%s: PCIe AER error %d\n", DRV_NAME, error);
1268
1269 /* quiesce and block I/O */
1270 ioat_shutdown(pdev);
1271
1272 return PCI_ERS_RESULT_NEED_RESET;
1273 }
1274
ioat_pcie_error_slot_reset(struct pci_dev * pdev)1275 static pci_ers_result_t ioat_pcie_error_slot_reset(struct pci_dev *pdev)
1276 {
1277 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
1278
1279 dev_dbg(&pdev->dev, "%s post reset handling\n", DRV_NAME);
1280
1281 if (pci_enable_device_mem(pdev) < 0) {
1282 dev_err(&pdev->dev,
1283 "Failed to enable PCIe device after reset.\n");
1284 result = PCI_ERS_RESULT_DISCONNECT;
1285 } else {
1286 pci_set_master(pdev);
1287 pci_restore_state(pdev);
1288 pci_save_state(pdev);
1289 pci_wake_from_d3(pdev, false);
1290 }
1291
1292 return result;
1293 }
1294
ioat_pcie_error_resume(struct pci_dev * pdev)1295 static void ioat_pcie_error_resume(struct pci_dev *pdev)
1296 {
1297 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev);
1298
1299 dev_dbg(&pdev->dev, "%s: AER handling resuming\n", DRV_NAME);
1300
1301 /* initialize and bring everything back */
1302 ioat_resume(ioat_dma);
1303 }
1304
1305 static const struct pci_error_handlers ioat_err_handler = {
1306 .error_detected = ioat_pcie_error_detected,
1307 .slot_reset = ioat_pcie_error_slot_reset,
1308 .resume = ioat_pcie_error_resume,
1309 };
1310
1311 static struct pci_driver ioat_pci_driver = {
1312 .name = DRV_NAME,
1313 .id_table = ioat_pci_tbl,
1314 .probe = ioat_pci_probe,
1315 .remove = ioat_remove,
1316 .shutdown = ioat_shutdown,
1317 .err_handler = &ioat_err_handler,
1318 };
1319
release_ioatdma(struct dma_device * device)1320 static void release_ioatdma(struct dma_device *device)
1321 {
1322 struct ioatdma_device *d = to_ioatdma_device(device);
1323 int i;
1324
1325 for (i = 0; i < IOAT_MAX_CHANS; i++)
1326 kfree(d->idx[i]);
1327
1328 dma_pool_destroy(d->completion_pool);
1329 kfree(d);
1330 }
1331
1332 static struct ioatdma_device *
alloc_ioatdma(struct pci_dev * pdev,void __iomem * iobase)1333 alloc_ioatdma(struct pci_dev *pdev, void __iomem *iobase)
1334 {
1335 struct ioatdma_device *d = kzalloc(sizeof(*d), GFP_KERNEL);
1336
1337 if (!d)
1338 return NULL;
1339 d->pdev = pdev;
1340 d->reg_base = iobase;
1341 d->dma_dev.device_release = release_ioatdma;
1342 return d;
1343 }
1344
ioat_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)1345 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1346 {
1347 void __iomem * const *iomap;
1348 struct device *dev = &pdev->dev;
1349 struct ioatdma_device *device;
1350 unsigned int i;
1351 u8 version;
1352 int err;
1353
1354 err = pcim_enable_device(pdev);
1355 if (err)
1356 return err;
1357
1358 err = pcim_iomap_regions(pdev, 1 << IOAT_MMIO_BAR, DRV_NAME);
1359 if (err)
1360 return err;
1361 iomap = pcim_iomap_table(pdev);
1362 if (!iomap)
1363 return -ENOMEM;
1364
1365 version = readb(iomap[IOAT_MMIO_BAR] + IOAT_VER_OFFSET);
1366 if (version < IOAT_VER_3_0)
1367 return -ENODEV;
1368
1369 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1370 if (err)
1371 return err;
1372
1373 device = alloc_ioatdma(pdev, iomap[IOAT_MMIO_BAR]);
1374 if (!device)
1375 return -ENOMEM;
1376 pci_set_master(pdev);
1377 pci_set_drvdata(pdev, device);
1378
1379 device->version = version;
1380 if (device->version >= IOAT_VER_3_4)
1381 ioat_dca_enabled = 0;
1382
1383 if (is_skx_ioat(pdev))
1384 device->version = IOAT_VER_3_2;
1385
1386 err = ioat3_dma_probe(device, ioat_dca_enabled);
1387 if (err) {
1388 for (i = 0; i < IOAT_MAX_CHANS; i++)
1389 kfree(device->idx[i]);
1390 kfree(device);
1391 dev_err(dev, "Intel(R) I/OAT DMA Engine init failed\n");
1392 return -ENODEV;
1393 }
1394
1395 return 0;
1396 }
1397
ioat_remove(struct pci_dev * pdev)1398 static void ioat_remove(struct pci_dev *pdev)
1399 {
1400 struct ioatdma_device *device = pci_get_drvdata(pdev);
1401
1402 if (!device)
1403 return;
1404
1405 ioat_shutdown(pdev);
1406
1407 dev_err(&pdev->dev, "Removing dma and dca services\n");
1408 if (device->dca) {
1409 unregister_dca_provider(device->dca, &pdev->dev);
1410 free_dca_provider(device->dca);
1411 device->dca = NULL;
1412 }
1413
1414 ioat_dma_remove(device);
1415 }
1416
ioat_init_module(void)1417 static int __init ioat_init_module(void)
1418 {
1419 int err = -ENOMEM;
1420
1421 pr_info("%s: Intel(R) QuickData Technology Driver %s\n",
1422 DRV_NAME, IOAT_DMA_VERSION);
1423
1424 ioat_cache = kmem_cache_create("ioat", sizeof(struct ioat_ring_ent),
1425 0, SLAB_HWCACHE_ALIGN, NULL);
1426 if (!ioat_cache)
1427 return -ENOMEM;
1428
1429 ioat_sed_cache = KMEM_CACHE(ioat_sed_ent, 0);
1430 if (!ioat_sed_cache)
1431 goto err_ioat_cache;
1432
1433 err = pci_register_driver(&ioat_pci_driver);
1434 if (err)
1435 goto err_ioat3_cache;
1436
1437 return 0;
1438
1439 err_ioat3_cache:
1440 kmem_cache_destroy(ioat_sed_cache);
1441
1442 err_ioat_cache:
1443 kmem_cache_destroy(ioat_cache);
1444
1445 return err;
1446 }
1447 module_init(ioat_init_module);
1448
ioat_exit_module(void)1449 static void __exit ioat_exit_module(void)
1450 {
1451 pci_unregister_driver(&ioat_pci_driver);
1452 kmem_cache_destroy(ioat_sed_cache);
1453 kmem_cache_destroy(ioat_cache);
1454 }
1455 module_exit(ioat_exit_module);
1456