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1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2012,2013 - ARM Ltd
4  * Author: Marc Zyngier <marc.zyngier@arm.com>
5  *
6  * Derived from arch/arm/kvm/coproc.c:
7  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8  * Authors: Rusty Russell <rusty@rustcorp.com.au>
9  *          Christoffer Dall <c.dall@virtualopensystems.com>
10  */
11 
12 #include <linux/bitfield.h>
13 #include <linux/bsearch.h>
14 #include <linux/cacheinfo.h>
15 #include <linux/kvm_host.h>
16 #include <linux/mm.h>
17 #include <linux/printk.h>
18 #include <linux/uaccess.h>
19 
20 #include <asm/cacheflush.h>
21 #include <asm/cputype.h>
22 #include <asm/debug-monitors.h>
23 #include <asm/esr.h>
24 #include <asm/kvm_arm.h>
25 #include <asm/kvm_emulate.h>
26 #include <asm/kvm_hyp.h>
27 #include <asm/kvm_mmu.h>
28 #include <asm/kvm_nested.h>
29 #include <asm/perf_event.h>
30 #include <asm/sysreg.h>
31 
32 #include <trace/events/kvm.h>
33 
34 #include "sys_regs.h"
35 #include "vgic/vgic.h"
36 
37 #include "trace.h"
38 
39 /*
40  * For AArch32, we only take care of what is being trapped. Anything
41  * that has to do with init and userspace access has to go via the
42  * 64bit interface.
43  */
44 
45 static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
46 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
47 		      u64 val);
48 
read_from_write_only(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)49 static bool read_from_write_only(struct kvm_vcpu *vcpu,
50 				 struct sys_reg_params *params,
51 				 const struct sys_reg_desc *r)
52 {
53 	WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n");
54 	print_sys_reg_instr(params);
55 	kvm_inject_undefined(vcpu);
56 	return false;
57 }
58 
write_to_read_only(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)59 static bool write_to_read_only(struct kvm_vcpu *vcpu,
60 			       struct sys_reg_params *params,
61 			       const struct sys_reg_desc *r)
62 {
63 	WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n");
64 	print_sys_reg_instr(params);
65 	kvm_inject_undefined(vcpu);
66 	return false;
67 }
68 
69 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
70 #define CSSELR_MAX 14
71 
72 /*
73  * Returns the minimum line size for the selected cache, expressed as
74  * Log2(bytes).
75  */
get_min_cache_line_size(bool icache)76 static u8 get_min_cache_line_size(bool icache)
77 {
78 	u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0);
79 	u8 field;
80 
81 	if (icache)
82 		field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr);
83 	else
84 		field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr);
85 
86 	/*
87 	 * Cache line size is represented as Log2(words) in CTR_EL0.
88 	 * Log2(bytes) can be derived with the following:
89 	 *
90 	 * Log2(words) + 2 = Log2(bytes / 4) + 2
91 	 * 		   = Log2(bytes) - 2 + 2
92 	 * 		   = Log2(bytes)
93 	 */
94 	return field + 2;
95 }
96 
97 /* Which cache CCSIDR represents depends on CSSELR value. */
get_ccsidr(struct kvm_vcpu * vcpu,u32 csselr)98 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr)
99 {
100 	u8 line_size;
101 
102 	if (vcpu->arch.ccsidr)
103 		return vcpu->arch.ccsidr[csselr];
104 
105 	line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD);
106 
107 	/*
108 	 * Fabricate a CCSIDR value as the overriding value does not exist.
109 	 * The real CCSIDR value will not be used as it can vary by the
110 	 * physical CPU which the vcpu currently resides in.
111 	 *
112 	 * The line size is determined with get_min_cache_line_size(), which
113 	 * should be valid for all CPUs even if they have different cache
114 	 * configuration.
115 	 *
116 	 * The associativity bits are cleared, meaning the geometry of all data
117 	 * and unified caches (which are guaranteed to be PIPT and thus
118 	 * non-aliasing) are 1 set and 1 way.
119 	 * Guests should not be doing cache operations by set/way at all, and
120 	 * for this reason, we trap them and attempt to infer the intent, so
121 	 * that we can flush the entire guest's address space at the appropriate
122 	 * time. The exposed geometry minimizes the number of the traps.
123 	 * [If guests should attempt to infer aliasing properties from the
124 	 * geometry (which is not permitted by the architecture), they would
125 	 * only do so for virtually indexed caches.]
126 	 *
127 	 * We don't check if the cache level exists as it is allowed to return
128 	 * an UNKNOWN value if not.
129 	 */
130 	return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4);
131 }
132 
set_ccsidr(struct kvm_vcpu * vcpu,u32 csselr,u32 val)133 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val)
134 {
135 	u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4;
136 	u32 *ccsidr = vcpu->arch.ccsidr;
137 	u32 i;
138 
139 	if ((val & CCSIDR_EL1_RES0) ||
140 	    line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD))
141 		return -EINVAL;
142 
143 	if (!ccsidr) {
144 		if (val == get_ccsidr(vcpu, csselr))
145 			return 0;
146 
147 		ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT);
148 		if (!ccsidr)
149 			return -ENOMEM;
150 
151 		for (i = 0; i < CSSELR_MAX; i++)
152 			ccsidr[i] = get_ccsidr(vcpu, i);
153 
154 		vcpu->arch.ccsidr = ccsidr;
155 	}
156 
157 	ccsidr[csselr] = val;
158 
159 	return 0;
160 }
161 
access_rw(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)162 static bool access_rw(struct kvm_vcpu *vcpu,
163 		      struct sys_reg_params *p,
164 		      const struct sys_reg_desc *r)
165 {
166 	if (p->is_write)
167 		vcpu_write_sys_reg(vcpu, p->regval, r->reg);
168 	else
169 		p->regval = vcpu_read_sys_reg(vcpu, r->reg);
170 
171 	return true;
172 }
173 
174 /*
175  * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
176  */
access_dcsw(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)177 static bool access_dcsw(struct kvm_vcpu *vcpu,
178 			struct sys_reg_params *p,
179 			const struct sys_reg_desc *r)
180 {
181 	if (!p->is_write)
182 		return read_from_write_only(vcpu, p, r);
183 
184 	/*
185 	 * Only track S/W ops if we don't have FWB. It still indicates
186 	 * that the guest is a bit broken (S/W operations should only
187 	 * be done by firmware, knowing that there is only a single
188 	 * CPU left in the system, and certainly not from non-secure
189 	 * software).
190 	 */
191 	if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
192 		kvm_set_way_flush(vcpu);
193 
194 	return true;
195 }
196 
access_dcgsw(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)197 static bool access_dcgsw(struct kvm_vcpu *vcpu,
198 			 struct sys_reg_params *p,
199 			 const struct sys_reg_desc *r)
200 {
201 	if (!kvm_has_mte(vcpu->kvm)) {
202 		kvm_inject_undefined(vcpu);
203 		return false;
204 	}
205 
206 	/* Treat MTE S/W ops as we treat the classic ones: with contempt */
207 	return access_dcsw(vcpu, p, r);
208 }
209 
get_access_mask(const struct sys_reg_desc * r,u64 * mask,u64 * shift)210 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift)
211 {
212 	switch (r->aarch32_map) {
213 	case AA32_LO:
214 		*mask = GENMASK_ULL(31, 0);
215 		*shift = 0;
216 		break;
217 	case AA32_HI:
218 		*mask = GENMASK_ULL(63, 32);
219 		*shift = 32;
220 		break;
221 	default:
222 		*mask = GENMASK_ULL(63, 0);
223 		*shift = 0;
224 		break;
225 	}
226 }
227 
228 /*
229  * Generic accessor for VM registers. Only called as long as HCR_TVM
230  * is set. If the guest enables the MMU, we stop trapping the VM
231  * sys_regs and leave it in complete control of the caches.
232  */
access_vm_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)233 static bool access_vm_reg(struct kvm_vcpu *vcpu,
234 			  struct sys_reg_params *p,
235 			  const struct sys_reg_desc *r)
236 {
237 	bool was_enabled = vcpu_has_cache_enabled(vcpu);
238 	u64 val, mask, shift;
239 
240 	BUG_ON(!p->is_write);
241 
242 	get_access_mask(r, &mask, &shift);
243 
244 	if (~mask) {
245 		val = vcpu_read_sys_reg(vcpu, r->reg);
246 		val &= ~mask;
247 	} else {
248 		val = 0;
249 	}
250 
251 	val |= (p->regval & (mask >> shift)) << shift;
252 	vcpu_write_sys_reg(vcpu, val, r->reg);
253 
254 	kvm_toggle_cache(vcpu, was_enabled);
255 	return true;
256 }
257 
access_actlr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)258 static bool access_actlr(struct kvm_vcpu *vcpu,
259 			 struct sys_reg_params *p,
260 			 const struct sys_reg_desc *r)
261 {
262 	u64 mask, shift;
263 
264 	if (p->is_write)
265 		return ignore_write(vcpu, p);
266 
267 	get_access_mask(r, &mask, &shift);
268 	p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift;
269 
270 	return true;
271 }
272 
273 /*
274  * Trap handler for the GICv3 SGI generation system register.
275  * Forward the request to the VGIC emulation.
276  * The cp15_64 code makes sure this automatically works
277  * for both AArch64 and AArch32 accesses.
278  */
access_gic_sgi(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)279 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
280 			   struct sys_reg_params *p,
281 			   const struct sys_reg_desc *r)
282 {
283 	bool g1;
284 
285 	if (!kvm_has_gicv3(vcpu->kvm)) {
286 		kvm_inject_undefined(vcpu);
287 		return false;
288 	}
289 
290 	if (!p->is_write)
291 		return read_from_write_only(vcpu, p, r);
292 
293 	/*
294 	 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
295 	 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
296 	 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
297 	 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
298 	 * group.
299 	 */
300 	if (p->Op0 == 0) {		/* AArch32 */
301 		switch (p->Op1) {
302 		default:		/* Keep GCC quiet */
303 		case 0:			/* ICC_SGI1R */
304 			g1 = true;
305 			break;
306 		case 1:			/* ICC_ASGI1R */
307 		case 2:			/* ICC_SGI0R */
308 			g1 = false;
309 			break;
310 		}
311 	} else {			/* AArch64 */
312 		switch (p->Op2) {
313 		default:		/* Keep GCC quiet */
314 		case 5:			/* ICC_SGI1R_EL1 */
315 			g1 = true;
316 			break;
317 		case 6:			/* ICC_ASGI1R_EL1 */
318 		case 7:			/* ICC_SGI0R_EL1 */
319 			g1 = false;
320 			break;
321 		}
322 	}
323 
324 	vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
325 
326 	return true;
327 }
328 
access_gic_sre(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)329 static bool access_gic_sre(struct kvm_vcpu *vcpu,
330 			   struct sys_reg_params *p,
331 			   const struct sys_reg_desc *r)
332 {
333 	if (p->is_write)
334 		return ignore_write(vcpu, p);
335 
336 	p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
337 	return true;
338 }
339 
trap_raz_wi(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)340 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
341 			struct sys_reg_params *p,
342 			const struct sys_reg_desc *r)
343 {
344 	if (p->is_write)
345 		return ignore_write(vcpu, p);
346 	else
347 		return read_zero(vcpu, p);
348 }
349 
trap_undef(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)350 static bool trap_undef(struct kvm_vcpu *vcpu,
351 		       struct sys_reg_params *p,
352 		       const struct sys_reg_desc *r)
353 {
354 	kvm_inject_undefined(vcpu);
355 	return false;
356 }
357 
358 /*
359  * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
360  * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
361  * system, these registers should UNDEF. LORID_EL1 being a RO register, we
362  * treat it separately.
363  */
trap_loregion(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)364 static bool trap_loregion(struct kvm_vcpu *vcpu,
365 			  struct sys_reg_params *p,
366 			  const struct sys_reg_desc *r)
367 {
368 	u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
369 	u32 sr = reg_to_encoding(r);
370 
371 	if (!(val & (0xfUL << ID_AA64MMFR1_EL1_LO_SHIFT))) {
372 		kvm_inject_undefined(vcpu);
373 		return false;
374 	}
375 
376 	if (p->is_write && sr == SYS_LORID_EL1)
377 		return write_to_read_only(vcpu, p, r);
378 
379 	return trap_raz_wi(vcpu, p, r);
380 }
381 
trap_oslar_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)382 static bool trap_oslar_el1(struct kvm_vcpu *vcpu,
383 			   struct sys_reg_params *p,
384 			   const struct sys_reg_desc *r)
385 {
386 	u64 oslsr;
387 
388 	if (!p->is_write)
389 		return read_from_write_only(vcpu, p, r);
390 
391 	/* Forward the OSLK bit to OSLSR */
392 	oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~OSLSR_EL1_OSLK;
393 	if (p->regval & OSLAR_EL1_OSLK)
394 		oslsr |= OSLSR_EL1_OSLK;
395 
396 	__vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr;
397 	return true;
398 }
399 
trap_oslsr_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)400 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
401 			   struct sys_reg_params *p,
402 			   const struct sys_reg_desc *r)
403 {
404 	if (p->is_write)
405 		return write_to_read_only(vcpu, p, r);
406 
407 	p->regval = __vcpu_sys_reg(vcpu, r->reg);
408 	return true;
409 }
410 
set_oslsr_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)411 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
412 			 u64 val)
413 {
414 	/*
415 	 * The only modifiable bit is the OSLK bit. Refuse the write if
416 	 * userspace attempts to change any other bit in the register.
417 	 */
418 	if ((val ^ rd->val) & ~OSLSR_EL1_OSLK)
419 		return -EINVAL;
420 
421 	__vcpu_sys_reg(vcpu, rd->reg) = val;
422 	return 0;
423 }
424 
trap_dbgauthstatus_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)425 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
426 				   struct sys_reg_params *p,
427 				   const struct sys_reg_desc *r)
428 {
429 	if (p->is_write) {
430 		return ignore_write(vcpu, p);
431 	} else {
432 		p->regval = read_sysreg(dbgauthstatus_el1);
433 		return true;
434 	}
435 }
436 
437 /*
438  * We want to avoid world-switching all the DBG registers all the
439  * time:
440  *
441  * - If we've touched any debug register, it is likely that we're
442  *   going to touch more of them. It then makes sense to disable the
443  *   traps and start doing the save/restore dance
444  * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
445  *   then mandatory to save/restore the registers, as the guest
446  *   depends on them.
447  *
448  * For this, we use a DIRTY bit, indicating the guest has modified the
449  * debug registers, used as follow:
450  *
451  * On guest entry:
452  * - If the dirty bit is set (because we're coming back from trapping),
453  *   disable the traps, save host registers, restore guest registers.
454  * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
455  *   set the dirty bit, disable the traps, save host registers,
456  *   restore guest registers.
457  * - Otherwise, enable the traps
458  *
459  * On guest exit:
460  * - If the dirty bit is set, save guest registers, restore host
461  *   registers and clear the dirty bit. This ensure that the host can
462  *   now use the debug registers.
463  */
trap_debug_regs(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)464 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
465 			    struct sys_reg_params *p,
466 			    const struct sys_reg_desc *r)
467 {
468 	access_rw(vcpu, p, r);
469 	if (p->is_write)
470 		vcpu_set_flag(vcpu, DEBUG_DIRTY);
471 
472 	trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
473 
474 	return true;
475 }
476 
477 /*
478  * reg_to_dbg/dbg_to_reg
479  *
480  * A 32 bit write to a debug register leave top bits alone
481  * A 32 bit read from a debug register only returns the bottom bits
482  *
483  * All writes will set the DEBUG_DIRTY flag to ensure the hyp code
484  * switches between host and guest values in future.
485  */
reg_to_dbg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd,u64 * dbg_reg)486 static void reg_to_dbg(struct kvm_vcpu *vcpu,
487 		       struct sys_reg_params *p,
488 		       const struct sys_reg_desc *rd,
489 		       u64 *dbg_reg)
490 {
491 	u64 mask, shift, val;
492 
493 	get_access_mask(rd, &mask, &shift);
494 
495 	val = *dbg_reg;
496 	val &= ~mask;
497 	val |= (p->regval & (mask >> shift)) << shift;
498 	*dbg_reg = val;
499 
500 	vcpu_set_flag(vcpu, DEBUG_DIRTY);
501 }
502 
dbg_to_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd,u64 * dbg_reg)503 static void dbg_to_reg(struct kvm_vcpu *vcpu,
504 		       struct sys_reg_params *p,
505 		       const struct sys_reg_desc *rd,
506 		       u64 *dbg_reg)
507 {
508 	u64 mask, shift;
509 
510 	get_access_mask(rd, &mask, &shift);
511 	p->regval = (*dbg_reg & mask) >> shift;
512 }
513 
trap_bvr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)514 static bool trap_bvr(struct kvm_vcpu *vcpu,
515 		     struct sys_reg_params *p,
516 		     const struct sys_reg_desc *rd)
517 {
518 	u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
519 
520 	if (p->is_write)
521 		reg_to_dbg(vcpu, p, rd, dbg_reg);
522 	else
523 		dbg_to_reg(vcpu, p, rd, dbg_reg);
524 
525 	trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
526 
527 	return true;
528 }
529 
set_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)530 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
531 		   u64 val)
532 {
533 	vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val;
534 	return 0;
535 }
536 
get_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)537 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
538 		   u64 *val)
539 {
540 	*val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
541 	return 0;
542 }
543 
reset_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)544 static u64 reset_bvr(struct kvm_vcpu *vcpu,
545 		      const struct sys_reg_desc *rd)
546 {
547 	vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;
548 	return rd->val;
549 }
550 
trap_bcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)551 static bool trap_bcr(struct kvm_vcpu *vcpu,
552 		     struct sys_reg_params *p,
553 		     const struct sys_reg_desc *rd)
554 {
555 	u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
556 
557 	if (p->is_write)
558 		reg_to_dbg(vcpu, p, rd, dbg_reg);
559 	else
560 		dbg_to_reg(vcpu, p, rd, dbg_reg);
561 
562 	trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
563 
564 	return true;
565 }
566 
set_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)567 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
568 		   u64 val)
569 {
570 	vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val;
571 	return 0;
572 }
573 
get_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)574 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
575 		   u64 *val)
576 {
577 	*val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
578 	return 0;
579 }
580 
reset_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)581 static u64 reset_bcr(struct kvm_vcpu *vcpu,
582 		      const struct sys_reg_desc *rd)
583 {
584 	vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;
585 	return rd->val;
586 }
587 
trap_wvr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)588 static bool trap_wvr(struct kvm_vcpu *vcpu,
589 		     struct sys_reg_params *p,
590 		     const struct sys_reg_desc *rd)
591 {
592 	u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
593 
594 	if (p->is_write)
595 		reg_to_dbg(vcpu, p, rd, dbg_reg);
596 	else
597 		dbg_to_reg(vcpu, p, rd, dbg_reg);
598 
599 	trace_trap_reg(__func__, rd->CRm, p->is_write,
600 		vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]);
601 
602 	return true;
603 }
604 
set_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)605 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
606 		   u64 val)
607 {
608 	vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = val;
609 	return 0;
610 }
611 
get_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)612 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
613 		   u64 *val)
614 {
615 	*val = vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
616 	return 0;
617 }
618 
reset_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)619 static u64 reset_wvr(struct kvm_vcpu *vcpu,
620 		      const struct sys_reg_desc *rd)
621 {
622 	vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;
623 	return rd->val;
624 }
625 
trap_wcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)626 static bool trap_wcr(struct kvm_vcpu *vcpu,
627 		     struct sys_reg_params *p,
628 		     const struct sys_reg_desc *rd)
629 {
630 	u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
631 
632 	if (p->is_write)
633 		reg_to_dbg(vcpu, p, rd, dbg_reg);
634 	else
635 		dbg_to_reg(vcpu, p, rd, dbg_reg);
636 
637 	trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
638 
639 	return true;
640 }
641 
set_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)642 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
643 		   u64 val)
644 {
645 	vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = val;
646 	return 0;
647 }
648 
get_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)649 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
650 		   u64 *val)
651 {
652 	*val = vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
653 	return 0;
654 }
655 
reset_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)656 static u64 reset_wcr(struct kvm_vcpu *vcpu,
657 		      const struct sys_reg_desc *rd)
658 {
659 	vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;
660 	return rd->val;
661 }
662 
reset_amair_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)663 static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
664 {
665 	u64 amair = read_sysreg(amair_el1);
666 	vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
667 	return amair;
668 }
669 
reset_actlr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)670 static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
671 {
672 	u64 actlr = read_sysreg(actlr_el1);
673 	vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1);
674 	return actlr;
675 }
676 
reset_mpidr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)677 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
678 {
679 	u64 mpidr = calculate_mpidr(vcpu);
680 
681 	vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1);
682 	return mpidr;
683 }
684 
pmu_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)685 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu,
686 				   const struct sys_reg_desc *r)
687 {
688 	if (kvm_vcpu_has_pmu(vcpu))
689 		return 0;
690 
691 	return REG_HIDDEN;
692 }
693 
reset_pmu_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)694 static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
695 {
696 	u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX);
697 
698 	/* No PMU available, any PMU reg may UNDEF... */
699 	if (!kvm_arm_support_pmu_v3())
700 		return 0;
701 
702 	n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT;
703 	n &= ARMV8_PMU_PMCR_N_MASK;
704 	if (n)
705 		mask |= GENMASK(n - 1, 0);
706 
707 	reset_unknown(vcpu, r);
708 	__vcpu_sys_reg(vcpu, r->reg) &= mask;
709 
710 	return __vcpu_sys_reg(vcpu, r->reg);
711 }
712 
reset_pmevcntr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)713 static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
714 {
715 	reset_unknown(vcpu, r);
716 	__vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0);
717 
718 	return __vcpu_sys_reg(vcpu, r->reg);
719 }
720 
reset_pmevtyper(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)721 static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
722 {
723 	reset_unknown(vcpu, r);
724 	__vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_EVTYPE_MASK;
725 
726 	return __vcpu_sys_reg(vcpu, r->reg);
727 }
728 
reset_pmselr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)729 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
730 {
731 	reset_unknown(vcpu, r);
732 	__vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK;
733 
734 	return __vcpu_sys_reg(vcpu, r->reg);
735 }
736 
reset_pmcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)737 static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
738 {
739 	u64 pmcr;
740 
741 	/* No PMU available, PMCR_EL0 may UNDEF... */
742 	if (!kvm_arm_support_pmu_v3())
743 		return 0;
744 
745 	/* Only preserve PMCR_EL0.N, and reset the rest to 0 */
746 	pmcr = read_sysreg(pmcr_el0) & (ARMV8_PMU_PMCR_N_MASK << ARMV8_PMU_PMCR_N_SHIFT);
747 	if (!kvm_supports_32bit_el0())
748 		pmcr |= ARMV8_PMU_PMCR_LC;
749 
750 	__vcpu_sys_reg(vcpu, r->reg) = pmcr;
751 
752 	return __vcpu_sys_reg(vcpu, r->reg);
753 }
754 
check_pmu_access_disabled(struct kvm_vcpu * vcpu,u64 flags)755 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
756 {
757 	u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
758 	bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
759 
760 	if (!enabled)
761 		kvm_inject_undefined(vcpu);
762 
763 	return !enabled;
764 }
765 
pmu_access_el0_disabled(struct kvm_vcpu * vcpu)766 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
767 {
768 	return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
769 }
770 
pmu_write_swinc_el0_disabled(struct kvm_vcpu * vcpu)771 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
772 {
773 	return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
774 }
775 
pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu * vcpu)776 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
777 {
778 	return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
779 }
780 
pmu_access_event_counter_el0_disabled(struct kvm_vcpu * vcpu)781 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
782 {
783 	return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
784 }
785 
access_pmcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)786 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
787 			const struct sys_reg_desc *r)
788 {
789 	u64 val;
790 
791 	if (pmu_access_el0_disabled(vcpu))
792 		return false;
793 
794 	if (p->is_write) {
795 		/*
796 		 * Only update writeable bits of PMCR (continuing into
797 		 * kvm_pmu_handle_pmcr() as well)
798 		 */
799 		val = __vcpu_sys_reg(vcpu, PMCR_EL0);
800 		val &= ~ARMV8_PMU_PMCR_MASK;
801 		val |= p->regval & ARMV8_PMU_PMCR_MASK;
802 		if (!kvm_supports_32bit_el0())
803 			val |= ARMV8_PMU_PMCR_LC;
804 		kvm_pmu_handle_pmcr(vcpu, val);
805 	} else {
806 		/* PMCR.P & PMCR.C are RAZ */
807 		val = __vcpu_sys_reg(vcpu, PMCR_EL0)
808 		      & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
809 		p->regval = val;
810 	}
811 
812 	return true;
813 }
814 
access_pmselr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)815 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
816 			  const struct sys_reg_desc *r)
817 {
818 	if (pmu_access_event_counter_el0_disabled(vcpu))
819 		return false;
820 
821 	if (p->is_write)
822 		__vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
823 	else
824 		/* return PMSELR.SEL field */
825 		p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
826 			    & ARMV8_PMU_COUNTER_MASK;
827 
828 	return true;
829 }
830 
access_pmceid(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)831 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
832 			  const struct sys_reg_desc *r)
833 {
834 	u64 pmceid, mask, shift;
835 
836 	BUG_ON(p->is_write);
837 
838 	if (pmu_access_el0_disabled(vcpu))
839 		return false;
840 
841 	get_access_mask(r, &mask, &shift);
842 
843 	pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1));
844 	pmceid &= mask;
845 	pmceid >>= shift;
846 
847 	p->regval = pmceid;
848 
849 	return true;
850 }
851 
pmu_counter_idx_valid(struct kvm_vcpu * vcpu,u64 idx)852 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
853 {
854 	u64 pmcr, val;
855 
856 	pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0);
857 	val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
858 	if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
859 		kvm_inject_undefined(vcpu);
860 		return false;
861 	}
862 
863 	return true;
864 }
865 
get_pmu_evcntr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 * val)866 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
867 			  u64 *val)
868 {
869 	u64 idx;
870 
871 	if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0)
872 		/* PMCCNTR_EL0 */
873 		idx = ARMV8_PMU_CYCLE_IDX;
874 	else
875 		/* PMEVCNTRn_EL0 */
876 		idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
877 
878 	*val = kvm_pmu_get_counter_value(vcpu, idx);
879 	return 0;
880 }
881 
access_pmu_evcntr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)882 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
883 			      struct sys_reg_params *p,
884 			      const struct sys_reg_desc *r)
885 {
886 	u64 idx = ~0UL;
887 
888 	if (r->CRn == 9 && r->CRm == 13) {
889 		if (r->Op2 == 2) {
890 			/* PMXEVCNTR_EL0 */
891 			if (pmu_access_event_counter_el0_disabled(vcpu))
892 				return false;
893 
894 			idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
895 			      & ARMV8_PMU_COUNTER_MASK;
896 		} else if (r->Op2 == 0) {
897 			/* PMCCNTR_EL0 */
898 			if (pmu_access_cycle_counter_el0_disabled(vcpu))
899 				return false;
900 
901 			idx = ARMV8_PMU_CYCLE_IDX;
902 		}
903 	} else if (r->CRn == 0 && r->CRm == 9) {
904 		/* PMCCNTR */
905 		if (pmu_access_event_counter_el0_disabled(vcpu))
906 			return false;
907 
908 		idx = ARMV8_PMU_CYCLE_IDX;
909 	} else if (r->CRn == 14 && (r->CRm & 12) == 8) {
910 		/* PMEVCNTRn_EL0 */
911 		if (pmu_access_event_counter_el0_disabled(vcpu))
912 			return false;
913 
914 		idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
915 	}
916 
917 	/* Catch any decoding mistake */
918 	WARN_ON(idx == ~0UL);
919 
920 	if (!pmu_counter_idx_valid(vcpu, idx))
921 		return false;
922 
923 	if (p->is_write) {
924 		if (pmu_access_el0_disabled(vcpu))
925 			return false;
926 
927 		kvm_pmu_set_counter_value(vcpu, idx, p->regval);
928 	} else {
929 		p->regval = kvm_pmu_get_counter_value(vcpu, idx);
930 	}
931 
932 	return true;
933 }
934 
access_pmu_evtyper(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)935 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
936 			       const struct sys_reg_desc *r)
937 {
938 	u64 idx, reg;
939 
940 	if (pmu_access_el0_disabled(vcpu))
941 		return false;
942 
943 	if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
944 		/* PMXEVTYPER_EL0 */
945 		idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
946 		reg = PMEVTYPER0_EL0 + idx;
947 	} else if (r->CRn == 14 && (r->CRm & 12) == 12) {
948 		idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
949 		if (idx == ARMV8_PMU_CYCLE_IDX)
950 			reg = PMCCFILTR_EL0;
951 		else
952 			/* PMEVTYPERn_EL0 */
953 			reg = PMEVTYPER0_EL0 + idx;
954 	} else {
955 		BUG();
956 	}
957 
958 	if (!pmu_counter_idx_valid(vcpu, idx))
959 		return false;
960 
961 	if (p->is_write) {
962 		kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
963 		kvm_vcpu_pmu_restore_guest(vcpu);
964 	} else {
965 		p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
966 	}
967 
968 	return true;
969 }
970 
access_pmcnten(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)971 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
972 			   const struct sys_reg_desc *r)
973 {
974 	u64 val, mask;
975 
976 	if (pmu_access_el0_disabled(vcpu))
977 		return false;
978 
979 	mask = kvm_pmu_valid_counter_mask(vcpu);
980 	if (p->is_write) {
981 		val = p->regval & mask;
982 		if (r->Op2 & 0x1) {
983 			/* accessing PMCNTENSET_EL0 */
984 			__vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
985 			kvm_pmu_enable_counter_mask(vcpu, val);
986 			kvm_vcpu_pmu_restore_guest(vcpu);
987 		} else {
988 			/* accessing PMCNTENCLR_EL0 */
989 			__vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
990 			kvm_pmu_disable_counter_mask(vcpu, val);
991 		}
992 	} else {
993 		p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
994 	}
995 
996 	return true;
997 }
998 
access_pminten(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)999 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1000 			   const struct sys_reg_desc *r)
1001 {
1002 	u64 mask = kvm_pmu_valid_counter_mask(vcpu);
1003 
1004 	if (check_pmu_access_disabled(vcpu, 0))
1005 		return false;
1006 
1007 	if (p->is_write) {
1008 		u64 val = p->regval & mask;
1009 
1010 		if (r->Op2 & 0x1)
1011 			/* accessing PMINTENSET_EL1 */
1012 			__vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
1013 		else
1014 			/* accessing PMINTENCLR_EL1 */
1015 			__vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
1016 	} else {
1017 		p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1);
1018 	}
1019 
1020 	return true;
1021 }
1022 
access_pmovs(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1023 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1024 			 const struct sys_reg_desc *r)
1025 {
1026 	u64 mask = kvm_pmu_valid_counter_mask(vcpu);
1027 
1028 	if (pmu_access_el0_disabled(vcpu))
1029 		return false;
1030 
1031 	if (p->is_write) {
1032 		if (r->CRm & 0x2)
1033 			/* accessing PMOVSSET_EL0 */
1034 			__vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
1035 		else
1036 			/* accessing PMOVSCLR_EL0 */
1037 			__vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
1038 	} else {
1039 		p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);
1040 	}
1041 
1042 	return true;
1043 }
1044 
access_pmswinc(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1045 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1046 			   const struct sys_reg_desc *r)
1047 {
1048 	u64 mask;
1049 
1050 	if (!p->is_write)
1051 		return read_from_write_only(vcpu, p, r);
1052 
1053 	if (pmu_write_swinc_el0_disabled(vcpu))
1054 		return false;
1055 
1056 	mask = kvm_pmu_valid_counter_mask(vcpu);
1057 	kvm_pmu_software_increment(vcpu, p->regval & mask);
1058 	return true;
1059 }
1060 
access_pmuserenr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1061 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1062 			     const struct sys_reg_desc *r)
1063 {
1064 	if (p->is_write) {
1065 		if (!vcpu_mode_priv(vcpu)) {
1066 			kvm_inject_undefined(vcpu);
1067 			return false;
1068 		}
1069 
1070 		__vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
1071 			       p->regval & ARMV8_PMU_USERENR_MASK;
1072 	} else {
1073 		p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
1074 			    & ARMV8_PMU_USERENR_MASK;
1075 	}
1076 
1077 	return true;
1078 }
1079 
1080 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
1081 #define DBG_BCR_BVR_WCR_WVR_EL1(n)					\
1082 	{ SYS_DESC(SYS_DBGBVRn_EL1(n)),					\
1083 	  trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr },		\
1084 	{ SYS_DESC(SYS_DBGBCRn_EL1(n)),					\
1085 	  trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr },		\
1086 	{ SYS_DESC(SYS_DBGWVRn_EL1(n)),					\
1087 	  trap_wvr, reset_wvr, 0, 0,  get_wvr, set_wvr },		\
1088 	{ SYS_DESC(SYS_DBGWCRn_EL1(n)),					\
1089 	  trap_wcr, reset_wcr, 0, 0,  get_wcr, set_wcr }
1090 
1091 #define PMU_SYS_REG(name)						\
1092 	SYS_DESC(SYS_##name), .reset = reset_pmu_reg,			\
1093 	.visibility = pmu_visibility
1094 
1095 /* Macro to expand the PMEVCNTRn_EL0 register */
1096 #define PMU_PMEVCNTR_EL0(n)						\
1097 	{ PMU_SYS_REG(PMEVCNTRn_EL0(n)),				\
1098 	  .reset = reset_pmevcntr, .get_user = get_pmu_evcntr,		\
1099 	  .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), }
1100 
1101 /* Macro to expand the PMEVTYPERn_EL0 register */
1102 #define PMU_PMEVTYPER_EL0(n)						\
1103 	{ PMU_SYS_REG(PMEVTYPERn_EL0(n)),				\
1104 	  .reset = reset_pmevtyper,					\
1105 	  .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), }
1106 
undef_access(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1107 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1108 			 const struct sys_reg_desc *r)
1109 {
1110 	kvm_inject_undefined(vcpu);
1111 
1112 	return false;
1113 }
1114 
1115 /* Macro to expand the AMU counter and type registers*/
1116 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access }
1117 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access }
1118 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access }
1119 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access }
1120 
ptrauth_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1121 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
1122 			const struct sys_reg_desc *rd)
1123 {
1124 	return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN;
1125 }
1126 
1127 /*
1128  * If we land here on a PtrAuth access, that is because we didn't
1129  * fixup the access on exit by allowing the PtrAuth sysregs. The only
1130  * way this happens is when the guest does not have PtrAuth support
1131  * enabled.
1132  */
1133 #define __PTRAUTH_KEY(k)						\
1134 	{ SYS_DESC(SYS_## k), undef_access, reset_unknown, k,		\
1135 	.visibility = ptrauth_visibility}
1136 
1137 #define PTRAUTH_KEY(k)							\
1138 	__PTRAUTH_KEY(k ## KEYLO_EL1),					\
1139 	__PTRAUTH_KEY(k ## KEYHI_EL1)
1140 
access_arch_timer(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1141 static bool access_arch_timer(struct kvm_vcpu *vcpu,
1142 			      struct sys_reg_params *p,
1143 			      const struct sys_reg_desc *r)
1144 {
1145 	enum kvm_arch_timers tmr;
1146 	enum kvm_arch_timer_regs treg;
1147 	u64 reg = reg_to_encoding(r);
1148 
1149 	switch (reg) {
1150 	case SYS_CNTP_TVAL_EL0:
1151 	case SYS_AARCH32_CNTP_TVAL:
1152 		tmr = TIMER_PTIMER;
1153 		treg = TIMER_REG_TVAL;
1154 		break;
1155 	case SYS_CNTP_CTL_EL0:
1156 	case SYS_AARCH32_CNTP_CTL:
1157 		tmr = TIMER_PTIMER;
1158 		treg = TIMER_REG_CTL;
1159 		break;
1160 	case SYS_CNTP_CVAL_EL0:
1161 	case SYS_AARCH32_CNTP_CVAL:
1162 		tmr = TIMER_PTIMER;
1163 		treg = TIMER_REG_CVAL;
1164 		break;
1165 	case SYS_CNTPCT_EL0:
1166 	case SYS_CNTPCTSS_EL0:
1167 	case SYS_AARCH32_CNTPCT:
1168 		tmr = TIMER_PTIMER;
1169 		treg = TIMER_REG_CNT;
1170 		break;
1171 	default:
1172 		print_sys_reg_msg(p, "%s", "Unhandled trapped timer register");
1173 		kvm_inject_undefined(vcpu);
1174 		return false;
1175 	}
1176 
1177 	if (p->is_write)
1178 		kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
1179 	else
1180 		p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
1181 
1182 	return true;
1183 }
1184 
kvm_arm64_ftr_safe_value(u32 id,const struct arm64_ftr_bits * ftrp,s64 new,s64 cur)1185 static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp,
1186 				    s64 new, s64 cur)
1187 {
1188 	struct arm64_ftr_bits kvm_ftr = *ftrp;
1189 
1190 	/* Some features have different safe value type in KVM than host features */
1191 	switch (id) {
1192 	case SYS_ID_AA64DFR0_EL1:
1193 		if (kvm_ftr.shift == ID_AA64DFR0_EL1_PMUVer_SHIFT)
1194 			kvm_ftr.type = FTR_LOWER_SAFE;
1195 		break;
1196 	case SYS_ID_DFR0_EL1:
1197 		if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT)
1198 			kvm_ftr.type = FTR_LOWER_SAFE;
1199 		break;
1200 	}
1201 
1202 	return arm64_ftr_safe_value(&kvm_ftr, new, cur);
1203 }
1204 
1205 /**
1206  * arm64_check_features() - Check if a feature register value constitutes
1207  * a subset of features indicated by the idreg's KVM sanitised limit.
1208  *
1209  * This function will check if each feature field of @val is the "safe" value
1210  * against idreg's KVM sanitised limit return from reset() callback.
1211  * If a field value in @val is the same as the one in limit, it is always
1212  * considered the safe value regardless For register fields that are not in
1213  * writable, only the value in limit is considered the safe value.
1214  *
1215  * Return: 0 if all the fields are safe. Otherwise, return negative errno.
1216  */
arm64_check_features(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1217 static int arm64_check_features(struct kvm_vcpu *vcpu,
1218 				const struct sys_reg_desc *rd,
1219 				u64 val)
1220 {
1221 	const struct arm64_ftr_reg *ftr_reg;
1222 	const struct arm64_ftr_bits *ftrp = NULL;
1223 	u32 id = reg_to_encoding(rd);
1224 	u64 writable_mask = rd->val;
1225 	u64 limit = rd->reset(vcpu, rd);
1226 	u64 mask = 0;
1227 
1228 	/*
1229 	 * Hidden and unallocated ID registers may not have a corresponding
1230 	 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the
1231 	 * only safe value is 0.
1232 	 */
1233 	if (sysreg_visible_as_raz(vcpu, rd))
1234 		return val ? -E2BIG : 0;
1235 
1236 	ftr_reg = get_arm64_ftr_reg(id);
1237 	if (!ftr_reg)
1238 		return -EINVAL;
1239 
1240 	ftrp = ftr_reg->ftr_bits;
1241 
1242 	for (; ftrp && ftrp->width; ftrp++) {
1243 		s64 f_val, f_lim, safe_val;
1244 		u64 ftr_mask;
1245 
1246 		ftr_mask = arm64_ftr_mask(ftrp);
1247 		if ((ftr_mask & writable_mask) != ftr_mask)
1248 			continue;
1249 
1250 		f_val = arm64_ftr_value(ftrp, val);
1251 		f_lim = arm64_ftr_value(ftrp, limit);
1252 		mask |= ftr_mask;
1253 
1254 		if (f_val == f_lim)
1255 			safe_val = f_val;
1256 		else
1257 			safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim);
1258 
1259 		if (safe_val != f_val)
1260 			return -E2BIG;
1261 	}
1262 
1263 	/* For fields that are not writable, values in limit are the safe values. */
1264 	if ((val & ~mask) != (limit & ~mask))
1265 		return -E2BIG;
1266 
1267 	return 0;
1268 }
1269 
pmuver_to_perfmon(u8 pmuver)1270 static u8 pmuver_to_perfmon(u8 pmuver)
1271 {
1272 	switch (pmuver) {
1273 	case ID_AA64DFR0_EL1_PMUVer_IMP:
1274 		return ID_DFR0_EL1_PerfMon_PMUv3;
1275 	case ID_AA64DFR0_EL1_PMUVer_IMP_DEF:
1276 		return ID_DFR0_EL1_PerfMon_IMPDEF;
1277 	default:
1278 		/* Anything ARMv8.1+ and NI have the same value. For now. */
1279 		return pmuver;
1280 	}
1281 }
1282 
1283 /* Read a sanitised cpufeature ID register by sys_reg_desc */
__kvm_read_sanitised_id_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1284 static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu,
1285 				       const struct sys_reg_desc *r)
1286 {
1287 	u32 id = reg_to_encoding(r);
1288 	u64 val;
1289 
1290 	if (sysreg_visible_as_raz(vcpu, r))
1291 		return 0;
1292 
1293 	val = read_sanitised_ftr_reg(id);
1294 
1295 	switch (id) {
1296 	case SYS_ID_AA64PFR1_EL1:
1297 		if (!kvm_has_mte(vcpu->kvm))
1298 			val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE);
1299 
1300 		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME);
1301 		break;
1302 	case SYS_ID_AA64ISAR1_EL1:
1303 		if (!vcpu_has_ptrauth(vcpu))
1304 			val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) |
1305 				 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) |
1306 				 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) |
1307 				 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI));
1308 		break;
1309 	case SYS_ID_AA64ISAR2_EL1:
1310 		if (!vcpu_has_ptrauth(vcpu))
1311 			val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) |
1312 				 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3));
1313 		if (!cpus_have_final_cap(ARM64_HAS_WFXT))
1314 			val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT);
1315 		val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_MOPS);
1316 		break;
1317 	case SYS_ID_AA64MMFR2_EL1:
1318 		val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK;
1319 		break;
1320 	case SYS_ID_MMFR4_EL1:
1321 		val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX);
1322 		break;
1323 	}
1324 
1325 	return val;
1326 }
1327 
kvm_read_sanitised_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1328 static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu,
1329 				     const struct sys_reg_desc *r)
1330 {
1331 	return __kvm_read_sanitised_id_reg(vcpu, r);
1332 }
1333 
read_id_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1334 static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
1335 {
1336 	return IDREG(vcpu->kvm, reg_to_encoding(r));
1337 }
1338 
1339 /*
1340  * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is
1341  * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8.
1342  */
is_id_reg(u32 id)1343 static inline bool is_id_reg(u32 id)
1344 {
1345 	return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 &&
1346 		sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 &&
1347 		sys_reg_CRm(id) < 8);
1348 }
1349 
id_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1350 static unsigned int id_visibility(const struct kvm_vcpu *vcpu,
1351 				  const struct sys_reg_desc *r)
1352 {
1353 	u32 id = reg_to_encoding(r);
1354 
1355 	switch (id) {
1356 	case SYS_ID_AA64ZFR0_EL1:
1357 		if (!vcpu_has_sve(vcpu))
1358 			return REG_RAZ;
1359 		break;
1360 	}
1361 
1362 	return 0;
1363 }
1364 
aa32_id_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1365 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu,
1366 				       const struct sys_reg_desc *r)
1367 {
1368 	/*
1369 	 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any
1370 	 * EL. Promote to RAZ/WI in order to guarantee consistency between
1371 	 * systems.
1372 	 */
1373 	if (!kvm_supports_32bit_el0())
1374 		return REG_RAZ | REG_USER_WI;
1375 
1376 	return id_visibility(vcpu, r);
1377 }
1378 
raz_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1379 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu,
1380 				   const struct sys_reg_desc *r)
1381 {
1382 	return REG_RAZ;
1383 }
1384 
1385 /* cpufeature ID register access trap handlers */
1386 
access_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1387 static bool access_id_reg(struct kvm_vcpu *vcpu,
1388 			  struct sys_reg_params *p,
1389 			  const struct sys_reg_desc *r)
1390 {
1391 	if (p->is_write)
1392 		return write_to_read_only(vcpu, p, r);
1393 
1394 	p->regval = read_id_reg(vcpu, r);
1395 	if (vcpu_has_nv(vcpu))
1396 		access_nested_id_reg(vcpu, p, r);
1397 
1398 	return true;
1399 }
1400 
1401 /* Visibility overrides for SVE-specific control registers */
sve_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1402 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
1403 				   const struct sys_reg_desc *rd)
1404 {
1405 	if (vcpu_has_sve(vcpu))
1406 		return 0;
1407 
1408 	return REG_HIDDEN;
1409 }
1410 
read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1411 static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
1412 					  const struct sys_reg_desc *rd)
1413 {
1414 	u64 val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1415 
1416 	if (!vcpu_has_sve(vcpu))
1417 		val &= ~ID_AA64PFR0_EL1_SVE_MASK;
1418 
1419 	/*
1420 	 * The default is to expose CSV2 == 1 if the HW isn't affected.
1421 	 * Although this is a per-CPU feature, we make it global because
1422 	 * asymmetric systems are just a nuisance.
1423 	 *
1424 	 * Userspace can override this as long as it doesn't promise
1425 	 * the impossible.
1426 	 */
1427 	if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) {
1428 		val &= ~ID_AA64PFR0_EL1_CSV2_MASK;
1429 		val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP);
1430 	}
1431 	if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) {
1432 		val &= ~ID_AA64PFR0_EL1_CSV3_MASK;
1433 		val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP);
1434 	}
1435 
1436 	if (kvm_vgic_global_state.type == VGIC_V3) {
1437 		val &= ~ID_AA64PFR0_EL1_GIC_MASK;
1438 		val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP);
1439 	}
1440 
1441 	val &= ~ID_AA64PFR0_EL1_AMU_MASK;
1442 
1443 	return val;
1444 }
1445 
read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1446 static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
1447 					  const struct sys_reg_desc *rd)
1448 {
1449 	u64 val = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1450 
1451 	/* Limit debug to ARMv8.0 */
1452 	val &= ~ID_AA64DFR0_EL1_DebugVer_MASK;
1453 	val |= SYS_FIELD_PREP_ENUM(ID_AA64DFR0_EL1, DebugVer, IMP);
1454 
1455 	/*
1456 	 * Only initialize the PMU version if the vCPU was configured with one.
1457 	 */
1458 	val &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
1459 	if (kvm_vcpu_has_pmu(vcpu))
1460 		val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer,
1461 				      kvm_arm_pmu_get_pmuver_limit());
1462 
1463 	/* Hide SPE from guests */
1464 	val &= ~ID_AA64DFR0_EL1_PMSVer_MASK;
1465 
1466 	return val;
1467 }
1468 
set_id_aa64dfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1469 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
1470 			       const struct sys_reg_desc *rd,
1471 			       u64 val)
1472 {
1473 	u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val);
1474 
1475 	/*
1476 	 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the
1477 	 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously
1478 	 * exposed an IMP_DEF PMU to userspace and the guest on systems w/
1479 	 * non-architectural PMUs. Of course, PMUv3 is the only game in town for
1480 	 * PMU virtualization, so the IMP_DEF value was rather user-hostile.
1481 	 *
1482 	 * At minimum, we're on the hook to allow values that were given to
1483 	 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value
1484 	 * with a more sensible NI. The value of an ID register changing under
1485 	 * the nose of the guest is unfortunate, but is certainly no more
1486 	 * surprising than an ill-guided PMU driver poking at impdef system
1487 	 * registers that end in an UNDEF...
1488 	 */
1489 	if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF)
1490 		val &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
1491 
1492 	return set_id_reg(vcpu, rd, val);
1493 }
1494 
read_sanitised_id_dfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1495 static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu,
1496 				      const struct sys_reg_desc *rd)
1497 {
1498 	u8 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit());
1499 	u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1);
1500 
1501 	val &= ~ID_DFR0_EL1_PerfMon_MASK;
1502 	if (kvm_vcpu_has_pmu(vcpu))
1503 		val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon);
1504 
1505 	return val;
1506 }
1507 
set_id_dfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1508 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
1509 			   const struct sys_reg_desc *rd,
1510 			   u64 val)
1511 {
1512 	u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val);
1513 
1514 	if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) {
1515 		val &= ~ID_DFR0_EL1_PerfMon_MASK;
1516 		perfmon = 0;
1517 	}
1518 
1519 	/*
1520 	 * Allow DFR0_EL1.PerfMon to be set from userspace as long as
1521 	 * it doesn't promise more than what the HW gives us on the
1522 	 * AArch64 side (as everything is emulated with that), and
1523 	 * that this is a PMUv3.
1524 	 */
1525 	if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3)
1526 		return -EINVAL;
1527 
1528 	return set_id_reg(vcpu, rd, val);
1529 }
1530 
1531 /*
1532  * cpufeature ID register user accessors
1533  *
1534  * For now, these registers are immutable for userspace, so no values
1535  * are stored, and for set_id_reg() we don't allow the effective value
1536  * to be changed.
1537  */
get_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)1538 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1539 		      u64 *val)
1540 {
1541 	/*
1542 	 * Avoid locking if the VM has already started, as the ID registers are
1543 	 * guaranteed to be invariant at that point.
1544 	 */
1545 	if (kvm_vm_has_ran_once(vcpu->kvm)) {
1546 		*val = read_id_reg(vcpu, rd);
1547 		return 0;
1548 	}
1549 
1550 	mutex_lock(&vcpu->kvm->arch.config_lock);
1551 	*val = read_id_reg(vcpu, rd);
1552 	mutex_unlock(&vcpu->kvm->arch.config_lock);
1553 
1554 	return 0;
1555 }
1556 
set_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1557 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1558 		      u64 val)
1559 {
1560 	u32 id = reg_to_encoding(rd);
1561 	int ret;
1562 
1563 	mutex_lock(&vcpu->kvm->arch.config_lock);
1564 
1565 	/*
1566 	 * Once the VM has started the ID registers are immutable. Reject any
1567 	 * write that does not match the final register value.
1568 	 */
1569 	if (kvm_vm_has_ran_once(vcpu->kvm)) {
1570 		if (val != read_id_reg(vcpu, rd))
1571 			ret = -EBUSY;
1572 		else
1573 			ret = 0;
1574 
1575 		mutex_unlock(&vcpu->kvm->arch.config_lock);
1576 		return ret;
1577 	}
1578 
1579 	ret = arm64_check_features(vcpu, rd, val);
1580 	if (!ret)
1581 		IDREG(vcpu->kvm, id) = val;
1582 
1583 	mutex_unlock(&vcpu->kvm->arch.config_lock);
1584 
1585 	/*
1586 	 * arm64_check_features() returns -E2BIG to indicate the register's
1587 	 * feature set is a superset of the maximally-allowed register value.
1588 	 * While it would be nice to precisely describe this to userspace, the
1589 	 * existing UAPI for KVM_SET_ONE_REG has it that invalid register
1590 	 * writes return -EINVAL.
1591 	 */
1592 	if (ret == -E2BIG)
1593 		ret = -EINVAL;
1594 	return ret;
1595 }
1596 
get_raz_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)1597 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1598 		       u64 *val)
1599 {
1600 	*val = 0;
1601 	return 0;
1602 }
1603 
set_wi_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1604 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1605 		      u64 val)
1606 {
1607 	return 0;
1608 }
1609 
access_ctr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1610 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1611 		       const struct sys_reg_desc *r)
1612 {
1613 	if (p->is_write)
1614 		return write_to_read_only(vcpu, p, r);
1615 
1616 	p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0);
1617 	return true;
1618 }
1619 
access_clidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1620 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1621 			 const struct sys_reg_desc *r)
1622 {
1623 	if (p->is_write)
1624 		return write_to_read_only(vcpu, p, r);
1625 
1626 	p->regval = __vcpu_sys_reg(vcpu, r->reg);
1627 	return true;
1628 }
1629 
1630 /*
1631  * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary
1632  * by the physical CPU which the vcpu currently resides in.
1633  */
reset_clidr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1634 static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
1635 {
1636 	u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
1637 	u64 clidr;
1638 	u8 loc;
1639 
1640 	if ((ctr_el0 & CTR_EL0_IDC)) {
1641 		/*
1642 		 * Data cache clean to the PoU is not required so LoUU and LoUIS
1643 		 * will not be set and a unified cache, which will be marked as
1644 		 * LoC, will be added.
1645 		 *
1646 		 * If not DIC, let the unified cache L2 so that an instruction
1647 		 * cache can be added as L1 later.
1648 		 */
1649 		loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2;
1650 		clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc);
1651 	} else {
1652 		/*
1653 		 * Data cache clean to the PoU is required so let L1 have a data
1654 		 * cache and mark it as LoUU and LoUIS. As L1 has a data cache,
1655 		 * it can be marked as LoC too.
1656 		 */
1657 		loc = 1;
1658 		clidr = 1 << CLIDR_LOUU_SHIFT;
1659 		clidr |= 1 << CLIDR_LOUIS_SHIFT;
1660 		clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1);
1661 	}
1662 
1663 	/*
1664 	 * Instruction cache invalidation to the PoU is required so let L1 have
1665 	 * an instruction cache. If L1 already has a data cache, it will be
1666 	 * CACHE_TYPE_SEPARATE.
1667 	 */
1668 	if (!(ctr_el0 & CTR_EL0_DIC))
1669 		clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1);
1670 
1671 	clidr |= loc << CLIDR_LOC_SHIFT;
1672 
1673 	/*
1674 	 * Add tag cache unified to data cache. Allocation tags and data are
1675 	 * unified in a cache line so that it looks valid even if there is only
1676 	 * one cache line.
1677 	 */
1678 	if (kvm_has_mte(vcpu->kvm))
1679 		clidr |= 2 << CLIDR_TTYPE_SHIFT(loc);
1680 
1681 	__vcpu_sys_reg(vcpu, r->reg) = clidr;
1682 
1683 	return __vcpu_sys_reg(vcpu, r->reg);
1684 }
1685 
set_clidr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1686 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1687 		      u64 val)
1688 {
1689 	u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
1690 	u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val));
1691 
1692 	if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc))
1693 		return -EINVAL;
1694 
1695 	__vcpu_sys_reg(vcpu, rd->reg) = val;
1696 
1697 	return 0;
1698 }
1699 
access_csselr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1700 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1701 			  const struct sys_reg_desc *r)
1702 {
1703 	int reg = r->reg;
1704 
1705 	if (p->is_write)
1706 		vcpu_write_sys_reg(vcpu, p->regval, reg);
1707 	else
1708 		p->regval = vcpu_read_sys_reg(vcpu, reg);
1709 	return true;
1710 }
1711 
access_ccsidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1712 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1713 			  const struct sys_reg_desc *r)
1714 {
1715 	u32 csselr;
1716 
1717 	if (p->is_write)
1718 		return write_to_read_only(vcpu, p, r);
1719 
1720 	csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
1721 	csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD;
1722 	if (csselr < CSSELR_MAX)
1723 		p->regval = get_ccsidr(vcpu, csselr);
1724 
1725 	return true;
1726 }
1727 
mte_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1728 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu,
1729 				   const struct sys_reg_desc *rd)
1730 {
1731 	if (kvm_has_mte(vcpu->kvm))
1732 		return 0;
1733 
1734 	return REG_HIDDEN;
1735 }
1736 
1737 #define MTE_REG(name) {				\
1738 	SYS_DESC(SYS_##name),			\
1739 	.access = undef_access,			\
1740 	.reset = reset_unknown,			\
1741 	.reg = name,				\
1742 	.visibility = mte_visibility,		\
1743 }
1744 
el2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1745 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu,
1746 				   const struct sys_reg_desc *rd)
1747 {
1748 	if (vcpu_has_nv(vcpu))
1749 		return 0;
1750 
1751 	return REG_HIDDEN;
1752 }
1753 
1754 #define EL2_REG(name, acc, rst, v) {		\
1755 	SYS_DESC(SYS_##name),			\
1756 	.access = acc,				\
1757 	.reset = rst,				\
1758 	.reg = name,				\
1759 	.visibility = el2_visibility,		\
1760 	.val = v,				\
1761 }
1762 
1763 /*
1764  * EL{0,1}2 registers are the EL2 view on an EL0 or EL1 register when
1765  * HCR_EL2.E2H==1, and only in the sysreg table for convenience of
1766  * handling traps. Given that, they are always hidden from userspace.
1767  */
elx2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1768 static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu,
1769 				    const struct sys_reg_desc *rd)
1770 {
1771 	return REG_HIDDEN_USER;
1772 }
1773 
1774 #define EL12_REG(name, acc, rst, v) {		\
1775 	SYS_DESC(SYS_##name##_EL12),		\
1776 	.access = acc,				\
1777 	.reset = rst,				\
1778 	.reg = name##_EL1,			\
1779 	.val = v,				\
1780 	.visibility = elx2_visibility,		\
1781 }
1782 
1783 /*
1784  * Since reset() callback and field val are not used for idregs, they will be
1785  * used for specific purposes for idregs.
1786  * The reset() would return KVM sanitised register value. The value would be the
1787  * same as the host kernel sanitised value if there is no KVM sanitisation.
1788  * The val would be used as a mask indicating writable fields for the idreg.
1789  * Only bits with 1 are writable from userspace. This mask might not be
1790  * necessary in the future whenever all ID registers are enabled as writable
1791  * from userspace.
1792  */
1793 
1794 /* sys_reg_desc initialiser for known cpufeature ID registers */
1795 #define ID_SANITISED(name) {			\
1796 	SYS_DESC(SYS_##name),			\
1797 	.access	= access_id_reg,		\
1798 	.get_user = get_id_reg,			\
1799 	.set_user = set_id_reg,			\
1800 	.visibility = id_visibility,		\
1801 	.reset = kvm_read_sanitised_id_reg,	\
1802 	.val = 0,				\
1803 }
1804 
1805 /* sys_reg_desc initialiser for known cpufeature ID registers */
1806 #define AA32_ID_SANITISED(name) {		\
1807 	SYS_DESC(SYS_##name),			\
1808 	.access	= access_id_reg,		\
1809 	.get_user = get_id_reg,			\
1810 	.set_user = set_id_reg,			\
1811 	.visibility = aa32_id_visibility,	\
1812 	.reset = kvm_read_sanitised_id_reg,	\
1813 	.val = 0,				\
1814 }
1815 
1816 /*
1817  * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
1818  * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1819  * (1 <= crm < 8, 0 <= Op2 < 8).
1820  */
1821 #define ID_UNALLOCATED(crm, op2) {			\
1822 	Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2),	\
1823 	.access = access_id_reg,			\
1824 	.get_user = get_id_reg,				\
1825 	.set_user = set_id_reg,				\
1826 	.visibility = raz_visibility,			\
1827 	.reset = kvm_read_sanitised_id_reg,		\
1828 	.val = 0,					\
1829 }
1830 
1831 /*
1832  * sys_reg_desc initialiser for known ID registers that we hide from guests.
1833  * For now, these are exposed just like unallocated ID regs: they appear
1834  * RAZ for the guest.
1835  */
1836 #define ID_HIDDEN(name) {			\
1837 	SYS_DESC(SYS_##name),			\
1838 	.access = access_id_reg,		\
1839 	.get_user = get_id_reg,			\
1840 	.set_user = set_id_reg,			\
1841 	.visibility = raz_visibility,		\
1842 	.reset = kvm_read_sanitised_id_reg,	\
1843 	.val = 0,				\
1844 }
1845 
access_sp_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1846 static bool access_sp_el1(struct kvm_vcpu *vcpu,
1847 			  struct sys_reg_params *p,
1848 			  const struct sys_reg_desc *r)
1849 {
1850 	if (p->is_write)
1851 		__vcpu_sys_reg(vcpu, SP_EL1) = p->regval;
1852 	else
1853 		p->regval = __vcpu_sys_reg(vcpu, SP_EL1);
1854 
1855 	return true;
1856 }
1857 
access_elr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1858 static bool access_elr(struct kvm_vcpu *vcpu,
1859 		       struct sys_reg_params *p,
1860 		       const struct sys_reg_desc *r)
1861 {
1862 	if (p->is_write)
1863 		vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1);
1864 	else
1865 		p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1);
1866 
1867 	return true;
1868 }
1869 
access_spsr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1870 static bool access_spsr(struct kvm_vcpu *vcpu,
1871 			struct sys_reg_params *p,
1872 			const struct sys_reg_desc *r)
1873 {
1874 	if (p->is_write)
1875 		__vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval;
1876 	else
1877 		p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1);
1878 
1879 	return true;
1880 }
1881 
1882 /*
1883  * Architected system registers.
1884  * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
1885  *
1886  * Debug handling: We do trap most, if not all debug related system
1887  * registers. The implementation is good enough to ensure that a guest
1888  * can use these with minimal performance degradation. The drawback is
1889  * that we don't implement any of the external debug architecture.
1890  * This should be revisited if we ever encounter a more demanding
1891  * guest...
1892  */
1893 static const struct sys_reg_desc sys_reg_descs[] = {
1894 	{ SYS_DESC(SYS_DC_ISW), access_dcsw },
1895 	{ SYS_DESC(SYS_DC_IGSW), access_dcgsw },
1896 	{ SYS_DESC(SYS_DC_IGDSW), access_dcgsw },
1897 	{ SYS_DESC(SYS_DC_CSW), access_dcsw },
1898 	{ SYS_DESC(SYS_DC_CGSW), access_dcgsw },
1899 	{ SYS_DESC(SYS_DC_CGDSW), access_dcgsw },
1900 	{ SYS_DESC(SYS_DC_CISW), access_dcsw },
1901 	{ SYS_DESC(SYS_DC_CIGSW), access_dcgsw },
1902 	{ SYS_DESC(SYS_DC_CIGDSW), access_dcgsw },
1903 
1904 	DBG_BCR_BVR_WCR_WVR_EL1(0),
1905 	DBG_BCR_BVR_WCR_WVR_EL1(1),
1906 	{ SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
1907 	{ SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
1908 	DBG_BCR_BVR_WCR_WVR_EL1(2),
1909 	DBG_BCR_BVR_WCR_WVR_EL1(3),
1910 	DBG_BCR_BVR_WCR_WVR_EL1(4),
1911 	DBG_BCR_BVR_WCR_WVR_EL1(5),
1912 	DBG_BCR_BVR_WCR_WVR_EL1(6),
1913 	DBG_BCR_BVR_WCR_WVR_EL1(7),
1914 	DBG_BCR_BVR_WCR_WVR_EL1(8),
1915 	DBG_BCR_BVR_WCR_WVR_EL1(9),
1916 	DBG_BCR_BVR_WCR_WVR_EL1(10),
1917 	DBG_BCR_BVR_WCR_WVR_EL1(11),
1918 	DBG_BCR_BVR_WCR_WVR_EL1(12),
1919 	DBG_BCR_BVR_WCR_WVR_EL1(13),
1920 	DBG_BCR_BVR_WCR_WVR_EL1(14),
1921 	DBG_BCR_BVR_WCR_WVR_EL1(15),
1922 
1923 	{ SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
1924 	{ SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 },
1925 	{ SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1,
1926 		OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, },
1927 	{ SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
1928 	{ SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
1929 	{ SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
1930 	{ SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
1931 	{ SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
1932 
1933 	{ SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
1934 	{ SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
1935 	// DBGDTR[TR]X_EL0 share the same encoding
1936 	{ SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
1937 
1938 	{ SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
1939 
1940 	{ SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
1941 
1942 	/*
1943 	 * ID regs: all ID_SANITISED() entries here must have corresponding
1944 	 * entries in arm64_ftr_regs[].
1945 	 */
1946 
1947 	/* AArch64 mappings of the AArch32 ID registers */
1948 	/* CRm=1 */
1949 	AA32_ID_SANITISED(ID_PFR0_EL1),
1950 	AA32_ID_SANITISED(ID_PFR1_EL1),
1951 	{ SYS_DESC(SYS_ID_DFR0_EL1),
1952 	  .access = access_id_reg,
1953 	  .get_user = get_id_reg,
1954 	  .set_user = set_id_dfr0_el1,
1955 	  .visibility = aa32_id_visibility,
1956 	  .reset = read_sanitised_id_dfr0_el1,
1957 	  .val = ID_DFR0_EL1_PerfMon_MASK, },
1958 	ID_HIDDEN(ID_AFR0_EL1),
1959 	AA32_ID_SANITISED(ID_MMFR0_EL1),
1960 	AA32_ID_SANITISED(ID_MMFR1_EL1),
1961 	AA32_ID_SANITISED(ID_MMFR2_EL1),
1962 	AA32_ID_SANITISED(ID_MMFR3_EL1),
1963 
1964 	/* CRm=2 */
1965 	AA32_ID_SANITISED(ID_ISAR0_EL1),
1966 	AA32_ID_SANITISED(ID_ISAR1_EL1),
1967 	AA32_ID_SANITISED(ID_ISAR2_EL1),
1968 	AA32_ID_SANITISED(ID_ISAR3_EL1),
1969 	AA32_ID_SANITISED(ID_ISAR4_EL1),
1970 	AA32_ID_SANITISED(ID_ISAR5_EL1),
1971 	AA32_ID_SANITISED(ID_MMFR4_EL1),
1972 	AA32_ID_SANITISED(ID_ISAR6_EL1),
1973 
1974 	/* CRm=3 */
1975 	AA32_ID_SANITISED(MVFR0_EL1),
1976 	AA32_ID_SANITISED(MVFR1_EL1),
1977 	AA32_ID_SANITISED(MVFR2_EL1),
1978 	ID_UNALLOCATED(3,3),
1979 	AA32_ID_SANITISED(ID_PFR2_EL1),
1980 	ID_HIDDEN(ID_DFR1_EL1),
1981 	AA32_ID_SANITISED(ID_MMFR5_EL1),
1982 	ID_UNALLOCATED(3,7),
1983 
1984 	/* AArch64 ID registers */
1985 	/* CRm=4 */
1986 	{ SYS_DESC(SYS_ID_AA64PFR0_EL1),
1987 	  .access = access_id_reg,
1988 	  .get_user = get_id_reg,
1989 	  .set_user = set_id_reg,
1990 	  .reset = read_sanitised_id_aa64pfr0_el1,
1991 	  .val = ID_AA64PFR0_EL1_CSV2_MASK | ID_AA64PFR0_EL1_CSV3_MASK, },
1992 	ID_SANITISED(ID_AA64PFR1_EL1),
1993 	ID_UNALLOCATED(4,2),
1994 	ID_UNALLOCATED(4,3),
1995 	ID_SANITISED(ID_AA64ZFR0_EL1),
1996 	ID_HIDDEN(ID_AA64SMFR0_EL1),
1997 	ID_UNALLOCATED(4,6),
1998 	ID_UNALLOCATED(4,7),
1999 
2000 	/* CRm=5 */
2001 	{ SYS_DESC(SYS_ID_AA64DFR0_EL1),
2002 	  .access = access_id_reg,
2003 	  .get_user = get_id_reg,
2004 	  .set_user = set_id_aa64dfr0_el1,
2005 	  .reset = read_sanitised_id_aa64dfr0_el1,
2006 	  .val = ID_AA64DFR0_EL1_PMUVer_MASK, },
2007 	ID_SANITISED(ID_AA64DFR1_EL1),
2008 	ID_UNALLOCATED(5,2),
2009 	ID_UNALLOCATED(5,3),
2010 	ID_HIDDEN(ID_AA64AFR0_EL1),
2011 	ID_HIDDEN(ID_AA64AFR1_EL1),
2012 	ID_UNALLOCATED(5,6),
2013 	ID_UNALLOCATED(5,7),
2014 
2015 	/* CRm=6 */
2016 	ID_SANITISED(ID_AA64ISAR0_EL1),
2017 	ID_SANITISED(ID_AA64ISAR1_EL1),
2018 	ID_SANITISED(ID_AA64ISAR2_EL1),
2019 	ID_UNALLOCATED(6,3),
2020 	ID_UNALLOCATED(6,4),
2021 	ID_UNALLOCATED(6,5),
2022 	ID_UNALLOCATED(6,6),
2023 	ID_UNALLOCATED(6,7),
2024 
2025 	/* CRm=7 */
2026 	ID_SANITISED(ID_AA64MMFR0_EL1),
2027 	ID_SANITISED(ID_AA64MMFR1_EL1),
2028 	ID_SANITISED(ID_AA64MMFR2_EL1),
2029 	ID_SANITISED(ID_AA64MMFR3_EL1),
2030 	ID_UNALLOCATED(7,4),
2031 	ID_UNALLOCATED(7,5),
2032 	ID_UNALLOCATED(7,6),
2033 	ID_UNALLOCATED(7,7),
2034 
2035 	{ SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
2036 	{ SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
2037 	{ SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
2038 
2039 	MTE_REG(RGSR_EL1),
2040 	MTE_REG(GCR_EL1),
2041 
2042 	{ SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
2043 	{ SYS_DESC(SYS_TRFCR_EL1), undef_access },
2044 	{ SYS_DESC(SYS_SMPRI_EL1), undef_access },
2045 	{ SYS_DESC(SYS_SMCR_EL1), undef_access },
2046 	{ SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
2047 	{ SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
2048 	{ SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
2049 	{ SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0 },
2050 
2051 	PTRAUTH_KEY(APIA),
2052 	PTRAUTH_KEY(APIB),
2053 	PTRAUTH_KEY(APDA),
2054 	PTRAUTH_KEY(APDB),
2055 	PTRAUTH_KEY(APGA),
2056 
2057 	{ SYS_DESC(SYS_SPSR_EL1), access_spsr},
2058 	{ SYS_DESC(SYS_ELR_EL1), access_elr},
2059 
2060 	{ SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
2061 	{ SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
2062 	{ SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
2063 
2064 	{ SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
2065 	{ SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
2066 	{ SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
2067 	{ SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
2068 	{ SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
2069 	{ SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
2070 	{ SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
2071 	{ SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
2072 
2073 	MTE_REG(TFSR_EL1),
2074 	MTE_REG(TFSRE0_EL1),
2075 
2076 	{ SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
2077 	{ SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
2078 
2079 	{ SYS_DESC(SYS_PMSCR_EL1), undef_access },
2080 	{ SYS_DESC(SYS_PMSNEVFR_EL1), undef_access },
2081 	{ SYS_DESC(SYS_PMSICR_EL1), undef_access },
2082 	{ SYS_DESC(SYS_PMSIRR_EL1), undef_access },
2083 	{ SYS_DESC(SYS_PMSFCR_EL1), undef_access },
2084 	{ SYS_DESC(SYS_PMSEVFR_EL1), undef_access },
2085 	{ SYS_DESC(SYS_PMSLATFR_EL1), undef_access },
2086 	{ SYS_DESC(SYS_PMSIDR_EL1), undef_access },
2087 	{ SYS_DESC(SYS_PMBLIMITR_EL1), undef_access },
2088 	{ SYS_DESC(SYS_PMBPTR_EL1), undef_access },
2089 	{ SYS_DESC(SYS_PMBSR_EL1), undef_access },
2090 	/* PMBIDR_EL1 is not trapped */
2091 
2092 	{ PMU_SYS_REG(PMINTENSET_EL1),
2093 	  .access = access_pminten, .reg = PMINTENSET_EL1 },
2094 	{ PMU_SYS_REG(PMINTENCLR_EL1),
2095 	  .access = access_pminten, .reg = PMINTENSET_EL1 },
2096 	{ SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi },
2097 
2098 	{ SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
2099 	{ SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1 },
2100 	{ SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1 },
2101 	{ SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
2102 
2103 	{ SYS_DESC(SYS_LORSA_EL1), trap_loregion },
2104 	{ SYS_DESC(SYS_LOREA_EL1), trap_loregion },
2105 	{ SYS_DESC(SYS_LORN_EL1), trap_loregion },
2106 	{ SYS_DESC(SYS_LORC_EL1), trap_loregion },
2107 	{ SYS_DESC(SYS_LORID_EL1), trap_loregion },
2108 
2109 	{ SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 },
2110 	{ SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
2111 
2112 	{ SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
2113 	{ SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
2114 	{ SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
2115 	{ SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
2116 	{ SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
2117 	{ SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
2118 	{ SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
2119 	{ SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
2120 	{ SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
2121 	{ SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
2122 	{ SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
2123 	{ SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
2124 
2125 	{ SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
2126 	{ SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
2127 
2128 	{ SYS_DESC(SYS_ACCDATA_EL1), undef_access },
2129 
2130 	{ SYS_DESC(SYS_SCXTNUM_EL1), undef_access },
2131 
2132 	{ SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
2133 
2134 	{ SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
2135 	{ SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1,
2136 	  .set_user = set_clidr },
2137 	{ SYS_DESC(SYS_CCSIDR2_EL1), undef_access },
2138 	{ SYS_DESC(SYS_SMIDR_EL1), undef_access },
2139 	{ SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
2140 	{ SYS_DESC(SYS_CTR_EL0), access_ctr },
2141 	{ SYS_DESC(SYS_SVCR), undef_access },
2142 
2143 	{ PMU_SYS_REG(PMCR_EL0), .access = access_pmcr,
2144 	  .reset = reset_pmcr, .reg = PMCR_EL0 },
2145 	{ PMU_SYS_REG(PMCNTENSET_EL0),
2146 	  .access = access_pmcnten, .reg = PMCNTENSET_EL0 },
2147 	{ PMU_SYS_REG(PMCNTENCLR_EL0),
2148 	  .access = access_pmcnten, .reg = PMCNTENSET_EL0 },
2149 	{ PMU_SYS_REG(PMOVSCLR_EL0),
2150 	  .access = access_pmovs, .reg = PMOVSSET_EL0 },
2151 	/*
2152 	 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was
2153 	 * previously (and pointlessly) advertised in the past...
2154 	 */
2155 	{ PMU_SYS_REG(PMSWINC_EL0),
2156 	  .get_user = get_raz_reg, .set_user = set_wi_reg,
2157 	  .access = access_pmswinc, .reset = NULL },
2158 	{ PMU_SYS_REG(PMSELR_EL0),
2159 	  .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 },
2160 	{ PMU_SYS_REG(PMCEID0_EL0),
2161 	  .access = access_pmceid, .reset = NULL },
2162 	{ PMU_SYS_REG(PMCEID1_EL0),
2163 	  .access = access_pmceid, .reset = NULL },
2164 	{ PMU_SYS_REG(PMCCNTR_EL0),
2165 	  .access = access_pmu_evcntr, .reset = reset_unknown,
2166 	  .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr},
2167 	{ PMU_SYS_REG(PMXEVTYPER_EL0),
2168 	  .access = access_pmu_evtyper, .reset = NULL },
2169 	{ PMU_SYS_REG(PMXEVCNTR_EL0),
2170 	  .access = access_pmu_evcntr, .reset = NULL },
2171 	/*
2172 	 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
2173 	 * in 32bit mode. Here we choose to reset it as zero for consistency.
2174 	 */
2175 	{ PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr,
2176 	  .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 },
2177 	{ PMU_SYS_REG(PMOVSSET_EL0),
2178 	  .access = access_pmovs, .reg = PMOVSSET_EL0 },
2179 
2180 	{ SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
2181 	{ SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
2182 	{ SYS_DESC(SYS_TPIDR2_EL0), undef_access },
2183 
2184 	{ SYS_DESC(SYS_SCXTNUM_EL0), undef_access },
2185 
2186 	{ SYS_DESC(SYS_AMCR_EL0), undef_access },
2187 	{ SYS_DESC(SYS_AMCFGR_EL0), undef_access },
2188 	{ SYS_DESC(SYS_AMCGCR_EL0), undef_access },
2189 	{ SYS_DESC(SYS_AMUSERENR_EL0), undef_access },
2190 	{ SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access },
2191 	{ SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access },
2192 	{ SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access },
2193 	{ SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access },
2194 	AMU_AMEVCNTR0_EL0(0),
2195 	AMU_AMEVCNTR0_EL0(1),
2196 	AMU_AMEVCNTR0_EL0(2),
2197 	AMU_AMEVCNTR0_EL0(3),
2198 	AMU_AMEVCNTR0_EL0(4),
2199 	AMU_AMEVCNTR0_EL0(5),
2200 	AMU_AMEVCNTR0_EL0(6),
2201 	AMU_AMEVCNTR0_EL0(7),
2202 	AMU_AMEVCNTR0_EL0(8),
2203 	AMU_AMEVCNTR0_EL0(9),
2204 	AMU_AMEVCNTR0_EL0(10),
2205 	AMU_AMEVCNTR0_EL0(11),
2206 	AMU_AMEVCNTR0_EL0(12),
2207 	AMU_AMEVCNTR0_EL0(13),
2208 	AMU_AMEVCNTR0_EL0(14),
2209 	AMU_AMEVCNTR0_EL0(15),
2210 	AMU_AMEVTYPER0_EL0(0),
2211 	AMU_AMEVTYPER0_EL0(1),
2212 	AMU_AMEVTYPER0_EL0(2),
2213 	AMU_AMEVTYPER0_EL0(3),
2214 	AMU_AMEVTYPER0_EL0(4),
2215 	AMU_AMEVTYPER0_EL0(5),
2216 	AMU_AMEVTYPER0_EL0(6),
2217 	AMU_AMEVTYPER0_EL0(7),
2218 	AMU_AMEVTYPER0_EL0(8),
2219 	AMU_AMEVTYPER0_EL0(9),
2220 	AMU_AMEVTYPER0_EL0(10),
2221 	AMU_AMEVTYPER0_EL0(11),
2222 	AMU_AMEVTYPER0_EL0(12),
2223 	AMU_AMEVTYPER0_EL0(13),
2224 	AMU_AMEVTYPER0_EL0(14),
2225 	AMU_AMEVTYPER0_EL0(15),
2226 	AMU_AMEVCNTR1_EL0(0),
2227 	AMU_AMEVCNTR1_EL0(1),
2228 	AMU_AMEVCNTR1_EL0(2),
2229 	AMU_AMEVCNTR1_EL0(3),
2230 	AMU_AMEVCNTR1_EL0(4),
2231 	AMU_AMEVCNTR1_EL0(5),
2232 	AMU_AMEVCNTR1_EL0(6),
2233 	AMU_AMEVCNTR1_EL0(7),
2234 	AMU_AMEVCNTR1_EL0(8),
2235 	AMU_AMEVCNTR1_EL0(9),
2236 	AMU_AMEVCNTR1_EL0(10),
2237 	AMU_AMEVCNTR1_EL0(11),
2238 	AMU_AMEVCNTR1_EL0(12),
2239 	AMU_AMEVCNTR1_EL0(13),
2240 	AMU_AMEVCNTR1_EL0(14),
2241 	AMU_AMEVCNTR1_EL0(15),
2242 	AMU_AMEVTYPER1_EL0(0),
2243 	AMU_AMEVTYPER1_EL0(1),
2244 	AMU_AMEVTYPER1_EL0(2),
2245 	AMU_AMEVTYPER1_EL0(3),
2246 	AMU_AMEVTYPER1_EL0(4),
2247 	AMU_AMEVTYPER1_EL0(5),
2248 	AMU_AMEVTYPER1_EL0(6),
2249 	AMU_AMEVTYPER1_EL0(7),
2250 	AMU_AMEVTYPER1_EL0(8),
2251 	AMU_AMEVTYPER1_EL0(9),
2252 	AMU_AMEVTYPER1_EL0(10),
2253 	AMU_AMEVTYPER1_EL0(11),
2254 	AMU_AMEVTYPER1_EL0(12),
2255 	AMU_AMEVTYPER1_EL0(13),
2256 	AMU_AMEVTYPER1_EL0(14),
2257 	AMU_AMEVTYPER1_EL0(15),
2258 
2259 	{ SYS_DESC(SYS_CNTPCT_EL0), access_arch_timer },
2260 	{ SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer },
2261 	{ SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
2262 	{ SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
2263 	{ SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
2264 
2265 	/* PMEVCNTRn_EL0 */
2266 	PMU_PMEVCNTR_EL0(0),
2267 	PMU_PMEVCNTR_EL0(1),
2268 	PMU_PMEVCNTR_EL0(2),
2269 	PMU_PMEVCNTR_EL0(3),
2270 	PMU_PMEVCNTR_EL0(4),
2271 	PMU_PMEVCNTR_EL0(5),
2272 	PMU_PMEVCNTR_EL0(6),
2273 	PMU_PMEVCNTR_EL0(7),
2274 	PMU_PMEVCNTR_EL0(8),
2275 	PMU_PMEVCNTR_EL0(9),
2276 	PMU_PMEVCNTR_EL0(10),
2277 	PMU_PMEVCNTR_EL0(11),
2278 	PMU_PMEVCNTR_EL0(12),
2279 	PMU_PMEVCNTR_EL0(13),
2280 	PMU_PMEVCNTR_EL0(14),
2281 	PMU_PMEVCNTR_EL0(15),
2282 	PMU_PMEVCNTR_EL0(16),
2283 	PMU_PMEVCNTR_EL0(17),
2284 	PMU_PMEVCNTR_EL0(18),
2285 	PMU_PMEVCNTR_EL0(19),
2286 	PMU_PMEVCNTR_EL0(20),
2287 	PMU_PMEVCNTR_EL0(21),
2288 	PMU_PMEVCNTR_EL0(22),
2289 	PMU_PMEVCNTR_EL0(23),
2290 	PMU_PMEVCNTR_EL0(24),
2291 	PMU_PMEVCNTR_EL0(25),
2292 	PMU_PMEVCNTR_EL0(26),
2293 	PMU_PMEVCNTR_EL0(27),
2294 	PMU_PMEVCNTR_EL0(28),
2295 	PMU_PMEVCNTR_EL0(29),
2296 	PMU_PMEVCNTR_EL0(30),
2297 	/* PMEVTYPERn_EL0 */
2298 	PMU_PMEVTYPER_EL0(0),
2299 	PMU_PMEVTYPER_EL0(1),
2300 	PMU_PMEVTYPER_EL0(2),
2301 	PMU_PMEVTYPER_EL0(3),
2302 	PMU_PMEVTYPER_EL0(4),
2303 	PMU_PMEVTYPER_EL0(5),
2304 	PMU_PMEVTYPER_EL0(6),
2305 	PMU_PMEVTYPER_EL0(7),
2306 	PMU_PMEVTYPER_EL0(8),
2307 	PMU_PMEVTYPER_EL0(9),
2308 	PMU_PMEVTYPER_EL0(10),
2309 	PMU_PMEVTYPER_EL0(11),
2310 	PMU_PMEVTYPER_EL0(12),
2311 	PMU_PMEVTYPER_EL0(13),
2312 	PMU_PMEVTYPER_EL0(14),
2313 	PMU_PMEVTYPER_EL0(15),
2314 	PMU_PMEVTYPER_EL0(16),
2315 	PMU_PMEVTYPER_EL0(17),
2316 	PMU_PMEVTYPER_EL0(18),
2317 	PMU_PMEVTYPER_EL0(19),
2318 	PMU_PMEVTYPER_EL0(20),
2319 	PMU_PMEVTYPER_EL0(21),
2320 	PMU_PMEVTYPER_EL0(22),
2321 	PMU_PMEVTYPER_EL0(23),
2322 	PMU_PMEVTYPER_EL0(24),
2323 	PMU_PMEVTYPER_EL0(25),
2324 	PMU_PMEVTYPER_EL0(26),
2325 	PMU_PMEVTYPER_EL0(27),
2326 	PMU_PMEVTYPER_EL0(28),
2327 	PMU_PMEVTYPER_EL0(29),
2328 	PMU_PMEVTYPER_EL0(30),
2329 	/*
2330 	 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
2331 	 * in 32bit mode. Here we choose to reset it as zero for consistency.
2332 	 */
2333 	{ PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper,
2334 	  .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 },
2335 
2336 	EL2_REG(VPIDR_EL2, access_rw, reset_unknown, 0),
2337 	EL2_REG(VMPIDR_EL2, access_rw, reset_unknown, 0),
2338 	EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1),
2339 	EL2_REG(ACTLR_EL2, access_rw, reset_val, 0),
2340 	EL2_REG(HCR_EL2, access_rw, reset_val, 0),
2341 	EL2_REG(MDCR_EL2, access_rw, reset_val, 0),
2342 	EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1),
2343 	EL2_REG(HSTR_EL2, access_rw, reset_val, 0),
2344 	EL2_REG(HFGRTR_EL2, access_rw, reset_val, 0),
2345 	EL2_REG(HFGWTR_EL2, access_rw, reset_val, 0),
2346 	EL2_REG(HFGITR_EL2, access_rw, reset_val, 0),
2347 	EL2_REG(HACR_EL2, access_rw, reset_val, 0),
2348 
2349 	EL2_REG(HCRX_EL2, access_rw, reset_val, 0),
2350 
2351 	EL2_REG(TTBR0_EL2, access_rw, reset_val, 0),
2352 	EL2_REG(TTBR1_EL2, access_rw, reset_val, 0),
2353 	EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1),
2354 	EL2_REG(VTTBR_EL2, access_rw, reset_val, 0),
2355 	EL2_REG(VTCR_EL2, access_rw, reset_val, 0),
2356 
2357 	{ SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
2358 	EL2_REG(HDFGRTR_EL2, access_rw, reset_val, 0),
2359 	EL2_REG(HDFGWTR_EL2, access_rw, reset_val, 0),
2360 	EL2_REG(HAFGRTR_EL2, access_rw, reset_val, 0),
2361 	EL2_REG(SPSR_EL2, access_rw, reset_val, 0),
2362 	EL2_REG(ELR_EL2, access_rw, reset_val, 0),
2363 	{ SYS_DESC(SYS_SP_EL1), access_sp_el1},
2364 
2365 	{ SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
2366 	EL2_REG(AFSR0_EL2, access_rw, reset_val, 0),
2367 	EL2_REG(AFSR1_EL2, access_rw, reset_val, 0),
2368 	EL2_REG(ESR_EL2, access_rw, reset_val, 0),
2369 	{ SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
2370 
2371 	EL2_REG(FAR_EL2, access_rw, reset_val, 0),
2372 	EL2_REG(HPFAR_EL2, access_rw, reset_val, 0),
2373 
2374 	EL2_REG(MAIR_EL2, access_rw, reset_val, 0),
2375 	EL2_REG(AMAIR_EL2, access_rw, reset_val, 0),
2376 
2377 	EL2_REG(VBAR_EL2, access_rw, reset_val, 0),
2378 	EL2_REG(RVBAR_EL2, access_rw, reset_val, 0),
2379 	{ SYS_DESC(SYS_RMR_EL2), trap_undef },
2380 
2381 	EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0),
2382 	EL2_REG(TPIDR_EL2, access_rw, reset_val, 0),
2383 
2384 	EL2_REG(CNTVOFF_EL2, access_rw, reset_val, 0),
2385 	EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0),
2386 
2387 	EL12_REG(SCTLR, access_vm_reg, reset_val, 0x00C50078),
2388 	EL12_REG(CPACR, access_rw, reset_val, 0),
2389 	EL12_REG(TTBR0, access_vm_reg, reset_unknown, 0),
2390 	EL12_REG(TTBR1, access_vm_reg, reset_unknown, 0),
2391 	EL12_REG(TCR, access_vm_reg, reset_val, 0),
2392 	{ SYS_DESC(SYS_SPSR_EL12), access_spsr},
2393 	{ SYS_DESC(SYS_ELR_EL12), access_elr},
2394 	EL12_REG(AFSR0, access_vm_reg, reset_unknown, 0),
2395 	EL12_REG(AFSR1, access_vm_reg, reset_unknown, 0),
2396 	EL12_REG(ESR, access_vm_reg, reset_unknown, 0),
2397 	EL12_REG(FAR, access_vm_reg, reset_unknown, 0),
2398 	EL12_REG(MAIR, access_vm_reg, reset_unknown, 0),
2399 	EL12_REG(AMAIR, access_vm_reg, reset_amair_el1, 0),
2400 	EL12_REG(VBAR, access_rw, reset_val, 0),
2401 	EL12_REG(CONTEXTIDR, access_vm_reg, reset_val, 0),
2402 	EL12_REG(CNTKCTL, access_rw, reset_val, 0),
2403 
2404 	EL2_REG(SP_EL2, NULL, reset_unknown, 0),
2405 };
2406 
2407 static const struct sys_reg_desc *first_idreg;
2408 
trap_dbgdidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2409 static bool trap_dbgdidr(struct kvm_vcpu *vcpu,
2410 			struct sys_reg_params *p,
2411 			const struct sys_reg_desc *r)
2412 {
2413 	if (p->is_write) {
2414 		return ignore_write(vcpu, p);
2415 	} else {
2416 		u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
2417 		u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
2418 		u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL1_EL3_SHIFT);
2419 
2420 		p->regval = ((((dfr >> ID_AA64DFR0_EL1_WRPs_SHIFT) & 0xf) << 28) |
2421 			     (((dfr >> ID_AA64DFR0_EL1_BRPs_SHIFT) & 0xf) << 24) |
2422 			     (((dfr >> ID_AA64DFR0_EL1_CTX_CMPs_SHIFT) & 0xf) << 20)
2423 			     | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12));
2424 		return true;
2425 	}
2426 }
2427 
2428 /*
2429  * AArch32 debug register mappings
2430  *
2431  * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
2432  * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
2433  *
2434  * None of the other registers share their location, so treat them as
2435  * if they were 64bit.
2436  */
2437 #define DBG_BCR_BVR_WCR_WVR(n)						      \
2438 	/* DBGBVRn */							      \
2439 	{ AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
2440 	/* DBGBCRn */							      \
2441 	{ Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n },	      \
2442 	/* DBGWVRn */							      \
2443 	{ Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n },	      \
2444 	/* DBGWCRn */							      \
2445 	{ Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
2446 
2447 #define DBGBXVR(n)							      \
2448 	{ AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n }
2449 
2450 /*
2451  * Trapped cp14 registers. We generally ignore most of the external
2452  * debug, on the principle that they don't really make sense to a
2453  * guest. Revisit this one day, would this principle change.
2454  */
2455 static const struct sys_reg_desc cp14_regs[] = {
2456 	/* DBGDIDR */
2457 	{ Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },
2458 	/* DBGDTRRXext */
2459 	{ Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
2460 
2461 	DBG_BCR_BVR_WCR_WVR(0),
2462 	/* DBGDSCRint */
2463 	{ Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
2464 	DBG_BCR_BVR_WCR_WVR(1),
2465 	/* DBGDCCINT */
2466 	{ Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 },
2467 	/* DBGDSCRext */
2468 	{ Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 },
2469 	DBG_BCR_BVR_WCR_WVR(2),
2470 	/* DBGDTR[RT]Xint */
2471 	{ Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
2472 	/* DBGDTR[RT]Xext */
2473 	{ Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
2474 	DBG_BCR_BVR_WCR_WVR(3),
2475 	DBG_BCR_BVR_WCR_WVR(4),
2476 	DBG_BCR_BVR_WCR_WVR(5),
2477 	/* DBGWFAR */
2478 	{ Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
2479 	/* DBGOSECCR */
2480 	{ Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
2481 	DBG_BCR_BVR_WCR_WVR(6),
2482 	/* DBGVCR */
2483 	{ Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 },
2484 	DBG_BCR_BVR_WCR_WVR(7),
2485 	DBG_BCR_BVR_WCR_WVR(8),
2486 	DBG_BCR_BVR_WCR_WVR(9),
2487 	DBG_BCR_BVR_WCR_WVR(10),
2488 	DBG_BCR_BVR_WCR_WVR(11),
2489 	DBG_BCR_BVR_WCR_WVR(12),
2490 	DBG_BCR_BVR_WCR_WVR(13),
2491 	DBG_BCR_BVR_WCR_WVR(14),
2492 	DBG_BCR_BVR_WCR_WVR(15),
2493 
2494 	/* DBGDRAR (32bit) */
2495 	{ Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
2496 
2497 	DBGBXVR(0),
2498 	/* DBGOSLAR */
2499 	{ Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 },
2500 	DBGBXVR(1),
2501 	/* DBGOSLSR */
2502 	{ Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 },
2503 	DBGBXVR(2),
2504 	DBGBXVR(3),
2505 	/* DBGOSDLR */
2506 	{ Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
2507 	DBGBXVR(4),
2508 	/* DBGPRCR */
2509 	{ Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
2510 	DBGBXVR(5),
2511 	DBGBXVR(6),
2512 	DBGBXVR(7),
2513 	DBGBXVR(8),
2514 	DBGBXVR(9),
2515 	DBGBXVR(10),
2516 	DBGBXVR(11),
2517 	DBGBXVR(12),
2518 	DBGBXVR(13),
2519 	DBGBXVR(14),
2520 	DBGBXVR(15),
2521 
2522 	/* DBGDSAR (32bit) */
2523 	{ Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
2524 
2525 	/* DBGDEVID2 */
2526 	{ Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
2527 	/* DBGDEVID1 */
2528 	{ Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
2529 	/* DBGDEVID */
2530 	{ Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
2531 	/* DBGCLAIMSET */
2532 	{ Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
2533 	/* DBGCLAIMCLR */
2534 	{ Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
2535 	/* DBGAUTHSTATUS */
2536 	{ Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
2537 };
2538 
2539 /* Trapped cp14 64bit registers */
2540 static const struct sys_reg_desc cp14_64_regs[] = {
2541 	/* DBGDRAR (64bit) */
2542 	{ Op1( 0), CRm( 1), .access = trap_raz_wi },
2543 
2544 	/* DBGDSAR (64bit) */
2545 	{ Op1( 0), CRm( 2), .access = trap_raz_wi },
2546 };
2547 
2548 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2)			\
2549 	AA32(_map),							\
2550 	Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2),			\
2551 	.visibility = pmu_visibility
2552 
2553 /* Macro to expand the PMEVCNTRn register */
2554 #define PMU_PMEVCNTR(n)							\
2555 	{ CP15_PMU_SYS_REG(DIRECT, 0, 0b1110,				\
2556 	  (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)),			\
2557 	  .access = access_pmu_evcntr }
2558 
2559 /* Macro to expand the PMEVTYPERn register */
2560 #define PMU_PMEVTYPER(n)						\
2561 	{ CP15_PMU_SYS_REG(DIRECT, 0, 0b1110,				\
2562 	  (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)),			\
2563 	  .access = access_pmu_evtyper }
2564 /*
2565  * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
2566  * depending on the way they are accessed (as a 32bit or a 64bit
2567  * register).
2568  */
2569 static const struct sys_reg_desc cp15_regs[] = {
2570 	{ Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
2571 	{ Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 },
2572 	/* ACTLR */
2573 	{ AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 },
2574 	/* ACTLR2 */
2575 	{ AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 },
2576 	{ Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
2577 	{ Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 },
2578 	/* TTBCR */
2579 	{ AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 },
2580 	/* TTBCR2 */
2581 	{ AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 },
2582 	{ Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 },
2583 	/* DFSR */
2584 	{ Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 },
2585 	{ Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 },
2586 	/* ADFSR */
2587 	{ Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 },
2588 	/* AIFSR */
2589 	{ Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 },
2590 	/* DFAR */
2591 	{ AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 },
2592 	/* IFAR */
2593 	{ AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 },
2594 
2595 	/*
2596 	 * DC{C,I,CI}SW operations:
2597 	 */
2598 	{ Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
2599 	{ Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
2600 	{ Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
2601 
2602 	/* PMU */
2603 	{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr },
2604 	{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten },
2605 	{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten },
2606 	{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs },
2607 	{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc },
2608 	{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr },
2609 	{ CP15_PMU_SYS_REG(LO,     0, 9, 12, 6), .access = access_pmceid },
2610 	{ CP15_PMU_SYS_REG(LO,     0, 9, 12, 7), .access = access_pmceid },
2611 	{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr },
2612 	{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper },
2613 	{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr },
2614 	{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr },
2615 	{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten },
2616 	{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten },
2617 	{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs },
2618 	{ CP15_PMU_SYS_REG(HI,     0, 9, 14, 4), .access = access_pmceid },
2619 	{ CP15_PMU_SYS_REG(HI,     0, 9, 14, 5), .access = access_pmceid },
2620 	/* PMMIR */
2621 	{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi },
2622 
2623 	/* PRRR/MAIR0 */
2624 	{ AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
2625 	/* NMRR/MAIR1 */
2626 	{ AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 },
2627 	/* AMAIR0 */
2628 	{ AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 },
2629 	/* AMAIR1 */
2630 	{ AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 },
2631 
2632 	/* ICC_SRE */
2633 	{ Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
2634 
2635 	{ Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 },
2636 
2637 	/* Arch Tmers */
2638 	{ SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
2639 	{ SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
2640 
2641 	/* PMEVCNTRn */
2642 	PMU_PMEVCNTR(0),
2643 	PMU_PMEVCNTR(1),
2644 	PMU_PMEVCNTR(2),
2645 	PMU_PMEVCNTR(3),
2646 	PMU_PMEVCNTR(4),
2647 	PMU_PMEVCNTR(5),
2648 	PMU_PMEVCNTR(6),
2649 	PMU_PMEVCNTR(7),
2650 	PMU_PMEVCNTR(8),
2651 	PMU_PMEVCNTR(9),
2652 	PMU_PMEVCNTR(10),
2653 	PMU_PMEVCNTR(11),
2654 	PMU_PMEVCNTR(12),
2655 	PMU_PMEVCNTR(13),
2656 	PMU_PMEVCNTR(14),
2657 	PMU_PMEVCNTR(15),
2658 	PMU_PMEVCNTR(16),
2659 	PMU_PMEVCNTR(17),
2660 	PMU_PMEVCNTR(18),
2661 	PMU_PMEVCNTR(19),
2662 	PMU_PMEVCNTR(20),
2663 	PMU_PMEVCNTR(21),
2664 	PMU_PMEVCNTR(22),
2665 	PMU_PMEVCNTR(23),
2666 	PMU_PMEVCNTR(24),
2667 	PMU_PMEVCNTR(25),
2668 	PMU_PMEVCNTR(26),
2669 	PMU_PMEVCNTR(27),
2670 	PMU_PMEVCNTR(28),
2671 	PMU_PMEVCNTR(29),
2672 	PMU_PMEVCNTR(30),
2673 	/* PMEVTYPERn */
2674 	PMU_PMEVTYPER(0),
2675 	PMU_PMEVTYPER(1),
2676 	PMU_PMEVTYPER(2),
2677 	PMU_PMEVTYPER(3),
2678 	PMU_PMEVTYPER(4),
2679 	PMU_PMEVTYPER(5),
2680 	PMU_PMEVTYPER(6),
2681 	PMU_PMEVTYPER(7),
2682 	PMU_PMEVTYPER(8),
2683 	PMU_PMEVTYPER(9),
2684 	PMU_PMEVTYPER(10),
2685 	PMU_PMEVTYPER(11),
2686 	PMU_PMEVTYPER(12),
2687 	PMU_PMEVTYPER(13),
2688 	PMU_PMEVTYPER(14),
2689 	PMU_PMEVTYPER(15),
2690 	PMU_PMEVTYPER(16),
2691 	PMU_PMEVTYPER(17),
2692 	PMU_PMEVTYPER(18),
2693 	PMU_PMEVTYPER(19),
2694 	PMU_PMEVTYPER(20),
2695 	PMU_PMEVTYPER(21),
2696 	PMU_PMEVTYPER(22),
2697 	PMU_PMEVTYPER(23),
2698 	PMU_PMEVTYPER(24),
2699 	PMU_PMEVTYPER(25),
2700 	PMU_PMEVTYPER(26),
2701 	PMU_PMEVTYPER(27),
2702 	PMU_PMEVTYPER(28),
2703 	PMU_PMEVTYPER(29),
2704 	PMU_PMEVTYPER(30),
2705 	/* PMCCFILTR */
2706 	{ CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper },
2707 
2708 	{ Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
2709 	{ Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
2710 
2711 	/* CCSIDR2 */
2712 	{ Op1(1), CRn( 0), CRm( 0),  Op2(2), undef_access },
2713 
2714 	{ Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 },
2715 };
2716 
2717 static const struct sys_reg_desc cp15_64_regs[] = {
2718 	{ Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
2719 	{ CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr },
2720 	{ Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
2721 	{ SYS_DESC(SYS_AARCH32_CNTPCT),	      access_arch_timer },
2722 	{ Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 },
2723 	{ Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
2724 	{ Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
2725 	{ SYS_DESC(SYS_AARCH32_CNTP_CVAL),    access_arch_timer },
2726 	{ SYS_DESC(SYS_AARCH32_CNTPCTSS),     access_arch_timer },
2727 };
2728 
check_sysreg_table(const struct sys_reg_desc * table,unsigned int n,bool is_32)2729 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n,
2730 			       bool is_32)
2731 {
2732 	unsigned int i;
2733 
2734 	for (i = 0; i < n; i++) {
2735 		if (!is_32 && table[i].reg && !table[i].reset) {
2736 			kvm_err("sys_reg table %pS entry %d lacks reset\n", &table[i], i);
2737 			return false;
2738 		}
2739 
2740 		if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2741 			kvm_err("sys_reg table %pS entry %d out of order\n", &table[i - 1], i - 1);
2742 			return false;
2743 		}
2744 	}
2745 
2746 	return true;
2747 }
2748 
kvm_handle_cp14_load_store(struct kvm_vcpu * vcpu)2749 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)
2750 {
2751 	kvm_inject_undefined(vcpu);
2752 	return 1;
2753 }
2754 
perform_access(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)2755 static void perform_access(struct kvm_vcpu *vcpu,
2756 			   struct sys_reg_params *params,
2757 			   const struct sys_reg_desc *r)
2758 {
2759 	trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
2760 
2761 	/* Check for regs disabled by runtime config */
2762 	if (sysreg_hidden(vcpu, r)) {
2763 		kvm_inject_undefined(vcpu);
2764 		return;
2765 	}
2766 
2767 	/*
2768 	 * Not having an accessor means that we have configured a trap
2769 	 * that we don't know how to handle. This certainly qualifies
2770 	 * as a gross bug that should be fixed right away.
2771 	 */
2772 	BUG_ON(!r->access);
2773 
2774 	/* Skip instruction if instructed so */
2775 	if (likely(r->access(vcpu, params, r)))
2776 		kvm_incr_pc(vcpu);
2777 }
2778 
2779 /*
2780  * emulate_cp --  tries to match a sys_reg access in a handling table, and
2781  *                call the corresponding trap handler.
2782  *
2783  * @params: pointer to the descriptor of the access
2784  * @table: array of trap descriptors
2785  * @num: size of the trap descriptor array
2786  *
2787  * Return true if the access has been handled, false if not.
2788  */
emulate_cp(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * table,size_t num)2789 static bool emulate_cp(struct kvm_vcpu *vcpu,
2790 		       struct sys_reg_params *params,
2791 		       const struct sys_reg_desc *table,
2792 		       size_t num)
2793 {
2794 	const struct sys_reg_desc *r;
2795 
2796 	if (!table)
2797 		return false;	/* Not handled */
2798 
2799 	r = find_reg(params, table, num);
2800 
2801 	if (r) {
2802 		perform_access(vcpu, params, r);
2803 		return true;
2804 	}
2805 
2806 	/* Not handled */
2807 	return false;
2808 }
2809 
unhandled_cp_access(struct kvm_vcpu * vcpu,struct sys_reg_params * params)2810 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
2811 				struct sys_reg_params *params)
2812 {
2813 	u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
2814 	int cp = -1;
2815 
2816 	switch (esr_ec) {
2817 	case ESR_ELx_EC_CP15_32:
2818 	case ESR_ELx_EC_CP15_64:
2819 		cp = 15;
2820 		break;
2821 	case ESR_ELx_EC_CP14_MR:
2822 	case ESR_ELx_EC_CP14_64:
2823 		cp = 14;
2824 		break;
2825 	default:
2826 		WARN_ON(1);
2827 	}
2828 
2829 	print_sys_reg_msg(params,
2830 			  "Unsupported guest CP%d access at: %08lx [%08lx]\n",
2831 			  cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2832 	kvm_inject_undefined(vcpu);
2833 }
2834 
2835 /**
2836  * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
2837  * @vcpu: The VCPU pointer
2838  * @run:  The kvm_run struct
2839  */
kvm_handle_cp_64(struct kvm_vcpu * vcpu,const struct sys_reg_desc * global,size_t nr_global)2840 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
2841 			    const struct sys_reg_desc *global,
2842 			    size_t nr_global)
2843 {
2844 	struct sys_reg_params params;
2845 	u64 esr = kvm_vcpu_get_esr(vcpu);
2846 	int Rt = kvm_vcpu_sys_get_rt(vcpu);
2847 	int Rt2 = (esr >> 10) & 0x1f;
2848 
2849 	params.CRm = (esr >> 1) & 0xf;
2850 	params.is_write = ((esr & 1) == 0);
2851 
2852 	params.Op0 = 0;
2853 	params.Op1 = (esr >> 16) & 0xf;
2854 	params.Op2 = 0;
2855 	params.CRn = 0;
2856 
2857 	/*
2858 	 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
2859 	 * backends between AArch32 and AArch64, we get away with it.
2860 	 */
2861 	if (params.is_write) {
2862 		params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
2863 		params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
2864 	}
2865 
2866 	/*
2867 	 * If the table contains a handler, handle the
2868 	 * potential register operation in the case of a read and return
2869 	 * with success.
2870 	 */
2871 	if (emulate_cp(vcpu, &params, global, nr_global)) {
2872 		/* Split up the value between registers for the read side */
2873 		if (!params.is_write) {
2874 			vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
2875 			vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
2876 		}
2877 
2878 		return 1;
2879 	}
2880 
2881 	unhandled_cp_access(vcpu, &params);
2882 	return 1;
2883 }
2884 
2885 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params);
2886 
2887 /*
2888  * The CP10 ID registers are architecturally mapped to AArch64 feature
2889  * registers. Abuse that fact so we can rely on the AArch64 handler for accesses
2890  * from AArch32.
2891  */
kvm_esr_cp10_id_to_sys64(u64 esr,struct sys_reg_params * params)2892 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params)
2893 {
2894 	u8 reg_id = (esr >> 10) & 0xf;
2895 	bool valid;
2896 
2897 	params->is_write = ((esr & 1) == 0);
2898 	params->Op0 = 3;
2899 	params->Op1 = 0;
2900 	params->CRn = 0;
2901 	params->CRm = 3;
2902 
2903 	/* CP10 ID registers are read-only */
2904 	valid = !params->is_write;
2905 
2906 	switch (reg_id) {
2907 	/* MVFR0 */
2908 	case 0b0111:
2909 		params->Op2 = 0;
2910 		break;
2911 	/* MVFR1 */
2912 	case 0b0110:
2913 		params->Op2 = 1;
2914 		break;
2915 	/* MVFR2 */
2916 	case 0b0101:
2917 		params->Op2 = 2;
2918 		break;
2919 	default:
2920 		valid = false;
2921 	}
2922 
2923 	if (valid)
2924 		return true;
2925 
2926 	kvm_pr_unimpl("Unhandled cp10 register %s: %u\n",
2927 		      params->is_write ? "write" : "read", reg_id);
2928 	return false;
2929 }
2930 
2931 /**
2932  * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and
2933  *			  VFP Register' from AArch32.
2934  * @vcpu: The vCPU pointer
2935  *
2936  * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers.
2937  * Work out the correct AArch64 system register encoding and reroute to the
2938  * AArch64 system register emulation.
2939  */
kvm_handle_cp10_id(struct kvm_vcpu * vcpu)2940 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu)
2941 {
2942 	int Rt = kvm_vcpu_sys_get_rt(vcpu);
2943 	u64 esr = kvm_vcpu_get_esr(vcpu);
2944 	struct sys_reg_params params;
2945 
2946 	/* UNDEF on any unhandled register access */
2947 	if (!kvm_esr_cp10_id_to_sys64(esr, &params)) {
2948 		kvm_inject_undefined(vcpu);
2949 		return 1;
2950 	}
2951 
2952 	if (emulate_sys_reg(vcpu, &params))
2953 		vcpu_set_reg(vcpu, Rt, params.regval);
2954 
2955 	return 1;
2956 }
2957 
2958 /**
2959  * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where
2960  *			       CRn=0, which corresponds to the AArch32 feature
2961  *			       registers.
2962  * @vcpu: the vCPU pointer
2963  * @params: the system register access parameters.
2964  *
2965  * Our cp15 system register tables do not enumerate the AArch32 feature
2966  * registers. Conveniently, our AArch64 table does, and the AArch32 system
2967  * register encoding can be trivially remapped into the AArch64 for the feature
2968  * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same.
2969  *
2970  * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit
2971  * System registers with (coproc=0b1111, CRn==c0)", read accesses from this
2972  * range are either UNKNOWN or RES0. Rerouting remains architectural as we
2973  * treat undefined registers in this range as RAZ.
2974  */
kvm_emulate_cp15_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * params)2975 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu,
2976 				   struct sys_reg_params *params)
2977 {
2978 	int Rt = kvm_vcpu_sys_get_rt(vcpu);
2979 
2980 	/* Treat impossible writes to RO registers as UNDEFINED */
2981 	if (params->is_write) {
2982 		unhandled_cp_access(vcpu, params);
2983 		return 1;
2984 	}
2985 
2986 	params->Op0 = 3;
2987 
2988 	/*
2989 	 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32.
2990 	 * Avoid conflicting with future expansion of AArch64 feature registers
2991 	 * and simply treat them as RAZ here.
2992 	 */
2993 	if (params->CRm > 3)
2994 		params->regval = 0;
2995 	else if (!emulate_sys_reg(vcpu, params))
2996 		return 1;
2997 
2998 	vcpu_set_reg(vcpu, Rt, params->regval);
2999 	return 1;
3000 }
3001 
3002 /**
3003  * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
3004  * @vcpu: The VCPU pointer
3005  * @run:  The kvm_run struct
3006  */
kvm_handle_cp_32(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * global,size_t nr_global)3007 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
3008 			    struct sys_reg_params *params,
3009 			    const struct sys_reg_desc *global,
3010 			    size_t nr_global)
3011 {
3012 	int Rt  = kvm_vcpu_sys_get_rt(vcpu);
3013 
3014 	params->regval = vcpu_get_reg(vcpu, Rt);
3015 
3016 	if (emulate_cp(vcpu, params, global, nr_global)) {
3017 		if (!params->is_write)
3018 			vcpu_set_reg(vcpu, Rt, params->regval);
3019 		return 1;
3020 	}
3021 
3022 	unhandled_cp_access(vcpu, params);
3023 	return 1;
3024 }
3025 
kvm_handle_cp15_64(struct kvm_vcpu * vcpu)3026 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu)
3027 {
3028 	return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs));
3029 }
3030 
kvm_handle_cp15_32(struct kvm_vcpu * vcpu)3031 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu)
3032 {
3033 	struct sys_reg_params params;
3034 
3035 	params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu));
3036 
3037 	/*
3038 	 * Certain AArch32 ID registers are handled by rerouting to the AArch64
3039 	 * system register table. Registers in the ID range where CRm=0 are
3040 	 * excluded from this scheme as they do not trivially map into AArch64
3041 	 * system register encodings.
3042 	 */
3043 	if (params.Op1 == 0 && params.CRn == 0 && params.CRm)
3044 		return kvm_emulate_cp15_id_reg(vcpu, &params);
3045 
3046 	return kvm_handle_cp_32(vcpu, &params, cp15_regs, ARRAY_SIZE(cp15_regs));
3047 }
3048 
kvm_handle_cp14_64(struct kvm_vcpu * vcpu)3049 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu)
3050 {
3051 	return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs));
3052 }
3053 
kvm_handle_cp14_32(struct kvm_vcpu * vcpu)3054 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu)
3055 {
3056 	struct sys_reg_params params;
3057 
3058 	params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu));
3059 
3060 	return kvm_handle_cp_32(vcpu, &params, cp14_regs, ARRAY_SIZE(cp14_regs));
3061 }
3062 
is_imp_def_sys_reg(struct sys_reg_params * params)3063 static bool is_imp_def_sys_reg(struct sys_reg_params *params)
3064 {
3065 	// See ARM DDI 0487E.a, section D12.3.2
3066 	return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011;
3067 }
3068 
3069 /**
3070  * emulate_sys_reg - Emulate a guest access to an AArch64 system register
3071  * @vcpu: The VCPU pointer
3072  * @params: Decoded system register parameters
3073  *
3074  * Return: true if the system register access was successful, false otherwise.
3075  */
emulate_sys_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * params)3076 static bool emulate_sys_reg(struct kvm_vcpu *vcpu,
3077 			   struct sys_reg_params *params)
3078 {
3079 	const struct sys_reg_desc *r;
3080 
3081 	r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
3082 
3083 	if (likely(r)) {
3084 		perform_access(vcpu, params, r);
3085 		return true;
3086 	}
3087 
3088 	if (is_imp_def_sys_reg(params)) {
3089 		kvm_inject_undefined(vcpu);
3090 	} else {
3091 		print_sys_reg_msg(params,
3092 				  "Unsupported guest sys_reg access at: %lx [%08lx]\n",
3093 				  *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
3094 		kvm_inject_undefined(vcpu);
3095 	}
3096 	return false;
3097 }
3098 
kvm_reset_id_regs(struct kvm_vcpu * vcpu)3099 static void kvm_reset_id_regs(struct kvm_vcpu *vcpu)
3100 {
3101 	const struct sys_reg_desc *idreg = first_idreg;
3102 	u32 id = reg_to_encoding(idreg);
3103 	struct kvm *kvm = vcpu->kvm;
3104 
3105 	if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags))
3106 		return;
3107 
3108 	lockdep_assert_held(&kvm->arch.config_lock);
3109 
3110 	/* Initialize all idregs */
3111 	while (is_id_reg(id)) {
3112 		IDREG(kvm, id) = idreg->reset(vcpu, idreg);
3113 
3114 		idreg++;
3115 		id = reg_to_encoding(idreg);
3116 	}
3117 
3118 	set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags);
3119 }
3120 
3121 /**
3122  * kvm_reset_sys_regs - sets system registers to reset value
3123  * @vcpu: The VCPU pointer
3124  *
3125  * This function finds the right table above and sets the registers on the
3126  * virtual CPU struct to their architecturally defined reset values.
3127  */
kvm_reset_sys_regs(struct kvm_vcpu * vcpu)3128 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
3129 {
3130 	unsigned long i;
3131 
3132 	kvm_reset_id_regs(vcpu);
3133 
3134 	for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) {
3135 		const struct sys_reg_desc *r = &sys_reg_descs[i];
3136 
3137 		if (is_id_reg(reg_to_encoding(r)))
3138 			continue;
3139 
3140 		if (r->reset)
3141 			r->reset(vcpu, r);
3142 	}
3143 }
3144 
3145 /**
3146  * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
3147  * @vcpu: The VCPU pointer
3148  */
kvm_handle_sys_reg(struct kvm_vcpu * vcpu)3149 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu)
3150 {
3151 	struct sys_reg_params params;
3152 	unsigned long esr = kvm_vcpu_get_esr(vcpu);
3153 	int Rt = kvm_vcpu_sys_get_rt(vcpu);
3154 
3155 	trace_kvm_handle_sys_reg(esr);
3156 
3157 	if (__check_nv_sr_forward(vcpu))
3158 		return 1;
3159 
3160 	params = esr_sys64_to_params(esr);
3161 	params.regval = vcpu_get_reg(vcpu, Rt);
3162 
3163 	if (!emulate_sys_reg(vcpu, &params))
3164 		return 1;
3165 
3166 	if (!params.is_write)
3167 		vcpu_set_reg(vcpu, Rt, params.regval);
3168 	return 1;
3169 }
3170 
3171 /******************************************************************************
3172  * Userspace API
3173  *****************************************************************************/
3174 
index_to_params(u64 id,struct sys_reg_params * params)3175 static bool index_to_params(u64 id, struct sys_reg_params *params)
3176 {
3177 	switch (id & KVM_REG_SIZE_MASK) {
3178 	case KVM_REG_SIZE_U64:
3179 		/* Any unused index bits means it's not valid. */
3180 		if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
3181 			      | KVM_REG_ARM_COPROC_MASK
3182 			      | KVM_REG_ARM64_SYSREG_OP0_MASK
3183 			      | KVM_REG_ARM64_SYSREG_OP1_MASK
3184 			      | KVM_REG_ARM64_SYSREG_CRN_MASK
3185 			      | KVM_REG_ARM64_SYSREG_CRM_MASK
3186 			      | KVM_REG_ARM64_SYSREG_OP2_MASK))
3187 			return false;
3188 		params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
3189 			       >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
3190 		params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
3191 			       >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
3192 		params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
3193 			       >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
3194 		params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
3195 			       >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
3196 		params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
3197 			       >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
3198 		return true;
3199 	default:
3200 		return false;
3201 	}
3202 }
3203 
get_reg_by_id(u64 id,const struct sys_reg_desc table[],unsigned int num)3204 const struct sys_reg_desc *get_reg_by_id(u64 id,
3205 					 const struct sys_reg_desc table[],
3206 					 unsigned int num)
3207 {
3208 	struct sys_reg_params params;
3209 
3210 	if (!index_to_params(id, &params))
3211 		return NULL;
3212 
3213 	return find_reg(&params, table, num);
3214 }
3215 
3216 /* Decode an index value, and find the sys_reg_desc entry. */
3217 static const struct sys_reg_desc *
id_to_sys_reg_desc(struct kvm_vcpu * vcpu,u64 id,const struct sys_reg_desc table[],unsigned int num)3218 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id,
3219 		   const struct sys_reg_desc table[], unsigned int num)
3220 
3221 {
3222 	const struct sys_reg_desc *r;
3223 
3224 	/* We only do sys_reg for now. */
3225 	if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
3226 		return NULL;
3227 
3228 	r = get_reg_by_id(id, table, num);
3229 
3230 	/* Not saved in the sys_reg array and not otherwise accessible? */
3231 	if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r)))
3232 		r = NULL;
3233 
3234 	return r;
3235 }
3236 
3237 /*
3238  * These are the invariant sys_reg registers: we let the guest see the
3239  * host versions of these, so they're part of the guest state.
3240  *
3241  * A future CPU may provide a mechanism to present different values to
3242  * the guest, or a future kvm may trap them.
3243  */
3244 
3245 #define FUNCTION_INVARIANT(reg)						\
3246 	static u64 get_##reg(struct kvm_vcpu *v,			\
3247 			      const struct sys_reg_desc *r)		\
3248 	{								\
3249 		((struct sys_reg_desc *)r)->val = read_sysreg(reg);	\
3250 		return ((struct sys_reg_desc *)r)->val;			\
3251 	}
3252 
3253 FUNCTION_INVARIANT(midr_el1)
FUNCTION_INVARIANT(revidr_el1)3254 FUNCTION_INVARIANT(revidr_el1)
3255 FUNCTION_INVARIANT(aidr_el1)
3256 
3257 static u64 get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
3258 {
3259 	((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
3260 	return ((struct sys_reg_desc *)r)->val;
3261 }
3262 
3263 /* ->val is filled in by kvm_sys_reg_table_init() */
3264 static struct sys_reg_desc invariant_sys_regs[] __ro_after_init = {
3265 	{ SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },
3266 	{ SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },
3267 	{ SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },
3268 	{ SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },
3269 };
3270 
get_invariant_sys_reg(u64 id,u64 __user * uaddr)3271 static int get_invariant_sys_reg(u64 id, u64 __user *uaddr)
3272 {
3273 	const struct sys_reg_desc *r;
3274 
3275 	r = get_reg_by_id(id, invariant_sys_regs,
3276 			  ARRAY_SIZE(invariant_sys_regs));
3277 	if (!r)
3278 		return -ENOENT;
3279 
3280 	return put_user(r->val, uaddr);
3281 }
3282 
set_invariant_sys_reg(u64 id,u64 __user * uaddr)3283 static int set_invariant_sys_reg(u64 id, u64 __user *uaddr)
3284 {
3285 	const struct sys_reg_desc *r;
3286 	u64 val;
3287 
3288 	r = get_reg_by_id(id, invariant_sys_regs,
3289 			  ARRAY_SIZE(invariant_sys_regs));
3290 	if (!r)
3291 		return -ENOENT;
3292 
3293 	if (get_user(val, uaddr))
3294 		return -EFAULT;
3295 
3296 	/* This is what we mean by invariant: you can't change it. */
3297 	if (r->val != val)
3298 		return -EINVAL;
3299 
3300 	return 0;
3301 }
3302 
demux_c15_get(struct kvm_vcpu * vcpu,u64 id,void __user * uaddr)3303 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
3304 {
3305 	u32 val;
3306 	u32 __user *uval = uaddr;
3307 
3308 	/* Fail if we have unknown bits set. */
3309 	if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
3310 		   | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
3311 		return -ENOENT;
3312 
3313 	switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
3314 	case KVM_REG_ARM_DEMUX_ID_CCSIDR:
3315 		if (KVM_REG_SIZE(id) != 4)
3316 			return -ENOENT;
3317 		val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
3318 			>> KVM_REG_ARM_DEMUX_VAL_SHIFT;
3319 		if (val >= CSSELR_MAX)
3320 			return -ENOENT;
3321 
3322 		return put_user(get_ccsidr(vcpu, val), uval);
3323 	default:
3324 		return -ENOENT;
3325 	}
3326 }
3327 
demux_c15_set(struct kvm_vcpu * vcpu,u64 id,void __user * uaddr)3328 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
3329 {
3330 	u32 val, newval;
3331 	u32 __user *uval = uaddr;
3332 
3333 	/* Fail if we have unknown bits set. */
3334 	if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
3335 		   | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
3336 		return -ENOENT;
3337 
3338 	switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
3339 	case KVM_REG_ARM_DEMUX_ID_CCSIDR:
3340 		if (KVM_REG_SIZE(id) != 4)
3341 			return -ENOENT;
3342 		val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
3343 			>> KVM_REG_ARM_DEMUX_VAL_SHIFT;
3344 		if (val >= CSSELR_MAX)
3345 			return -ENOENT;
3346 
3347 		if (get_user(newval, uval))
3348 			return -EFAULT;
3349 
3350 		return set_ccsidr(vcpu, val, newval);
3351 	default:
3352 		return -ENOENT;
3353 	}
3354 }
3355 
kvm_sys_reg_get_user(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg,const struct sys_reg_desc table[],unsigned int num)3356 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
3357 			 const struct sys_reg_desc table[], unsigned int num)
3358 {
3359 	u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
3360 	const struct sys_reg_desc *r;
3361 	u64 val;
3362 	int ret;
3363 
3364 	r = id_to_sys_reg_desc(vcpu, reg->id, table, num);
3365 	if (!r || sysreg_hidden_user(vcpu, r))
3366 		return -ENOENT;
3367 
3368 	if (r->get_user) {
3369 		ret = (r->get_user)(vcpu, r, &val);
3370 	} else {
3371 		val = __vcpu_sys_reg(vcpu, r->reg);
3372 		ret = 0;
3373 	}
3374 
3375 	if (!ret)
3376 		ret = put_user(val, uaddr);
3377 
3378 	return ret;
3379 }
3380 
kvm_arm_sys_reg_get_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)3381 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
3382 {
3383 	void __user *uaddr = (void __user *)(unsigned long)reg->addr;
3384 	int err;
3385 
3386 	if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
3387 		return demux_c15_get(vcpu, reg->id, uaddr);
3388 
3389 	err = get_invariant_sys_reg(reg->id, uaddr);
3390 	if (err != -ENOENT)
3391 		return err;
3392 
3393 	return kvm_sys_reg_get_user(vcpu, reg,
3394 				    sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
3395 }
3396 
kvm_sys_reg_set_user(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg,const struct sys_reg_desc table[],unsigned int num)3397 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
3398 			 const struct sys_reg_desc table[], unsigned int num)
3399 {
3400 	u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
3401 	const struct sys_reg_desc *r;
3402 	u64 val;
3403 	int ret;
3404 
3405 	if (get_user(val, uaddr))
3406 		return -EFAULT;
3407 
3408 	r = id_to_sys_reg_desc(vcpu, reg->id, table, num);
3409 	if (!r || sysreg_hidden_user(vcpu, r))
3410 		return -ENOENT;
3411 
3412 	if (sysreg_user_write_ignore(vcpu, r))
3413 		return 0;
3414 
3415 	if (r->set_user) {
3416 		ret = (r->set_user)(vcpu, r, val);
3417 	} else {
3418 		__vcpu_sys_reg(vcpu, r->reg) = val;
3419 		ret = 0;
3420 	}
3421 
3422 	return ret;
3423 }
3424 
kvm_arm_sys_reg_set_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)3425 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
3426 {
3427 	void __user *uaddr = (void __user *)(unsigned long)reg->addr;
3428 	int err;
3429 
3430 	if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
3431 		return demux_c15_set(vcpu, reg->id, uaddr);
3432 
3433 	err = set_invariant_sys_reg(reg->id, uaddr);
3434 	if (err != -ENOENT)
3435 		return err;
3436 
3437 	return kvm_sys_reg_set_user(vcpu, reg,
3438 				    sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
3439 }
3440 
num_demux_regs(void)3441 static unsigned int num_demux_regs(void)
3442 {
3443 	return CSSELR_MAX;
3444 }
3445 
write_demux_regids(u64 __user * uindices)3446 static int write_demux_regids(u64 __user *uindices)
3447 {
3448 	u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
3449 	unsigned int i;
3450 
3451 	val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
3452 	for (i = 0; i < CSSELR_MAX; i++) {
3453 		if (put_user(val | i, uindices))
3454 			return -EFAULT;
3455 		uindices++;
3456 	}
3457 	return 0;
3458 }
3459 
sys_reg_to_index(const struct sys_reg_desc * reg)3460 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
3461 {
3462 	return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
3463 		KVM_REG_ARM64_SYSREG |
3464 		(reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
3465 		(reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
3466 		(reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
3467 		(reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
3468 		(reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
3469 }
3470 
copy_reg_to_user(const struct sys_reg_desc * reg,u64 __user ** uind)3471 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
3472 {
3473 	if (!*uind)
3474 		return true;
3475 
3476 	if (put_user(sys_reg_to_index(reg), *uind))
3477 		return false;
3478 
3479 	(*uind)++;
3480 	return true;
3481 }
3482 
walk_one_sys_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 __user ** uind,unsigned int * total)3483 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
3484 			    const struct sys_reg_desc *rd,
3485 			    u64 __user **uind,
3486 			    unsigned int *total)
3487 {
3488 	/*
3489 	 * Ignore registers we trap but don't save,
3490 	 * and for which no custom user accessor is provided.
3491 	 */
3492 	if (!(rd->reg || rd->get_user))
3493 		return 0;
3494 
3495 	if (sysreg_hidden_user(vcpu, rd))
3496 		return 0;
3497 
3498 	if (!copy_reg_to_user(rd, uind))
3499 		return -EFAULT;
3500 
3501 	(*total)++;
3502 	return 0;
3503 }
3504 
3505 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
walk_sys_regs(struct kvm_vcpu * vcpu,u64 __user * uind)3506 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
3507 {
3508 	const struct sys_reg_desc *i2, *end2;
3509 	unsigned int total = 0;
3510 	int err;
3511 
3512 	i2 = sys_reg_descs;
3513 	end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
3514 
3515 	while (i2 != end2) {
3516 		err = walk_one_sys_reg(vcpu, i2++, &uind, &total);
3517 		if (err)
3518 			return err;
3519 	}
3520 	return total;
3521 }
3522 
kvm_arm_num_sys_reg_descs(struct kvm_vcpu * vcpu)3523 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
3524 {
3525 	return ARRAY_SIZE(invariant_sys_regs)
3526 		+ num_demux_regs()
3527 		+ walk_sys_regs(vcpu, (u64 __user *)NULL);
3528 }
3529 
kvm_arm_copy_sys_reg_indices(struct kvm_vcpu * vcpu,u64 __user * uindices)3530 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
3531 {
3532 	unsigned int i;
3533 	int err;
3534 
3535 	/* Then give them all the invariant registers' indices. */
3536 	for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
3537 		if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
3538 			return -EFAULT;
3539 		uindices++;
3540 	}
3541 
3542 	err = walk_sys_regs(vcpu, uindices);
3543 	if (err < 0)
3544 		return err;
3545 	uindices += err;
3546 
3547 	return write_demux_regids(uindices);
3548 }
3549 
kvm_sys_reg_table_init(void)3550 int __init kvm_sys_reg_table_init(void)
3551 {
3552 	struct sys_reg_params params;
3553 	bool valid = true;
3554 	unsigned int i;
3555 
3556 	/* Make sure tables are unique and in order. */
3557 	valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false);
3558 	valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true);
3559 	valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true);
3560 	valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true);
3561 	valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true);
3562 	valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false);
3563 
3564 	if (!valid)
3565 		return -EINVAL;
3566 
3567 	/* We abuse the reset function to overwrite the table itself. */
3568 	for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
3569 		invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
3570 
3571 	/* Find the first idreg (SYS_ID_PFR0_EL1) in sys_reg_descs. */
3572 	params = encoding_to_params(SYS_ID_PFR0_EL1);
3573 	first_idreg = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
3574 	if (!first_idreg)
3575 		return -EINVAL;
3576 
3577 	if (kvm_get_mode() == KVM_MODE_NV)
3578 		return populate_nv_trap_config();
3579 
3580 	return 0;
3581 }
3582