1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 /* FILE POLICY AND INTENDED USAGE:
27 *
28 * This file implements generic display communication protocols such as i2c, aux
29 * and scdc. The file should not contain any specific applications of these
30 * protocols such as display capability query, detection, or handshaking such as
31 * link training.
32 */
33 #include "link_ddc.h"
34 #include "vector.h"
35 #include "dce/dce_aux.h"
36 #include "dal_asic_id.h"
37 #include "link_dpcd.h"
38 #include "dm_helpers.h"
39 #include "atomfirmware.h"
40
41 #define DC_LOGGER_INIT(logger)
42
43 static const uint8_t DP_VGA_DONGLE_BRANCH_DEV_NAME[] = "DpVga";
44 /* DP to Dual link DVI converter */
45 static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
46 static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2";
47
48 struct i2c_payloads {
49 struct vector payloads;
50 };
51
52 struct aux_payloads {
53 struct vector payloads;
54 };
55
i2c_payloads_create(struct dc_context * ctx,struct i2c_payloads * payloads,uint32_t count)56 static bool i2c_payloads_create(
57 struct dc_context *ctx,
58 struct i2c_payloads *payloads,
59 uint32_t count)
60 {
61 if (dal_vector_construct(
62 &payloads->payloads, ctx, count, sizeof(struct i2c_payload)))
63 return true;
64
65 return false;
66 }
67
i2c_payloads_get(struct i2c_payloads * p)68 static struct i2c_payload *i2c_payloads_get(struct i2c_payloads *p)
69 {
70 return (struct i2c_payload *)p->payloads.container;
71 }
72
i2c_payloads_get_count(struct i2c_payloads * p)73 static uint32_t i2c_payloads_get_count(struct i2c_payloads *p)
74 {
75 return p->payloads.count;
76 }
77
i2c_payloads_destroy(struct i2c_payloads * p)78 static void i2c_payloads_destroy(struct i2c_payloads *p)
79 {
80 if (!p)
81 return;
82
83 dal_vector_destruct(&p->payloads);
84 }
85
86 #define DDC_MIN(a, b) (((a) < (b)) ? (a) : (b))
87
i2c_payloads_add(struct i2c_payloads * payloads,uint32_t address,uint32_t len,uint8_t * data,bool write)88 static void i2c_payloads_add(
89 struct i2c_payloads *payloads,
90 uint32_t address,
91 uint32_t len,
92 uint8_t *data,
93 bool write)
94 {
95 uint32_t payload_size = EDID_SEGMENT_SIZE;
96 uint32_t pos;
97
98 for (pos = 0; pos < len; pos += payload_size) {
99 struct i2c_payload payload = {
100 .write = write,
101 .address = address,
102 .length = DDC_MIN(payload_size, len - pos),
103 .data = data + pos };
104 dal_vector_append(&payloads->payloads, &payload);
105 }
106
107 }
108
ddc_service_construct(struct ddc_service * ddc_service,struct ddc_service_init_data * init_data)109 static void ddc_service_construct(
110 struct ddc_service *ddc_service,
111 struct ddc_service_init_data *init_data)
112 {
113 enum connector_id connector_id =
114 dal_graphics_object_id_get_connector_id(init_data->id);
115
116 struct gpio_service *gpio_service = init_data->ctx->gpio_service;
117 struct graphics_object_i2c_info i2c_info;
118 struct gpio_ddc_hw_info hw_info;
119 struct dc_bios *dcb = init_data->ctx->dc_bios;
120
121 ddc_service->link = init_data->link;
122 ddc_service->ctx = init_data->ctx;
123
124 if (init_data->is_dpia_link ||
125 dcb->funcs->get_i2c_info(dcb, init_data->id, &i2c_info) != BP_RESULT_OK) {
126 ddc_service->ddc_pin = NULL;
127 } else {
128 DC_LOGGER_INIT(ddc_service->ctx->logger);
129 DC_LOG_DC("BIOS object table - i2c_line: %d", i2c_info.i2c_line);
130 DC_LOG_DC("BIOS object table - i2c_engine_id: %d", i2c_info.i2c_engine_id);
131
132 hw_info.ddc_channel = i2c_info.i2c_line;
133 if (ddc_service->link != NULL)
134 hw_info.hw_supported = i2c_info.i2c_hw_assist;
135 else
136 hw_info.hw_supported = false;
137
138 ddc_service->ddc_pin = dal_gpio_create_ddc(
139 gpio_service,
140 i2c_info.gpio_info.clk_a_register_index,
141 1 << i2c_info.gpio_info.clk_a_shift,
142 &hw_info);
143 }
144
145 ddc_service->flags.EDID_QUERY_DONE_ONCE = false;
146 ddc_service->flags.FORCE_READ_REPEATED_START = false;
147 ddc_service->flags.EDID_STRESS_READ = false;
148
149 ddc_service->flags.IS_INTERNAL_DISPLAY =
150 connector_id == CONNECTOR_ID_EDP ||
151 connector_id == CONNECTOR_ID_LVDS;
152
153 ddc_service->wa.raw = 0;
154 }
155
link_create_ddc_service(struct ddc_service_init_data * init_data)156 struct ddc_service *link_create_ddc_service(
157 struct ddc_service_init_data *init_data)
158 {
159 struct ddc_service *ddc_service;
160
161 ddc_service = kzalloc(sizeof(struct ddc_service), GFP_KERNEL);
162
163 if (!ddc_service)
164 return NULL;
165
166 ddc_service_construct(ddc_service, init_data);
167 return ddc_service;
168 }
169
ddc_service_destruct(struct ddc_service * ddc)170 static void ddc_service_destruct(struct ddc_service *ddc)
171 {
172 if (ddc->ddc_pin)
173 dal_gpio_destroy_ddc(&ddc->ddc_pin);
174 }
175
link_destroy_ddc_service(struct ddc_service ** ddc)176 void link_destroy_ddc_service(struct ddc_service **ddc)
177 {
178 if (!ddc || !*ddc) {
179 BREAK_TO_DEBUGGER();
180 return;
181 }
182 ddc_service_destruct(*ddc);
183 kfree(*ddc);
184 *ddc = NULL;
185 }
186
set_ddc_transaction_type(struct ddc_service * ddc,enum ddc_transaction_type type)187 void set_ddc_transaction_type(
188 struct ddc_service *ddc,
189 enum ddc_transaction_type type)
190 {
191 ddc->transaction_type = type;
192 }
193
link_is_in_aux_transaction_mode(struct ddc_service * ddc)194 bool link_is_in_aux_transaction_mode(struct ddc_service *ddc)
195 {
196 switch (ddc->transaction_type) {
197 case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
198 case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
199 case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER:
200 return true;
201 default:
202 break;
203 }
204 return false;
205 }
206
set_dongle_type(struct ddc_service * ddc,enum display_dongle_type dongle_type)207 void set_dongle_type(struct ddc_service *ddc,
208 enum display_dongle_type dongle_type)
209 {
210 ddc->dongle_type = dongle_type;
211 }
212
defer_delay_converter_wa(struct ddc_service * ddc,uint32_t defer_delay)213 static uint32_t defer_delay_converter_wa(
214 struct ddc_service *ddc,
215 uint32_t defer_delay)
216 {
217 struct dc_link *link = ddc->link;
218
219 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER &&
220 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&
221 (link->dpcd_caps.branch_fw_revision[0] < 0x01 ||
222 (link->dpcd_caps.branch_fw_revision[0] == 0x01 &&
223 link->dpcd_caps.branch_fw_revision[1] < 0x40)) &&
224 !memcmp(link->dpcd_caps.branch_dev_name,
225 DP_VGA_DONGLE_BRANCH_DEV_NAME,
226 sizeof(link->dpcd_caps.branch_dev_name)))
227
228 return defer_delay > DPVGA_DONGLE_AUX_DEFER_WA_DELAY ?
229 defer_delay : DPVGA_DONGLE_AUX_DEFER_WA_DELAY;
230
231 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&
232 !memcmp(link->dpcd_caps.branch_dev_name,
233 DP_DVI_CONVERTER_ID_4,
234 sizeof(link->dpcd_caps.branch_dev_name)))
235 return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY ?
236 defer_delay : I2C_OVER_AUX_DEFER_WA_DELAY;
237 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_006037 &&
238 !memcmp(link->dpcd_caps.branch_dev_name,
239 DP_DVI_CONVERTER_ID_5,
240 sizeof(link->dpcd_caps.branch_dev_name)))
241 return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY_1MS ?
242 I2C_OVER_AUX_DEFER_WA_DELAY_1MS : defer_delay;
243
244 return defer_delay;
245 }
246
247 #define DP_TRANSLATOR_DELAY 5
248
link_get_aux_defer_delay(struct ddc_service * ddc)249 uint32_t link_get_aux_defer_delay(struct ddc_service *ddc)
250 {
251 uint32_t defer_delay = 0;
252
253 switch (ddc->transaction_type) {
254 case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
255 if ((DISPLAY_DONGLE_DP_VGA_CONVERTER == ddc->dongle_type) ||
256 (DISPLAY_DONGLE_DP_DVI_CONVERTER == ddc->dongle_type) ||
257 (DISPLAY_DONGLE_DP_HDMI_CONVERTER ==
258 ddc->dongle_type)) {
259
260 defer_delay = DP_TRANSLATOR_DELAY;
261
262 defer_delay =
263 defer_delay_converter_wa(ddc, defer_delay);
264
265 } else /*sink has a delay different from an Active Converter*/
266 defer_delay = 0;
267 break;
268 case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
269 defer_delay = DP_TRANSLATOR_DELAY;
270 break;
271 default:
272 break;
273 }
274 return defer_delay;
275 }
276
submit_aux_command(struct ddc_service * ddc,struct aux_payload * payload)277 static bool submit_aux_command(struct ddc_service *ddc,
278 struct aux_payload *payload)
279 {
280 uint32_t retrieved = 0;
281 bool ret = false;
282
283 if (!ddc)
284 return false;
285
286 if (!payload)
287 return false;
288
289 do {
290 struct aux_payload current_payload;
291 bool is_end_of_payload = (retrieved + DEFAULT_AUX_MAX_DATA_SIZE) >=
292 payload->length;
293 uint32_t payload_length = is_end_of_payload ?
294 payload->length - retrieved : DEFAULT_AUX_MAX_DATA_SIZE;
295
296 current_payload.address = payload->address;
297 current_payload.data = &payload->data[retrieved];
298 current_payload.defer_delay = payload->defer_delay;
299 current_payload.i2c_over_aux = payload->i2c_over_aux;
300 current_payload.length = payload_length;
301 /* set mot (middle of transaction) to false if it is the last payload */
302 current_payload.mot = is_end_of_payload ? payload->mot:true;
303 current_payload.write_status_update = false;
304 current_payload.reply = payload->reply;
305 current_payload.write = payload->write;
306
307 ret = link_aux_transfer_with_retries_no_mutex(ddc, ¤t_payload);
308
309 retrieved += payload_length;
310 } while (retrieved < payload->length && ret == true);
311
312 return ret;
313 }
314
link_query_ddc_data(struct ddc_service * ddc,uint32_t address,uint8_t * write_buf,uint32_t write_size,uint8_t * read_buf,uint32_t read_size)315 bool link_query_ddc_data(
316 struct ddc_service *ddc,
317 uint32_t address,
318 uint8_t *write_buf,
319 uint32_t write_size,
320 uint8_t *read_buf,
321 uint32_t read_size)
322 {
323 bool success = true;
324 uint32_t payload_size =
325 link_is_in_aux_transaction_mode(ddc) ?
326 DEFAULT_AUX_MAX_DATA_SIZE : EDID_SEGMENT_SIZE;
327
328 uint32_t write_payloads =
329 (write_size + payload_size - 1) / payload_size;
330
331 uint32_t read_payloads =
332 (read_size + payload_size - 1) / payload_size;
333
334 uint32_t payloads_num = write_payloads + read_payloads;
335
336 if (!payloads_num)
337 return false;
338
339 if (link_is_in_aux_transaction_mode(ddc)) {
340 struct aux_payload payload;
341
342 payload.i2c_over_aux = true;
343 payload.address = address;
344 payload.reply = NULL;
345 payload.defer_delay = link_get_aux_defer_delay(ddc);
346 payload.write_status_update = false;
347
348 if (write_size != 0) {
349 payload.write = true;
350 /* should not set mot (middle of transaction) to 0
351 * if there are pending read payloads
352 */
353 payload.mot = !(read_size == 0);
354 payload.length = write_size;
355 payload.data = write_buf;
356
357 success = submit_aux_command(ddc, &payload);
358 }
359
360 if (read_size != 0 && success) {
361 payload.write = false;
362 /* should set mot (middle of transaction) to 0
363 * since it is the last payload to send
364 */
365 payload.mot = false;
366 payload.length = read_size;
367 payload.data = read_buf;
368
369 success = submit_aux_command(ddc, &payload);
370 }
371 } else {
372 struct i2c_command command = {0};
373 struct i2c_payloads payloads;
374
375 if (!i2c_payloads_create(ddc->ctx, &payloads, payloads_num))
376 return false;
377
378 command.payloads = i2c_payloads_get(&payloads);
379 command.number_of_payloads = 0;
380 command.engine = DDC_I2C_COMMAND_ENGINE;
381 command.speed = ddc->ctx->dc->caps.i2c_speed_in_khz;
382
383 i2c_payloads_add(
384 &payloads, address, write_size, write_buf, true);
385
386 i2c_payloads_add(
387 &payloads, address, read_size, read_buf, false);
388
389 command.number_of_payloads =
390 i2c_payloads_get_count(&payloads);
391
392 success = dm_helpers_submit_i2c(
393 ddc->ctx,
394 ddc->link,
395 &command);
396
397 i2c_payloads_destroy(&payloads);
398 }
399
400 return success;
401 }
402
link_aux_transfer_raw(struct ddc_service * ddc,struct aux_payload * payload,enum aux_return_code_type * operation_result)403 int link_aux_transfer_raw(struct ddc_service *ddc,
404 struct aux_payload *payload,
405 enum aux_return_code_type *operation_result)
406 {
407 if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc ||
408 !ddc->ddc_pin) {
409 return dce_aux_transfer_dmub_raw(ddc, payload, operation_result);
410 } else {
411 return dce_aux_transfer_raw(ddc, payload, operation_result);
412 }
413 }
414
link_get_fixed_vs_pe_retimer_write_address(struct dc_link * link)415 uint32_t link_get_fixed_vs_pe_retimer_write_address(struct dc_link *link)
416 {
417 uint32_t vendor_lttpr_write_address = 0xF004F;
418 uint8_t offset;
419
420 switch (link->dpcd_caps.lttpr_caps.phy_repeater_cnt) {
421 case 0x80: // 1 lttpr repeater
422 offset = 1;
423 break;
424 case 0x40: // 2 lttpr repeaters
425 offset = 2;
426 break;
427 case 0x20: // 3 lttpr repeaters
428 offset = 3;
429 break;
430 case 0x10: // 4 lttpr repeaters
431 offset = 4;
432 break;
433 case 0x08: // 5 lttpr repeaters
434 offset = 5;
435 break;
436 case 0x04: // 6 lttpr repeaters
437 offset = 6;
438 break;
439 case 0x02: // 7 lttpr repeaters
440 offset = 7;
441 break;
442 case 0x01: // 8 lttpr repeaters
443 offset = 8;
444 break;
445 default:
446 offset = 0xFF;
447 }
448
449 if (offset != 0xFF) {
450 vendor_lttpr_write_address +=
451 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
452 }
453 return vendor_lttpr_write_address;
454 }
455
link_get_fixed_vs_pe_retimer_read_address(struct dc_link * link)456 uint32_t link_get_fixed_vs_pe_retimer_read_address(struct dc_link *link)
457 {
458 return link_get_fixed_vs_pe_retimer_write_address(link) + 4;
459 }
460
link_configure_fixed_vs_pe_retimer(struct ddc_service * ddc,const uint8_t * data,uint32_t length)461 bool link_configure_fixed_vs_pe_retimer(struct ddc_service *ddc, const uint8_t *data, uint32_t length)
462 {
463 struct aux_payload write_payload = {
464 .i2c_over_aux = false,
465 .write = true,
466 .address = link_get_fixed_vs_pe_retimer_write_address(ddc->link),
467 .length = length,
468 .data = (uint8_t *) data,
469 .reply = NULL,
470 .mot = I2C_MOT_UNDEF,
471 .write_status_update = false,
472 .defer_delay = 0,
473 };
474
475 return link_aux_transfer_with_retries_no_mutex(ddc,
476 &write_payload);
477 }
478
link_query_fixed_vs_pe_retimer(struct ddc_service * ddc,uint8_t * data,uint32_t length)479 bool link_query_fixed_vs_pe_retimer(struct ddc_service *ddc, uint8_t *data, uint32_t length)
480 {
481 struct aux_payload read_payload = {
482 .i2c_over_aux = false,
483 .write = false,
484 .address = link_get_fixed_vs_pe_retimer_read_address(ddc->link),
485 .length = length,
486 .data = data,
487 .reply = NULL,
488 .mot = I2C_MOT_UNDEF,
489 .write_status_update = false,
490 .defer_delay = 0,
491 };
492
493 return link_aux_transfer_with_retries_no_mutex(ddc,
494 &read_payload);
495 }
496
link_aux_transfer_with_retries_no_mutex(struct ddc_service * ddc,struct aux_payload * payload)497 bool link_aux_transfer_with_retries_no_mutex(struct ddc_service *ddc,
498 struct aux_payload *payload)
499 {
500 return dce_aux_transfer_with_retries(ddc, payload);
501 }
502
503
try_to_configure_aux_timeout(struct ddc_service * ddc,uint32_t timeout)504 bool try_to_configure_aux_timeout(struct ddc_service *ddc,
505 uint32_t timeout)
506 {
507 bool result = false;
508 struct ddc *ddc_pin = ddc->ddc_pin;
509
510 if ((ddc->link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
511 !ddc->link->dc->debug.disable_fixed_vs_aux_timeout_wa &&
512 ddc->ctx->dce_version == DCN_VERSION_3_1) {
513 /* Fixed VS workaround for AUX timeout */
514 const uint32_t fixed_vs_address = 0xF004F;
515 const uint8_t fixed_vs_data[4] = {0x1, 0x22, 0x63, 0xc};
516
517 core_link_write_dpcd(ddc->link,
518 fixed_vs_address,
519 fixed_vs_data,
520 sizeof(fixed_vs_data));
521
522 timeout = 3072;
523 }
524
525 /* Do not try to access nonexistent DDC pin. */
526 if (ddc->link->ep_type != DISPLAY_ENDPOINT_PHY)
527 return true;
528
529 if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout) {
530 ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout);
531 result = true;
532 }
533
534 return result;
535 }
536
get_ddc_pin(struct ddc_service * ddc_service)537 struct ddc *get_ddc_pin(struct ddc_service *ddc_service)
538 {
539 return ddc_service->ddc_pin;
540 }
541
write_scdc_data(struct ddc_service * ddc_service,uint32_t pix_clk,bool lte_340_scramble)542 void write_scdc_data(struct ddc_service *ddc_service,
543 uint32_t pix_clk,
544 bool lte_340_scramble)
545 {
546 bool over_340_mhz = pix_clk > 340000 ? 1 : 0;
547 uint8_t slave_address = HDMI_SCDC_ADDRESS;
548 uint8_t offset = HDMI_SCDC_SINK_VERSION;
549 uint8_t sink_version = 0;
550 uint8_t write_buffer[2] = {0};
551 /*Lower than 340 Scramble bit from SCDC caps*/
552
553 if (ddc_service->link->local_sink &&
554 ddc_service->link->local_sink->edid_caps.panel_patch.skip_scdc_overwrite)
555 return;
556
557 link_query_ddc_data(ddc_service, slave_address, &offset,
558 sizeof(offset), &sink_version, sizeof(sink_version));
559 if (sink_version == 1) {
560 /*Source Version = 1*/
561 write_buffer[0] = HDMI_SCDC_SOURCE_VERSION;
562 write_buffer[1] = 1;
563 link_query_ddc_data(ddc_service, slave_address,
564 write_buffer, sizeof(write_buffer), NULL, 0);
565 /*Read Request from SCDC caps*/
566 }
567 write_buffer[0] = HDMI_SCDC_TMDS_CONFIG;
568
569 if (over_340_mhz) {
570 write_buffer[1] = 3;
571 } else if (lte_340_scramble) {
572 write_buffer[1] = 1;
573 } else {
574 write_buffer[1] = 0;
575 }
576 link_query_ddc_data(ddc_service, slave_address, write_buffer,
577 sizeof(write_buffer), NULL, 0);
578 }
579
read_scdc_data(struct ddc_service * ddc_service)580 void read_scdc_data(struct ddc_service *ddc_service)
581 {
582 uint8_t slave_address = HDMI_SCDC_ADDRESS;
583 uint8_t offset = HDMI_SCDC_TMDS_CONFIG;
584 uint8_t tmds_config = 0;
585
586 if (ddc_service->link->local_sink &&
587 ddc_service->link->local_sink->edid_caps.panel_patch.skip_scdc_overwrite)
588 return;
589
590 link_query_ddc_data(ddc_service, slave_address, &offset,
591 sizeof(offset), &tmds_config, sizeof(tmds_config));
592 if (tmds_config & 0x1) {
593 union hdmi_scdc_status_flags_data status_data = {0};
594 uint8_t scramble_status = 0;
595
596 offset = HDMI_SCDC_SCRAMBLER_STATUS;
597 link_query_ddc_data(ddc_service, slave_address,
598 &offset, sizeof(offset), &scramble_status,
599 sizeof(scramble_status));
600 offset = HDMI_SCDC_STATUS_FLAGS;
601 link_query_ddc_data(ddc_service, slave_address,
602 &offset, sizeof(offset), &status_data.byte,
603 sizeof(status_data.byte));
604 }
605 }
606