1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6 #include <drm/drm_blend.h>
7 #include <drm/drm_fourcc.h>
8 #include <drm/drm_framebuffer.h>
9
10 #include <linux/clk.h>
11 #include <linux/component.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/soc/mediatek/mtk-cmdq.h>
17
18 #include "mtk_disp_drv.h"
19 #include "mtk_drm_crtc.h"
20 #include "mtk_drm_ddp_comp.h"
21 #include "mtk_drm_drv.h"
22
23 #define DISP_REG_OVL_INTEN 0x0004
24 #define OVL_FME_CPL_INT BIT(1)
25 #define DISP_REG_OVL_INTSTA 0x0008
26 #define DISP_REG_OVL_EN 0x000c
27 #define DISP_REG_OVL_RST 0x0014
28 #define DISP_REG_OVL_ROI_SIZE 0x0020
29 #define DISP_REG_OVL_DATAPATH_CON 0x0024
30 #define OVL_LAYER_SMI_ID_EN BIT(0)
31 #define OVL_BGCLR_SEL_IN BIT(2)
32 #define OVL_LAYER_AFBC_EN(n) BIT(4+n)
33 #define DISP_REG_OVL_ROI_BGCLR 0x0028
34 #define DISP_REG_OVL_SRC_CON 0x002c
35 #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n))
36 #define DISP_REG_OVL_SRC_SIZE(n) (0x0038 + 0x20 * (n))
37 #define DISP_REG_OVL_OFFSET(n) (0x003c + 0x20 * (n))
38 #define DISP_REG_OVL_PITCH_MSB(n) (0x0040 + 0x20 * (n))
39 #define OVL_PITCH_MSB_2ND_SUBBUF BIT(16)
40 #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n))
41 #define OVL_CONST_BLEND BIT(28)
42 #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n))
43 #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n))
44 #define DISP_REG_OVL_ADDR_MT2701 0x0040
45 #define DISP_REG_OVL_CLRFMT_EXT 0x02D0
46 #define DISP_REG_OVL_ADDR_MT8173 0x0f40
47 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n))
48 #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04)
49 #define DISP_REG_OVL_HDR_PITCH(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x08)
50
51 #define GMC_THRESHOLD_BITS 16
52 #define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4)
53 #define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8)
54
55 #define OVL_CON_BYTE_SWAP BIT(24)
56 #define OVL_CON_MTX_YUV_TO_RGB (6 << 16)
57 #define OVL_CON_CLRFMT_RGB (1 << 12)
58 #define OVL_CON_CLRFMT_RGBA8888 (2 << 12)
59 #define OVL_CON_CLRFMT_ARGB8888 (3 << 12)
60 #define OVL_CON_CLRFMT_UYVY (4 << 12)
61 #define OVL_CON_CLRFMT_YUYV (5 << 12)
62 #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
63 0 : OVL_CON_CLRFMT_RGB)
64 #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
65 OVL_CON_CLRFMT_RGB : 0)
66 #define OVL_CON_CLRFMT_BIT_DEPTH_MASK(ovl) (0xFF << 4 * (ovl))
67 #define OVL_CON_CLRFMT_BIT_DEPTH(depth, ovl) (depth << 4 * (ovl))
68 #define OVL_CON_CLRFMT_8_BIT 0x00
69 #define OVL_CON_CLRFMT_10_BIT 0x01
70 #define OVL_CON_AEN BIT(8)
71 #define OVL_CON_ALPHA 0xff
72 #define OVL_CON_VIRT_FLIP BIT(9)
73 #define OVL_CON_HORZ_FLIP BIT(10)
74
75 #define OVL_COLOR_ALPHA GENMASK(31, 24)
76
77 static const u32 mt8173_formats[] = {
78 DRM_FORMAT_XRGB8888,
79 DRM_FORMAT_ARGB8888,
80 DRM_FORMAT_BGRX8888,
81 DRM_FORMAT_BGRA8888,
82 DRM_FORMAT_ABGR8888,
83 DRM_FORMAT_XBGR8888,
84 DRM_FORMAT_RGB888,
85 DRM_FORMAT_BGR888,
86 DRM_FORMAT_RGB565,
87 DRM_FORMAT_UYVY,
88 DRM_FORMAT_YUYV,
89 };
90
91 static const u32 mt8195_formats[] = {
92 DRM_FORMAT_XRGB8888,
93 DRM_FORMAT_ARGB8888,
94 DRM_FORMAT_ARGB2101010,
95 DRM_FORMAT_BGRX8888,
96 DRM_FORMAT_BGRA8888,
97 DRM_FORMAT_BGRA1010102,
98 DRM_FORMAT_ABGR8888,
99 DRM_FORMAT_XBGR8888,
100 DRM_FORMAT_RGB888,
101 DRM_FORMAT_BGR888,
102 DRM_FORMAT_RGB565,
103 DRM_FORMAT_UYVY,
104 DRM_FORMAT_YUYV,
105 };
106
107 struct mtk_disp_ovl_data {
108 unsigned int addr;
109 unsigned int gmc_bits;
110 unsigned int layer_nr;
111 bool fmt_rgb565_is_0;
112 bool smi_id_en;
113 bool supports_afbc;
114 const u32 *formats;
115 size_t num_formats;
116 bool supports_clrfmt_ext;
117 };
118
119 /*
120 * struct mtk_disp_ovl - DISP_OVL driver structure
121 * @crtc: associated crtc to report vblank events to
122 * @data: platform data
123 */
124 struct mtk_disp_ovl {
125 struct drm_crtc *crtc;
126 struct clk *clk;
127 void __iomem *regs;
128 struct cmdq_client_reg cmdq_reg;
129 const struct mtk_disp_ovl_data *data;
130 void (*vblank_cb)(void *data);
131 void *vblank_cb_data;
132 };
133
mtk_disp_ovl_irq_handler(int irq,void * dev_id)134 static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id)
135 {
136 struct mtk_disp_ovl *priv = dev_id;
137
138 /* Clear frame completion interrupt */
139 writel(0x0, priv->regs + DISP_REG_OVL_INTSTA);
140
141 if (!priv->vblank_cb)
142 return IRQ_NONE;
143
144 priv->vblank_cb(priv->vblank_cb_data);
145
146 return IRQ_HANDLED;
147 }
148
mtk_ovl_register_vblank_cb(struct device * dev,void (* vblank_cb)(void *),void * vblank_cb_data)149 void mtk_ovl_register_vblank_cb(struct device *dev,
150 void (*vblank_cb)(void *),
151 void *vblank_cb_data)
152 {
153 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
154
155 ovl->vblank_cb = vblank_cb;
156 ovl->vblank_cb_data = vblank_cb_data;
157 }
158
mtk_ovl_unregister_vblank_cb(struct device * dev)159 void mtk_ovl_unregister_vblank_cb(struct device *dev)
160 {
161 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
162
163 ovl->vblank_cb = NULL;
164 ovl->vblank_cb_data = NULL;
165 }
166
mtk_ovl_enable_vblank(struct device * dev)167 void mtk_ovl_enable_vblank(struct device *dev)
168 {
169 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
170
171 writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA);
172 writel_relaxed(OVL_FME_CPL_INT, ovl->regs + DISP_REG_OVL_INTEN);
173 }
174
mtk_ovl_disable_vblank(struct device * dev)175 void mtk_ovl_disable_vblank(struct device *dev)
176 {
177 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
178
179 writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN);
180 }
181
mtk_ovl_get_formats(struct device * dev)182 const u32 *mtk_ovl_get_formats(struct device *dev)
183 {
184 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
185
186 return ovl->data->formats;
187 }
188
mtk_ovl_get_num_formats(struct device * dev)189 size_t mtk_ovl_get_num_formats(struct device *dev)
190 {
191 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
192
193 return ovl->data->num_formats;
194 }
195
mtk_ovl_clk_enable(struct device * dev)196 int mtk_ovl_clk_enable(struct device *dev)
197 {
198 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
199
200 return clk_prepare_enable(ovl->clk);
201 }
202
mtk_ovl_clk_disable(struct device * dev)203 void mtk_ovl_clk_disable(struct device *dev)
204 {
205 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
206
207 clk_disable_unprepare(ovl->clk);
208 }
209
mtk_ovl_start(struct device * dev)210 void mtk_ovl_start(struct device *dev)
211 {
212 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
213
214 if (ovl->data->smi_id_en) {
215 unsigned int reg;
216
217 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
218 reg = reg | OVL_LAYER_SMI_ID_EN;
219 writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
220 }
221 writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);
222 }
223
mtk_ovl_stop(struct device * dev)224 void mtk_ovl_stop(struct device *dev)
225 {
226 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
227
228 writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN);
229 if (ovl->data->smi_id_en) {
230 unsigned int reg;
231
232 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
233 reg = reg & ~OVL_LAYER_SMI_ID_EN;
234 writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
235 }
236 }
237
mtk_ovl_set_afbc(struct mtk_disp_ovl * ovl,struct cmdq_pkt * cmdq_pkt,int idx,bool enabled)238 static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt,
239 int idx, bool enabled)
240 {
241 mtk_ddp_write_mask(cmdq_pkt, enabled ? OVL_LAYER_AFBC_EN(idx) : 0,
242 &ovl->cmdq_reg, ovl->regs,
243 DISP_REG_OVL_DATAPATH_CON, OVL_LAYER_AFBC_EN(idx));
244 }
245
mtk_ovl_set_bit_depth(struct device * dev,int idx,u32 format,struct cmdq_pkt * cmdq_pkt)246 static void mtk_ovl_set_bit_depth(struct device *dev, int idx, u32 format,
247 struct cmdq_pkt *cmdq_pkt)
248 {
249 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
250 unsigned int reg;
251 unsigned int bit_depth = OVL_CON_CLRFMT_8_BIT;
252
253 if (!ovl->data->supports_clrfmt_ext)
254 return;
255
256 reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT);
257 reg &= ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx);
258
259 if (format == DRM_FORMAT_RGBA1010102 ||
260 format == DRM_FORMAT_BGRA1010102 ||
261 format == DRM_FORMAT_ARGB2101010)
262 bit_depth = OVL_CON_CLRFMT_10_BIT;
263
264 reg |= OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx);
265
266 mtk_ddp_write(cmdq_pkt, reg, &ovl->cmdq_reg,
267 ovl->regs, DISP_REG_OVL_CLRFMT_EXT);
268 }
269
mtk_ovl_config(struct device * dev,unsigned int w,unsigned int h,unsigned int vrefresh,unsigned int bpc,struct cmdq_pkt * cmdq_pkt)270 void mtk_ovl_config(struct device *dev, unsigned int w,
271 unsigned int h, unsigned int vrefresh,
272 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
273 {
274 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
275
276 if (w != 0 && h != 0)
277 mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs,
278 DISP_REG_OVL_ROI_SIZE);
279
280 /*
281 * The background color must be opaque black (ARGB),
282 * otherwise the alpha blending will have no effect
283 */
284 mtk_ddp_write_relaxed(cmdq_pkt, OVL_COLOR_ALPHA, &ovl->cmdq_reg,
285 ovl->regs, DISP_REG_OVL_ROI_BGCLR);
286
287 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);
288 mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);
289 }
290
mtk_ovl_layer_nr(struct device * dev)291 unsigned int mtk_ovl_layer_nr(struct device *dev)
292 {
293 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
294
295 return ovl->data->layer_nr;
296 }
297
mtk_ovl_supported_rotations(struct device * dev)298 unsigned int mtk_ovl_supported_rotations(struct device *dev)
299 {
300 return DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
301 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
302 }
303
mtk_ovl_layer_check(struct device * dev,unsigned int idx,struct mtk_plane_state * mtk_state)304 int mtk_ovl_layer_check(struct device *dev, unsigned int idx,
305 struct mtk_plane_state *mtk_state)
306 {
307 struct drm_plane_state *state = &mtk_state->base;
308 unsigned int rotation = 0;
309
310 rotation = drm_rotation_simplify(state->rotation,
311 DRM_MODE_ROTATE_0 |
312 DRM_MODE_REFLECT_X |
313 DRM_MODE_REFLECT_Y);
314 rotation &= ~DRM_MODE_ROTATE_0;
315
316 /* We can only do reflection, not rotation */
317 if ((rotation & DRM_MODE_ROTATE_MASK) != 0)
318 return -EINVAL;
319
320 /*
321 * TODO: Rotating/reflecting YUV buffers is not supported at this time.
322 * Only RGB[AX] variants are supported.
323 */
324 if (state->fb->format->is_yuv && rotation != 0)
325 return -EINVAL;
326
327 state->rotation = rotation;
328
329 return 0;
330 }
331
mtk_ovl_layer_on(struct device * dev,unsigned int idx,struct cmdq_pkt * cmdq_pkt)332 void mtk_ovl_layer_on(struct device *dev, unsigned int idx,
333 struct cmdq_pkt *cmdq_pkt)
334 {
335 unsigned int gmc_thrshd_l;
336 unsigned int gmc_thrshd_h;
337 unsigned int gmc_value;
338 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
339
340 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,
341 DISP_REG_OVL_RDMA_CTRL(idx));
342 gmc_thrshd_l = GMC_THRESHOLD_LOW >>
343 (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
344 gmc_thrshd_h = GMC_THRESHOLD_HIGH >>
345 (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
346 if (ovl->data->gmc_bits == 10)
347 gmc_value = gmc_thrshd_h | gmc_thrshd_h << 16;
348 else
349 gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 |
350 gmc_thrshd_h << 16 | gmc_thrshd_h << 24;
351 mtk_ddp_write(cmdq_pkt, gmc_value,
352 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx));
353 mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs,
354 DISP_REG_OVL_SRC_CON, BIT(idx));
355 }
356
mtk_ovl_layer_off(struct device * dev,unsigned int idx,struct cmdq_pkt * cmdq_pkt)357 void mtk_ovl_layer_off(struct device *dev, unsigned int idx,
358 struct cmdq_pkt *cmdq_pkt)
359 {
360 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
361
362 mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,
363 DISP_REG_OVL_SRC_CON, BIT(idx));
364 mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,
365 DISP_REG_OVL_RDMA_CTRL(idx));
366 }
367
ovl_fmt_convert(struct mtk_disp_ovl * ovl,unsigned int fmt)368 static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
369 {
370 /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
371 * is defined in mediatek HW data sheet.
372 * The alphabet order in XXX is no relation to data
373 * arrangement in memory.
374 */
375 switch (fmt) {
376 default:
377 case DRM_FORMAT_RGB565:
378 return OVL_CON_CLRFMT_RGB565(ovl);
379 case DRM_FORMAT_BGR565:
380 return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP;
381 case DRM_FORMAT_RGB888:
382 return OVL_CON_CLRFMT_RGB888(ovl);
383 case DRM_FORMAT_BGR888:
384 return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP;
385 case DRM_FORMAT_RGBX8888:
386 case DRM_FORMAT_RGBA8888:
387 return OVL_CON_CLRFMT_ARGB8888;
388 case DRM_FORMAT_BGRX8888:
389 case DRM_FORMAT_BGRA8888:
390 case DRM_FORMAT_BGRA1010102:
391 return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP;
392 case DRM_FORMAT_XRGB8888:
393 case DRM_FORMAT_ARGB8888:
394 case DRM_FORMAT_ARGB2101010:
395 return OVL_CON_CLRFMT_RGBA8888;
396 case DRM_FORMAT_XBGR8888:
397 case DRM_FORMAT_ABGR8888:
398 return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP;
399 case DRM_FORMAT_UYVY:
400 return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB;
401 case DRM_FORMAT_YUYV:
402 return OVL_CON_CLRFMT_YUYV | OVL_CON_MTX_YUV_TO_RGB;
403 }
404 }
405
mtk_ovl_layer_config(struct device * dev,unsigned int idx,struct mtk_plane_state * state,struct cmdq_pkt * cmdq_pkt)406 void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
407 struct mtk_plane_state *state,
408 struct cmdq_pkt *cmdq_pkt)
409 {
410 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
411 struct mtk_plane_pending_state *pending = &state->pending;
412 unsigned int addr = pending->addr;
413 unsigned int hdr_addr = pending->hdr_addr;
414 unsigned int pitch = pending->pitch;
415 unsigned int hdr_pitch = pending->hdr_pitch;
416 unsigned int fmt = pending->format;
417 unsigned int offset = (pending->y << 16) | pending->x;
418 unsigned int src_size = (pending->height << 16) | pending->width;
419 unsigned int ignore_pixel_alpha = 0;
420 unsigned int con;
421 bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR;
422 union overlay_pitch {
423 struct split_pitch {
424 u16 lsb;
425 u16 msb;
426 } split_pitch;
427 u32 pitch;
428 } overlay_pitch;
429
430 overlay_pitch.pitch = pitch;
431
432 if (!pending->enable) {
433 mtk_ovl_layer_off(dev, idx, cmdq_pkt);
434 return;
435 }
436
437 con = ovl_fmt_convert(ovl, fmt);
438 if (state->base.fb && state->base.fb->format->has_alpha)
439 con |= OVL_CON_AEN | OVL_CON_ALPHA;
440
441 /* CONST_BLD must be enabled for XRGB formats although the alpha channel
442 * can be ignored, or OVL will still read the value from memory.
443 * For RGB888 related formats, whether CONST_BLD is enabled or not won't
444 * affect the result. Therefore we use !has_alpha as the condition.
445 */
446 if (state->base.fb && !state->base.fb->format->has_alpha)
447 ignore_pixel_alpha = OVL_CONST_BLEND;
448
449 if (pending->rotation & DRM_MODE_REFLECT_Y) {
450 con |= OVL_CON_VIRT_FLIP;
451 addr += (pending->height - 1) * pending->pitch;
452 }
453
454 if (pending->rotation & DRM_MODE_REFLECT_X) {
455 con |= OVL_CON_HORZ_FLIP;
456 addr += pending->pitch - 1;
457 }
458
459 if (ovl->data->supports_afbc)
460 mtk_ovl_set_afbc(ovl, cmdq_pkt, idx, is_afbc);
461
462 mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,
463 DISP_REG_OVL_CON(idx));
464 mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb | ignore_pixel_alpha,
465 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx));
466 mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,
467 DISP_REG_OVL_SRC_SIZE(idx));
468 mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,
469 DISP_REG_OVL_OFFSET(idx));
470 mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs,
471 DISP_REG_OVL_ADDR(ovl, idx));
472
473 if (is_afbc) {
474 mtk_ddp_write_relaxed(cmdq_pkt, hdr_addr, &ovl->cmdq_reg, ovl->regs,
475 DISP_REG_OVL_HDR_ADDR(ovl, idx));
476 mtk_ddp_write_relaxed(cmdq_pkt,
477 OVL_PITCH_MSB_2ND_SUBBUF | overlay_pitch.split_pitch.msb,
478 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx));
479 mtk_ddp_write_relaxed(cmdq_pkt, hdr_pitch, &ovl->cmdq_reg, ovl->regs,
480 DISP_REG_OVL_HDR_PITCH(ovl, idx));
481 } else {
482 mtk_ddp_write_relaxed(cmdq_pkt,
483 overlay_pitch.split_pitch.msb,
484 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx));
485 }
486
487 mtk_ovl_set_bit_depth(dev, idx, fmt, cmdq_pkt);
488 mtk_ovl_layer_on(dev, idx, cmdq_pkt);
489 }
490
mtk_ovl_bgclr_in_on(struct device * dev)491 void mtk_ovl_bgclr_in_on(struct device *dev)
492 {
493 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
494 unsigned int reg;
495
496 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
497 reg = reg | OVL_BGCLR_SEL_IN;
498 writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
499 }
500
mtk_ovl_bgclr_in_off(struct device * dev)501 void mtk_ovl_bgclr_in_off(struct device *dev)
502 {
503 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
504 unsigned int reg;
505
506 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
507 reg = reg & ~OVL_BGCLR_SEL_IN;
508 writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
509 }
510
mtk_disp_ovl_bind(struct device * dev,struct device * master,void * data)511 static int mtk_disp_ovl_bind(struct device *dev, struct device *master,
512 void *data)
513 {
514 return 0;
515 }
516
mtk_disp_ovl_unbind(struct device * dev,struct device * master,void * data)517 static void mtk_disp_ovl_unbind(struct device *dev, struct device *master,
518 void *data)
519 {
520 }
521
522 static const struct component_ops mtk_disp_ovl_component_ops = {
523 .bind = mtk_disp_ovl_bind,
524 .unbind = mtk_disp_ovl_unbind,
525 };
526
mtk_disp_ovl_probe(struct platform_device * pdev)527 static int mtk_disp_ovl_probe(struct platform_device *pdev)
528 {
529 struct device *dev = &pdev->dev;
530 struct mtk_disp_ovl *priv;
531 struct resource *res;
532 int irq;
533 int ret;
534
535 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
536 if (!priv)
537 return -ENOMEM;
538
539 irq = platform_get_irq(pdev, 0);
540 if (irq < 0)
541 return irq;
542
543 priv->clk = devm_clk_get(dev, NULL);
544 if (IS_ERR(priv->clk)) {
545 dev_err(dev, "failed to get ovl clk\n");
546 return PTR_ERR(priv->clk);
547 }
548
549 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
550 priv->regs = devm_ioremap_resource(dev, res);
551 if (IS_ERR(priv->regs)) {
552 dev_err(dev, "failed to ioremap ovl\n");
553 return PTR_ERR(priv->regs);
554 }
555 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
556 ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
557 if (ret)
558 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
559 #endif
560
561 priv->data = of_device_get_match_data(dev);
562 platform_set_drvdata(pdev, priv);
563
564 ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler,
565 IRQF_TRIGGER_NONE, dev_name(dev), priv);
566 if (ret < 0) {
567 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
568 return ret;
569 }
570
571 pm_runtime_enable(dev);
572
573 ret = component_add(dev, &mtk_disp_ovl_component_ops);
574 if (ret) {
575 pm_runtime_disable(dev);
576 dev_err(dev, "Failed to add component: %d\n", ret);
577 }
578
579 return ret;
580 }
581
mtk_disp_ovl_remove(struct platform_device * pdev)582 static void mtk_disp_ovl_remove(struct platform_device *pdev)
583 {
584 component_del(&pdev->dev, &mtk_disp_ovl_component_ops);
585 pm_runtime_disable(&pdev->dev);
586 }
587
588 static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
589 .addr = DISP_REG_OVL_ADDR_MT2701,
590 .gmc_bits = 8,
591 .layer_nr = 4,
592 .fmt_rgb565_is_0 = false,
593 .formats = mt8173_formats,
594 .num_formats = ARRAY_SIZE(mt8173_formats),
595 };
596
597 static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
598 .addr = DISP_REG_OVL_ADDR_MT8173,
599 .gmc_bits = 8,
600 .layer_nr = 4,
601 .fmt_rgb565_is_0 = true,
602 .formats = mt8173_formats,
603 .num_formats = ARRAY_SIZE(mt8173_formats),
604 };
605
606 static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
607 .addr = DISP_REG_OVL_ADDR_MT8173,
608 .gmc_bits = 10,
609 .layer_nr = 4,
610 .fmt_rgb565_is_0 = true,
611 .formats = mt8173_formats,
612 .num_formats = ARRAY_SIZE(mt8173_formats),
613 };
614
615 static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
616 .addr = DISP_REG_OVL_ADDR_MT8173,
617 .gmc_bits = 10,
618 .layer_nr = 2,
619 .fmt_rgb565_is_0 = true,
620 .formats = mt8173_formats,
621 .num_formats = ARRAY_SIZE(mt8173_formats),
622 };
623
624 static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
625 .addr = DISP_REG_OVL_ADDR_MT8173,
626 .gmc_bits = 10,
627 .layer_nr = 4,
628 .fmt_rgb565_is_0 = true,
629 .smi_id_en = true,
630 .formats = mt8173_formats,
631 .num_formats = ARRAY_SIZE(mt8173_formats),
632 };
633
634 static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
635 .addr = DISP_REG_OVL_ADDR_MT8173,
636 .gmc_bits = 10,
637 .layer_nr = 2,
638 .fmt_rgb565_is_0 = true,
639 .smi_id_en = true,
640 .formats = mt8173_formats,
641 .num_formats = ARRAY_SIZE(mt8173_formats),
642 };
643
644 static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {
645 .addr = DISP_REG_OVL_ADDR_MT8173,
646 .gmc_bits = 10,
647 .layer_nr = 4,
648 .fmt_rgb565_is_0 = true,
649 .smi_id_en = true,
650 .supports_afbc = true,
651 .formats = mt8195_formats,
652 .num_formats = ARRAY_SIZE(mt8195_formats),
653 .supports_clrfmt_ext = true,
654 };
655
656 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
657 { .compatible = "mediatek,mt2701-disp-ovl",
658 .data = &mt2701_ovl_driver_data},
659 { .compatible = "mediatek,mt8173-disp-ovl",
660 .data = &mt8173_ovl_driver_data},
661 { .compatible = "mediatek,mt8183-disp-ovl",
662 .data = &mt8183_ovl_driver_data},
663 { .compatible = "mediatek,mt8183-disp-ovl-2l",
664 .data = &mt8183_ovl_2l_driver_data},
665 { .compatible = "mediatek,mt8192-disp-ovl",
666 .data = &mt8192_ovl_driver_data},
667 { .compatible = "mediatek,mt8192-disp-ovl-2l",
668 .data = &mt8192_ovl_2l_driver_data},
669 { .compatible = "mediatek,mt8195-disp-ovl",
670 .data = &mt8195_ovl_driver_data},
671 {},
672 };
673 MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
674
675 struct platform_driver mtk_disp_ovl_driver = {
676 .probe = mtk_disp_ovl_probe,
677 .remove_new = mtk_disp_ovl_remove,
678 .driver = {
679 .name = "mediatek-disp-ovl",
680 .owner = THIS_MODULE,
681 .of_match_table = mtk_disp_ovl_driver_dt_match,
682 },
683 };
684