1 /*
2 * Driver header file for the ST Microelectronics SPEAr pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <vireshk@kernel.org>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #ifndef __PINMUX_SPEAR_H__
13 #define __PINMUX_SPEAR_H__
14
15 #include <linux/gpio/driver.h>
16 #include <linux/io.h>
17 #include <linux/pinctrl/pinctrl.h>
18 #include <linux/regmap.h>
19 #include <linux/types.h>
20
21 struct platform_device;
22 struct device;
23 struct spear_pmx;
24
25 /**
26 * struct spear_pmx_mode - SPEAr pmx mode
27 * @name: name of pmx mode
28 * @mode: mode id
29 * @reg: register for configuring this mode
30 * @mask: mask of this mode in reg
31 * @val: val to be configured at reg after doing (val & mask)
32 */
33 struct spear_pmx_mode {
34 const char *const name;
35 u16 mode;
36 u16 reg;
37 u16 mask;
38 u32 val;
39 };
40
41 /**
42 * struct spear_muxreg - SPEAr mux reg configuration
43 * @reg: register offset
44 * @mask: mask bits
45 * @val: val to be written on mask bits
46 */
47 struct spear_muxreg {
48 u16 reg;
49 u32 mask;
50 u32 val;
51 };
52
53 struct spear_gpio_pingroup {
54 const unsigned *pins;
55 unsigned npins;
56 struct spear_muxreg *muxregs;
57 u8 nmuxregs;
58 };
59
60 /* ste: set to enable */
61 #define DEFINE_MUXREG(__pins, __muxreg, __mask, __ste) \
62 static struct spear_muxreg __pins##_muxregs[] = { \
63 { \
64 .reg = __muxreg, \
65 .mask = __mask, \
66 .val = __ste ? __mask : 0, \
67 }, \
68 }
69
70 #define DEFINE_2_MUXREG(__pins, __muxreg1, __muxreg2, __mask, __ste1, __ste2) \
71 static struct spear_muxreg __pins##_muxregs[] = { \
72 { \
73 .reg = __muxreg1, \
74 .mask = __mask, \
75 .val = __ste1 ? __mask : 0, \
76 }, { \
77 .reg = __muxreg2, \
78 .mask = __mask, \
79 .val = __ste2 ? __mask : 0, \
80 }, \
81 }
82
83 #define GPIO_PINGROUP(__pins) \
84 { \
85 .pins = __pins, \
86 .npins = ARRAY_SIZE(__pins), \
87 .muxregs = __pins##_muxregs, \
88 .nmuxregs = ARRAY_SIZE(__pins##_muxregs), \
89 }
90
91 /**
92 * struct spear_modemux - SPEAr mode mux configuration
93 * @modes: mode ids supported by this group of muxregs
94 * @nmuxregs: number of muxreg configurations to be done for modes
95 * @muxregs: array of muxreg configurations to be done for modes
96 */
97 struct spear_modemux {
98 u16 modes;
99 u8 nmuxregs;
100 struct spear_muxreg *muxregs;
101 };
102
103 /**
104 * struct spear_pingroup - SPEAr pin group configurations
105 * @name: name of pin group
106 * @pins: array containing pin numbers
107 * @npins: size of pins array
108 * @modemuxs: array of modemux configurations for this pin group
109 * @nmodemuxs: size of array modemuxs
110 *
111 * A representation of a group of pins in the SPEAr pin controller. Each group
112 * allows some parameter or parameters to be configured.
113 */
114 struct spear_pingroup {
115 const char *name;
116 const unsigned *pins;
117 unsigned npins;
118 struct spear_modemux *modemuxs;
119 unsigned nmodemuxs;
120 };
121
122 /**
123 * struct spear_function - SPEAr pinctrl mux function
124 * @name: The name of the function, exported to pinctrl core.
125 * @groups: An array of pin groups that may select this function.
126 * @ngroups: The number of entries in @groups.
127 */
128 struct spear_function {
129 const char *name;
130 const char *const *groups;
131 unsigned ngroups;
132 };
133
134 /**
135 * struct spear_pinctrl_machdata - SPEAr pin controller machine driver
136 * configuration
137 * @pins: An array describing all pins the pin controller affects.
138 * All pins which are also GPIOs must be listed first within the *array,
139 * and be numbered identically to the GPIO controller's *numbering.
140 * @npins: The numbmer of entries in @pins.
141 * @functions: An array describing all mux functions the SoC supports.
142 * @nfunctions: The numbmer of entries in @functions.
143 * @groups: An array describing all pin groups the pin SoC supports.
144 * @ngroups: The numbmer of entries in @groups.
145 * @gpio_pingroups: gpio pingroups
146 * @ngpio_pingroups: gpio pingroups count
147 *
148 * @modes_supported: Does SoC support modes
149 * @mode: mode configured from probe
150 * @pmx_modes: array of modes supported by SoC
151 * @npmx_modes: number of entries in pmx_modes.
152 */
153 struct spear_pinctrl_machdata {
154 const struct pinctrl_pin_desc *pins;
155 unsigned npins;
156 struct spear_function **functions;
157 unsigned nfunctions;
158 struct spear_pingroup **groups;
159 unsigned ngroups;
160 struct spear_gpio_pingroup *gpio_pingroups;
161 void (*gpio_request_endisable)(struct spear_pmx *pmx, int offset,
162 bool enable);
163 unsigned ngpio_pingroups;
164
165 bool modes_supported;
166 u16 mode;
167 struct spear_pmx_mode **pmx_modes;
168 unsigned npmx_modes;
169 };
170
171 /**
172 * struct spear_pmx - SPEAr pinctrl mux
173 * @dev: pointer to struct dev of platform_device registered
174 * @pctl: pointer to struct pinctrl_dev
175 * @machdata: pointer to SoC or machine specific structure
176 * @regmap: regmap of pinmux controller
177 */
178 struct spear_pmx {
179 struct device *dev;
180 struct pinctrl_dev *pctl;
181 struct spear_pinctrl_machdata *machdata;
182 struct regmap *regmap;
183 };
184
185 /* exported routines */
pmx_readl(struct spear_pmx * pmx,u32 reg)186 static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg)
187 {
188 u32 val;
189
190 regmap_read(pmx->regmap, reg, &val);
191 return val;
192 }
193
pmx_writel(struct spear_pmx * pmx,u32 val,u32 reg)194 static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg)
195 {
196 regmap_write(pmx->regmap, reg, val);
197 }
198
199 void pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
200 void pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup,
201 unsigned count, u16 reg);
202 int spear_pinctrl_probe(struct platform_device *pdev,
203 struct spear_pinctrl_machdata *machdata);
204
205 #define SPEAR_PIN_0_TO_101 \
206 PINCTRL_PIN(0, "PLGPIO0"), \
207 PINCTRL_PIN(1, "PLGPIO1"), \
208 PINCTRL_PIN(2, "PLGPIO2"), \
209 PINCTRL_PIN(3, "PLGPIO3"), \
210 PINCTRL_PIN(4, "PLGPIO4"), \
211 PINCTRL_PIN(5, "PLGPIO5"), \
212 PINCTRL_PIN(6, "PLGPIO6"), \
213 PINCTRL_PIN(7, "PLGPIO7"), \
214 PINCTRL_PIN(8, "PLGPIO8"), \
215 PINCTRL_PIN(9, "PLGPIO9"), \
216 PINCTRL_PIN(10, "PLGPIO10"), \
217 PINCTRL_PIN(11, "PLGPIO11"), \
218 PINCTRL_PIN(12, "PLGPIO12"), \
219 PINCTRL_PIN(13, "PLGPIO13"), \
220 PINCTRL_PIN(14, "PLGPIO14"), \
221 PINCTRL_PIN(15, "PLGPIO15"), \
222 PINCTRL_PIN(16, "PLGPIO16"), \
223 PINCTRL_PIN(17, "PLGPIO17"), \
224 PINCTRL_PIN(18, "PLGPIO18"), \
225 PINCTRL_PIN(19, "PLGPIO19"), \
226 PINCTRL_PIN(20, "PLGPIO20"), \
227 PINCTRL_PIN(21, "PLGPIO21"), \
228 PINCTRL_PIN(22, "PLGPIO22"), \
229 PINCTRL_PIN(23, "PLGPIO23"), \
230 PINCTRL_PIN(24, "PLGPIO24"), \
231 PINCTRL_PIN(25, "PLGPIO25"), \
232 PINCTRL_PIN(26, "PLGPIO26"), \
233 PINCTRL_PIN(27, "PLGPIO27"), \
234 PINCTRL_PIN(28, "PLGPIO28"), \
235 PINCTRL_PIN(29, "PLGPIO29"), \
236 PINCTRL_PIN(30, "PLGPIO30"), \
237 PINCTRL_PIN(31, "PLGPIO31"), \
238 PINCTRL_PIN(32, "PLGPIO32"), \
239 PINCTRL_PIN(33, "PLGPIO33"), \
240 PINCTRL_PIN(34, "PLGPIO34"), \
241 PINCTRL_PIN(35, "PLGPIO35"), \
242 PINCTRL_PIN(36, "PLGPIO36"), \
243 PINCTRL_PIN(37, "PLGPIO37"), \
244 PINCTRL_PIN(38, "PLGPIO38"), \
245 PINCTRL_PIN(39, "PLGPIO39"), \
246 PINCTRL_PIN(40, "PLGPIO40"), \
247 PINCTRL_PIN(41, "PLGPIO41"), \
248 PINCTRL_PIN(42, "PLGPIO42"), \
249 PINCTRL_PIN(43, "PLGPIO43"), \
250 PINCTRL_PIN(44, "PLGPIO44"), \
251 PINCTRL_PIN(45, "PLGPIO45"), \
252 PINCTRL_PIN(46, "PLGPIO46"), \
253 PINCTRL_PIN(47, "PLGPIO47"), \
254 PINCTRL_PIN(48, "PLGPIO48"), \
255 PINCTRL_PIN(49, "PLGPIO49"), \
256 PINCTRL_PIN(50, "PLGPIO50"), \
257 PINCTRL_PIN(51, "PLGPIO51"), \
258 PINCTRL_PIN(52, "PLGPIO52"), \
259 PINCTRL_PIN(53, "PLGPIO53"), \
260 PINCTRL_PIN(54, "PLGPIO54"), \
261 PINCTRL_PIN(55, "PLGPIO55"), \
262 PINCTRL_PIN(56, "PLGPIO56"), \
263 PINCTRL_PIN(57, "PLGPIO57"), \
264 PINCTRL_PIN(58, "PLGPIO58"), \
265 PINCTRL_PIN(59, "PLGPIO59"), \
266 PINCTRL_PIN(60, "PLGPIO60"), \
267 PINCTRL_PIN(61, "PLGPIO61"), \
268 PINCTRL_PIN(62, "PLGPIO62"), \
269 PINCTRL_PIN(63, "PLGPIO63"), \
270 PINCTRL_PIN(64, "PLGPIO64"), \
271 PINCTRL_PIN(65, "PLGPIO65"), \
272 PINCTRL_PIN(66, "PLGPIO66"), \
273 PINCTRL_PIN(67, "PLGPIO67"), \
274 PINCTRL_PIN(68, "PLGPIO68"), \
275 PINCTRL_PIN(69, "PLGPIO69"), \
276 PINCTRL_PIN(70, "PLGPIO70"), \
277 PINCTRL_PIN(71, "PLGPIO71"), \
278 PINCTRL_PIN(72, "PLGPIO72"), \
279 PINCTRL_PIN(73, "PLGPIO73"), \
280 PINCTRL_PIN(74, "PLGPIO74"), \
281 PINCTRL_PIN(75, "PLGPIO75"), \
282 PINCTRL_PIN(76, "PLGPIO76"), \
283 PINCTRL_PIN(77, "PLGPIO77"), \
284 PINCTRL_PIN(78, "PLGPIO78"), \
285 PINCTRL_PIN(79, "PLGPIO79"), \
286 PINCTRL_PIN(80, "PLGPIO80"), \
287 PINCTRL_PIN(81, "PLGPIO81"), \
288 PINCTRL_PIN(82, "PLGPIO82"), \
289 PINCTRL_PIN(83, "PLGPIO83"), \
290 PINCTRL_PIN(84, "PLGPIO84"), \
291 PINCTRL_PIN(85, "PLGPIO85"), \
292 PINCTRL_PIN(86, "PLGPIO86"), \
293 PINCTRL_PIN(87, "PLGPIO87"), \
294 PINCTRL_PIN(88, "PLGPIO88"), \
295 PINCTRL_PIN(89, "PLGPIO89"), \
296 PINCTRL_PIN(90, "PLGPIO90"), \
297 PINCTRL_PIN(91, "PLGPIO91"), \
298 PINCTRL_PIN(92, "PLGPIO92"), \
299 PINCTRL_PIN(93, "PLGPIO93"), \
300 PINCTRL_PIN(94, "PLGPIO94"), \
301 PINCTRL_PIN(95, "PLGPIO95"), \
302 PINCTRL_PIN(96, "PLGPIO96"), \
303 PINCTRL_PIN(97, "PLGPIO97"), \
304 PINCTRL_PIN(98, "PLGPIO98"), \
305 PINCTRL_PIN(99, "PLGPIO99"), \
306 PINCTRL_PIN(100, "PLGPIO100"), \
307 PINCTRL_PIN(101, "PLGPIO101")
308
309 #define SPEAR_PIN_102_TO_245 \
310 PINCTRL_PIN(102, "PLGPIO102"), \
311 PINCTRL_PIN(103, "PLGPIO103"), \
312 PINCTRL_PIN(104, "PLGPIO104"), \
313 PINCTRL_PIN(105, "PLGPIO105"), \
314 PINCTRL_PIN(106, "PLGPIO106"), \
315 PINCTRL_PIN(107, "PLGPIO107"), \
316 PINCTRL_PIN(108, "PLGPIO108"), \
317 PINCTRL_PIN(109, "PLGPIO109"), \
318 PINCTRL_PIN(110, "PLGPIO110"), \
319 PINCTRL_PIN(111, "PLGPIO111"), \
320 PINCTRL_PIN(112, "PLGPIO112"), \
321 PINCTRL_PIN(113, "PLGPIO113"), \
322 PINCTRL_PIN(114, "PLGPIO114"), \
323 PINCTRL_PIN(115, "PLGPIO115"), \
324 PINCTRL_PIN(116, "PLGPIO116"), \
325 PINCTRL_PIN(117, "PLGPIO117"), \
326 PINCTRL_PIN(118, "PLGPIO118"), \
327 PINCTRL_PIN(119, "PLGPIO119"), \
328 PINCTRL_PIN(120, "PLGPIO120"), \
329 PINCTRL_PIN(121, "PLGPIO121"), \
330 PINCTRL_PIN(122, "PLGPIO122"), \
331 PINCTRL_PIN(123, "PLGPIO123"), \
332 PINCTRL_PIN(124, "PLGPIO124"), \
333 PINCTRL_PIN(125, "PLGPIO125"), \
334 PINCTRL_PIN(126, "PLGPIO126"), \
335 PINCTRL_PIN(127, "PLGPIO127"), \
336 PINCTRL_PIN(128, "PLGPIO128"), \
337 PINCTRL_PIN(129, "PLGPIO129"), \
338 PINCTRL_PIN(130, "PLGPIO130"), \
339 PINCTRL_PIN(131, "PLGPIO131"), \
340 PINCTRL_PIN(132, "PLGPIO132"), \
341 PINCTRL_PIN(133, "PLGPIO133"), \
342 PINCTRL_PIN(134, "PLGPIO134"), \
343 PINCTRL_PIN(135, "PLGPIO135"), \
344 PINCTRL_PIN(136, "PLGPIO136"), \
345 PINCTRL_PIN(137, "PLGPIO137"), \
346 PINCTRL_PIN(138, "PLGPIO138"), \
347 PINCTRL_PIN(139, "PLGPIO139"), \
348 PINCTRL_PIN(140, "PLGPIO140"), \
349 PINCTRL_PIN(141, "PLGPIO141"), \
350 PINCTRL_PIN(142, "PLGPIO142"), \
351 PINCTRL_PIN(143, "PLGPIO143"), \
352 PINCTRL_PIN(144, "PLGPIO144"), \
353 PINCTRL_PIN(145, "PLGPIO145"), \
354 PINCTRL_PIN(146, "PLGPIO146"), \
355 PINCTRL_PIN(147, "PLGPIO147"), \
356 PINCTRL_PIN(148, "PLGPIO148"), \
357 PINCTRL_PIN(149, "PLGPIO149"), \
358 PINCTRL_PIN(150, "PLGPIO150"), \
359 PINCTRL_PIN(151, "PLGPIO151"), \
360 PINCTRL_PIN(152, "PLGPIO152"), \
361 PINCTRL_PIN(153, "PLGPIO153"), \
362 PINCTRL_PIN(154, "PLGPIO154"), \
363 PINCTRL_PIN(155, "PLGPIO155"), \
364 PINCTRL_PIN(156, "PLGPIO156"), \
365 PINCTRL_PIN(157, "PLGPIO157"), \
366 PINCTRL_PIN(158, "PLGPIO158"), \
367 PINCTRL_PIN(159, "PLGPIO159"), \
368 PINCTRL_PIN(160, "PLGPIO160"), \
369 PINCTRL_PIN(161, "PLGPIO161"), \
370 PINCTRL_PIN(162, "PLGPIO162"), \
371 PINCTRL_PIN(163, "PLGPIO163"), \
372 PINCTRL_PIN(164, "PLGPIO164"), \
373 PINCTRL_PIN(165, "PLGPIO165"), \
374 PINCTRL_PIN(166, "PLGPIO166"), \
375 PINCTRL_PIN(167, "PLGPIO167"), \
376 PINCTRL_PIN(168, "PLGPIO168"), \
377 PINCTRL_PIN(169, "PLGPIO169"), \
378 PINCTRL_PIN(170, "PLGPIO170"), \
379 PINCTRL_PIN(171, "PLGPIO171"), \
380 PINCTRL_PIN(172, "PLGPIO172"), \
381 PINCTRL_PIN(173, "PLGPIO173"), \
382 PINCTRL_PIN(174, "PLGPIO174"), \
383 PINCTRL_PIN(175, "PLGPIO175"), \
384 PINCTRL_PIN(176, "PLGPIO176"), \
385 PINCTRL_PIN(177, "PLGPIO177"), \
386 PINCTRL_PIN(178, "PLGPIO178"), \
387 PINCTRL_PIN(179, "PLGPIO179"), \
388 PINCTRL_PIN(180, "PLGPIO180"), \
389 PINCTRL_PIN(181, "PLGPIO181"), \
390 PINCTRL_PIN(182, "PLGPIO182"), \
391 PINCTRL_PIN(183, "PLGPIO183"), \
392 PINCTRL_PIN(184, "PLGPIO184"), \
393 PINCTRL_PIN(185, "PLGPIO185"), \
394 PINCTRL_PIN(186, "PLGPIO186"), \
395 PINCTRL_PIN(187, "PLGPIO187"), \
396 PINCTRL_PIN(188, "PLGPIO188"), \
397 PINCTRL_PIN(189, "PLGPIO189"), \
398 PINCTRL_PIN(190, "PLGPIO190"), \
399 PINCTRL_PIN(191, "PLGPIO191"), \
400 PINCTRL_PIN(192, "PLGPIO192"), \
401 PINCTRL_PIN(193, "PLGPIO193"), \
402 PINCTRL_PIN(194, "PLGPIO194"), \
403 PINCTRL_PIN(195, "PLGPIO195"), \
404 PINCTRL_PIN(196, "PLGPIO196"), \
405 PINCTRL_PIN(197, "PLGPIO197"), \
406 PINCTRL_PIN(198, "PLGPIO198"), \
407 PINCTRL_PIN(199, "PLGPIO199"), \
408 PINCTRL_PIN(200, "PLGPIO200"), \
409 PINCTRL_PIN(201, "PLGPIO201"), \
410 PINCTRL_PIN(202, "PLGPIO202"), \
411 PINCTRL_PIN(203, "PLGPIO203"), \
412 PINCTRL_PIN(204, "PLGPIO204"), \
413 PINCTRL_PIN(205, "PLGPIO205"), \
414 PINCTRL_PIN(206, "PLGPIO206"), \
415 PINCTRL_PIN(207, "PLGPIO207"), \
416 PINCTRL_PIN(208, "PLGPIO208"), \
417 PINCTRL_PIN(209, "PLGPIO209"), \
418 PINCTRL_PIN(210, "PLGPIO210"), \
419 PINCTRL_PIN(211, "PLGPIO211"), \
420 PINCTRL_PIN(212, "PLGPIO212"), \
421 PINCTRL_PIN(213, "PLGPIO213"), \
422 PINCTRL_PIN(214, "PLGPIO214"), \
423 PINCTRL_PIN(215, "PLGPIO215"), \
424 PINCTRL_PIN(216, "PLGPIO216"), \
425 PINCTRL_PIN(217, "PLGPIO217"), \
426 PINCTRL_PIN(218, "PLGPIO218"), \
427 PINCTRL_PIN(219, "PLGPIO219"), \
428 PINCTRL_PIN(220, "PLGPIO220"), \
429 PINCTRL_PIN(221, "PLGPIO221"), \
430 PINCTRL_PIN(222, "PLGPIO222"), \
431 PINCTRL_PIN(223, "PLGPIO223"), \
432 PINCTRL_PIN(224, "PLGPIO224"), \
433 PINCTRL_PIN(225, "PLGPIO225"), \
434 PINCTRL_PIN(226, "PLGPIO226"), \
435 PINCTRL_PIN(227, "PLGPIO227"), \
436 PINCTRL_PIN(228, "PLGPIO228"), \
437 PINCTRL_PIN(229, "PLGPIO229"), \
438 PINCTRL_PIN(230, "PLGPIO230"), \
439 PINCTRL_PIN(231, "PLGPIO231"), \
440 PINCTRL_PIN(232, "PLGPIO232"), \
441 PINCTRL_PIN(233, "PLGPIO233"), \
442 PINCTRL_PIN(234, "PLGPIO234"), \
443 PINCTRL_PIN(235, "PLGPIO235"), \
444 PINCTRL_PIN(236, "PLGPIO236"), \
445 PINCTRL_PIN(237, "PLGPIO237"), \
446 PINCTRL_PIN(238, "PLGPIO238"), \
447 PINCTRL_PIN(239, "PLGPIO239"), \
448 PINCTRL_PIN(240, "PLGPIO240"), \
449 PINCTRL_PIN(241, "PLGPIO241"), \
450 PINCTRL_PIN(242, "PLGPIO242"), \
451 PINCTRL_PIN(243, "PLGPIO243"), \
452 PINCTRL_PIN(244, "PLGPIO244"), \
453 PINCTRL_PIN(245, "PLGPIO245")
454
455 #endif /* __PINMUX_SPEAR_H__ */
456