1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Support for Intel Camera Imaging ISP subsystem.
4 * Copyright (c) 2015, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16 #include "debug.h"
17
18 #ifndef __INLINE_INPUT_SYSTEM__
19 #define __INLINE_INPUT_SYSTEM__
20 #endif
21 #ifndef __INLINE_IBUF_CTRL__
22 #define __INLINE_IBUF_CTRL__
23 #endif
24 #ifndef __INLINE_CSI_RX__
25 #define __INLINE_CSI_RX__
26 #endif
27 #ifndef __INLINE_PIXELGEN__
28 #define __INLINE_PIXELGEN__
29 #endif
30 #ifndef __INLINE_STREAM2MMIO__
31 #define __INLINE_STREAM2MMIO__
32 #endif
33
34 #include <linux/string.h> /* for strscpy() */
35
36 #include "ia_css_debug.h"
37 #include "ia_css_debug_pipe.h"
38 #include "ia_css_irq.h"
39 #include "ia_css_stream.h"
40 #include "ia_css_pipeline.h"
41 #include "ia_css_isp_param.h"
42 #include "sh_css_params.h"
43 #include "ia_css_bufq.h"
44 /* ISP2401 */
45 #include "ia_css_queue.h"
46
47 #include "ia_css_isp_params.h"
48
49 #include "system_local.h"
50 #include "assert_support.h"
51 #include "print_support.h"
52
53 #include "fifo_monitor.h"
54
55 #include "input_formatter.h"
56 #include "dma.h"
57 #include "irq.h"
58 #include "gp_device.h"
59 #include "sp.h"
60 #include "isp.h"
61 #include "type_support.h"
62 #include "math_support.h" /* CEIL_DIV */
63 #include "input_system.h" /* input_formatter_reg_load */
64 #include "ia_css_tagger_common.h"
65
66 #include "sh_css_internal.h"
67 #include "ia_css_isys.h"
68 #include "sh_css_sp.h" /* sh_css_sp_get_debug_state() */
69
70 #include "css_trace.h" /* tracer */
71
72 #include "device_access.h" /* for ia_css_device_load_uint32 */
73
74 /* Include all kernel host interfaces for ISP1 */
75 #include "anr/anr_1.0/ia_css_anr.host.h"
76 #include "cnr/cnr_1.0/ia_css_cnr.host.h"
77 #include "csc/csc_1.0/ia_css_csc.host.h"
78 #include "de/de_1.0/ia_css_de.host.h"
79 #include "dp/dp_1.0/ia_css_dp.host.h"
80 #include "bnr/bnr_1.0/ia_css_bnr.host.h"
81 #include "fpn/fpn_1.0/ia_css_fpn.host.h"
82 #include "gc/gc_1.0/ia_css_gc.host.h"
83 #include "ob/ob_1.0/ia_css_ob.host.h"
84 #include "s3a/s3a_1.0/ia_css_s3a.host.h"
85 #include "sc/sc_1.0/ia_css_sc.host.h"
86 #include "tnr/tnr_1.0/ia_css_tnr.host.h"
87 #include "uds/uds_1.0/ia_css_uds_param.h"
88 #include "wb/wb_1.0/ia_css_wb.host.h"
89 #include "ynr/ynr_1.0/ia_css_ynr.host.h"
90
91 /* Include additional kernel host interfaces for ISP2 */
92 #include "aa/aa_2/ia_css_aa2.host.h"
93 #include "anr/anr_2/ia_css_anr2.host.h"
94 #include "cnr/cnr_2/ia_css_cnr2.host.h"
95 #include "de/de_2/ia_css_de2.host.h"
96 #include "gc/gc_2/ia_css_gc2.host.h"
97 #include "ynr/ynr_2/ia_css_ynr2.host.h"
98
99 #define DPG_START "ia_css_debug_pipe_graph_dump_start "
100 #define DPG_END " ia_css_debug_pipe_graph_dump_end\n"
101
102 #define ENABLE_LINE_MAX_LENGTH (25)
103
104 /*
105 * TODO:SH_CSS_MAX_SP_THREADS is not the max number of sp threads
106 * future rework should fix this and remove the define MAX_THREAD_NUM
107 */
108 #define MAX_THREAD_NUM (SH_CSS_MAX_SP_THREADS + SH_CSS_MAX_SP_INTERNAL_THREADS)
109
110 static struct pipe_graph_class {
111 bool do_init;
112 int height;
113 int width;
114 int eff_height;
115 int eff_width;
116 enum atomisp_input_format stream_format;
117 } pg_inst = {true, 0, 0, 0, 0, N_ATOMISP_INPUT_FORMAT};
118
119 static const char *const queue_id_to_str[] = {
120 /* [SH_CSS_QUEUE_A_ID] =*/ "queue_A",
121 /* [SH_CSS_QUEUE_B_ID] =*/ "queue_B",
122 /* [SH_CSS_QUEUE_C_ID] =*/ "queue_C",
123 /* [SH_CSS_QUEUE_D_ID] =*/ "queue_D",
124 /* [SH_CSS_QUEUE_E_ID] =*/ "queue_E",
125 /* [SH_CSS_QUEUE_F_ID] =*/ "queue_F",
126 /* [SH_CSS_QUEUE_G_ID] =*/ "queue_G",
127 /* [SH_CSS_QUEUE_H_ID] =*/ "queue_H"
128 };
129
130 static const char *const pipe_id_to_str[] = {
131 /* [IA_CSS_PIPE_ID_PREVIEW] =*/ "preview",
132 /* [IA_CSS_PIPE_ID_COPY] =*/ "copy",
133 /* [IA_CSS_PIPE_ID_VIDEO] =*/ "video",
134 /* [IA_CSS_PIPE_ID_CAPTURE] =*/ "capture",
135 /* [IA_CSS_PIPE_ID_YUVPP] =*/ "yuvpp",
136 };
137
138 static char dot_id_input_bin[SH_CSS_MAX_BINARY_NAME + 10];
139 static char ring_buffer[200];
140
ia_css_debug_dtrace(unsigned int level,const char * fmt,...)141 void ia_css_debug_dtrace(unsigned int level, const char *fmt, ...)
142 {
143 va_list ap;
144
145 va_start(ap, fmt);
146 ia_css_debug_vdtrace(level, fmt, ap);
147 va_end(ap);
148 }
149
debug_dump_long_array_formatted(const sp_ID_t sp_id,hrt_address stack_sp_addr,unsigned int stack_size)150 static void debug_dump_long_array_formatted(
151 const sp_ID_t sp_id,
152 hrt_address stack_sp_addr,
153 unsigned int stack_size)
154 {
155 unsigned int i;
156 u32 val;
157 u32 addr = (uint32_t)stack_sp_addr;
158 u32 stack_size_words = CEIL_DIV(stack_size, sizeof(uint32_t));
159
160 /* When size is not multiple of four, last word is only relevant for
161 * remaining bytes */
162 for (i = 0; i < stack_size_words; i++) {
163 val = sp_dmem_load_uint32(sp_id, (hrt_address)addr);
164 if ((i % 8) == 0)
165 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\n");
166
167 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "0x%08x ", val);
168 addr += sizeof(uint32_t);
169 }
170
171 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\n");
172 }
173
debug_dump_sp_stack_info(const sp_ID_t sp_id)174 static void debug_dump_sp_stack_info(
175 const sp_ID_t sp_id)
176 {
177 const struct ia_css_fw_info *fw;
178 unsigned int HIVE_ADDR_sp_threads_stack;
179 unsigned int HIVE_ADDR_sp_threads_stack_size;
180 u32 stack_sizes[MAX_THREAD_NUM];
181 u32 stack_sp_addr[MAX_THREAD_NUM];
182 unsigned int i;
183
184 fw = &sh_css_sp_fw;
185
186 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "sp_id(%u) stack info\n", sp_id);
187 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
188 "from objects stack_addr_offset:0x%x stack_size_offset:0x%x\n",
189 fw->info.sp.threads_stack,
190 fw->info.sp.threads_stack_size);
191
192 HIVE_ADDR_sp_threads_stack = fw->info.sp.threads_stack;
193 HIVE_ADDR_sp_threads_stack_size = fw->info.sp.threads_stack_size;
194
195 if (fw->info.sp.threads_stack == 0 ||
196 fw->info.sp.threads_stack_size == 0)
197 return;
198
199 (void)HIVE_ADDR_sp_threads_stack;
200 (void)HIVE_ADDR_sp_threads_stack_size;
201
202 sp_dmem_load(sp_id,
203 (unsigned int)sp_address_of(sp_threads_stack),
204 &stack_sp_addr, sizeof(stack_sp_addr));
205 sp_dmem_load(sp_id,
206 (unsigned int)sp_address_of(sp_threads_stack_size),
207 &stack_sizes, sizeof(stack_sizes));
208
209 for (i = 0 ; i < MAX_THREAD_NUM; i++) {
210 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
211 "thread: %u stack_addr: 0x%08x stack_size: %u\n",
212 i, stack_sp_addr[i], stack_sizes[i]);
213 debug_dump_long_array_formatted(sp_id, (hrt_address)stack_sp_addr[i],
214 stack_sizes[i]);
215 }
216 }
217
ia_css_debug_dump_sp_stack_info(void)218 void ia_css_debug_dump_sp_stack_info(void)
219 {
220 debug_dump_sp_stack_info(SP0_ID);
221 }
222
ia_css_debug_set_dtrace_level(const unsigned int trace_level)223 void ia_css_debug_set_dtrace_level(const unsigned int trace_level)
224 {
225 dbg_level = trace_level;
226 return;
227 }
228
ia_css_debug_get_dtrace_level(void)229 unsigned int ia_css_debug_get_dtrace_level(void)
230 {
231 return dbg_level;
232 }
233
debug_stream_format2str(const enum atomisp_input_format stream_format)234 static const char *debug_stream_format2str(const enum atomisp_input_format
235 stream_format)
236 {
237 switch (stream_format) {
238 case ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY:
239 return "yuv420-8-legacy";
240 case ATOMISP_INPUT_FORMAT_YUV420_8:
241 return "yuv420-8";
242 case ATOMISP_INPUT_FORMAT_YUV420_10:
243 return "yuv420-10";
244 case ATOMISP_INPUT_FORMAT_YUV420_16:
245 return "yuv420-16";
246 case ATOMISP_INPUT_FORMAT_YUV422_8:
247 return "yuv422-8";
248 case ATOMISP_INPUT_FORMAT_YUV422_10:
249 return "yuv422-10";
250 case ATOMISP_INPUT_FORMAT_YUV422_16:
251 return "yuv422-16";
252 case ATOMISP_INPUT_FORMAT_RGB_444:
253 return "rgb444";
254 case ATOMISP_INPUT_FORMAT_RGB_555:
255 return "rgb555";
256 case ATOMISP_INPUT_FORMAT_RGB_565:
257 return "rgb565";
258 case ATOMISP_INPUT_FORMAT_RGB_666:
259 return "rgb666";
260 case ATOMISP_INPUT_FORMAT_RGB_888:
261 return "rgb888";
262 case ATOMISP_INPUT_FORMAT_RAW_6:
263 return "raw6";
264 case ATOMISP_INPUT_FORMAT_RAW_7:
265 return "raw7";
266 case ATOMISP_INPUT_FORMAT_RAW_8:
267 return "raw8";
268 case ATOMISP_INPUT_FORMAT_RAW_10:
269 return "raw10";
270 case ATOMISP_INPUT_FORMAT_RAW_12:
271 return "raw12";
272 case ATOMISP_INPUT_FORMAT_RAW_14:
273 return "raw14";
274 case ATOMISP_INPUT_FORMAT_RAW_16:
275 return "raw16";
276 case ATOMISP_INPUT_FORMAT_BINARY_8:
277 return "binary8";
278 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT1:
279 return "generic-short1";
280 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT2:
281 return "generic-short2";
282 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT3:
283 return "generic-short3";
284 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT4:
285 return "generic-short4";
286 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT5:
287 return "generic-short5";
288 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT6:
289 return "generic-short6";
290 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT7:
291 return "generic-short7";
292 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT8:
293 return "generic-short8";
294 case ATOMISP_INPUT_FORMAT_YUV420_8_SHIFT:
295 return "yuv420-8-shift";
296 case ATOMISP_INPUT_FORMAT_YUV420_10_SHIFT:
297 return "yuv420-10-shift";
298 case ATOMISP_INPUT_FORMAT_EMBEDDED:
299 return "embedded-8";
300 case ATOMISP_INPUT_FORMAT_USER_DEF1:
301 return "user-def-8-type-1";
302 case ATOMISP_INPUT_FORMAT_USER_DEF2:
303 return "user-def-8-type-2";
304 case ATOMISP_INPUT_FORMAT_USER_DEF3:
305 return "user-def-8-type-3";
306 case ATOMISP_INPUT_FORMAT_USER_DEF4:
307 return "user-def-8-type-4";
308 case ATOMISP_INPUT_FORMAT_USER_DEF5:
309 return "user-def-8-type-5";
310 case ATOMISP_INPUT_FORMAT_USER_DEF6:
311 return "user-def-8-type-6";
312 case ATOMISP_INPUT_FORMAT_USER_DEF7:
313 return "user-def-8-type-7";
314 case ATOMISP_INPUT_FORMAT_USER_DEF8:
315 return "user-def-8-type-8";
316
317 default:
318 assert(!"Unknown stream format");
319 return "unknown-stream-format";
320 }
321 };
322
debug_frame_format2str(const enum ia_css_frame_format frame_format)323 static const char *debug_frame_format2str(const enum ia_css_frame_format
324 frame_format)
325 {
326 switch (frame_format) {
327 case IA_CSS_FRAME_FORMAT_NV11:
328 return "NV11";
329 case IA_CSS_FRAME_FORMAT_NV12:
330 return "NV12";
331 case IA_CSS_FRAME_FORMAT_NV12_16:
332 return "NV12_16";
333 case IA_CSS_FRAME_FORMAT_NV12_TILEY:
334 return "NV12_TILEY";
335 case IA_CSS_FRAME_FORMAT_NV16:
336 return "NV16";
337 case IA_CSS_FRAME_FORMAT_NV21:
338 return "NV21";
339 case IA_CSS_FRAME_FORMAT_NV61:
340 return "NV61";
341 case IA_CSS_FRAME_FORMAT_YV12:
342 return "YV12";
343 case IA_CSS_FRAME_FORMAT_YV16:
344 return "YV16";
345 case IA_CSS_FRAME_FORMAT_YUV420:
346 return "YUV420";
347 case IA_CSS_FRAME_FORMAT_YUV420_16:
348 return "YUV420_16";
349 case IA_CSS_FRAME_FORMAT_YUV422:
350 return "YUV422";
351 case IA_CSS_FRAME_FORMAT_YUV422_16:
352 return "YUV422_16";
353 case IA_CSS_FRAME_FORMAT_UYVY:
354 return "UYVY";
355 case IA_CSS_FRAME_FORMAT_YUYV:
356 return "YUYV";
357 case IA_CSS_FRAME_FORMAT_YUV444:
358 return "YUV444";
359 case IA_CSS_FRAME_FORMAT_YUV_LINE:
360 return "YUV_LINE";
361 case IA_CSS_FRAME_FORMAT_RAW:
362 return "RAW";
363 case IA_CSS_FRAME_FORMAT_RGB565:
364 return "RGB565";
365 case IA_CSS_FRAME_FORMAT_PLANAR_RGB888:
366 return "PLANAR_RGB888";
367 case IA_CSS_FRAME_FORMAT_RGBA888:
368 return "RGBA888";
369 case IA_CSS_FRAME_FORMAT_QPLANE6:
370 return "QPLANE6";
371 case IA_CSS_FRAME_FORMAT_BINARY_8:
372 return "BINARY_8";
373 case IA_CSS_FRAME_FORMAT_MIPI:
374 return "MIPI";
375 case IA_CSS_FRAME_FORMAT_RAW_PACKED:
376 return "RAW_PACKED";
377 case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8:
378 return "CSI_MIPI_YUV420_8";
379 case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8:
380 return "CSI_MIPI_LEGACY_YUV420_8";
381 case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_10:
382 return "CSI_MIPI_YUV420_10";
383
384 default:
385 assert(!"Unknown frame format");
386 return "unknown-frame-format";
387 }
388 }
389
debug_print_sp_state(const sp_state_t * state,const char * cell)390 static void debug_print_sp_state(const sp_state_t *state, const char *cell)
391 {
392 assert(cell);
393 assert(state);
394
395 ia_css_debug_dtrace(2, "%s state:\n", cell);
396 ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "PC", state->pc);
397 ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "Status register",
398 state->status_register);
399 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is broken", state->is_broken);
400 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is idle", state->is_idle);
401 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is sleeping",
402 state->is_sleeping);
403 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is stalling",
404 state->is_stalling);
405 return;
406 }
407
debug_print_isp_state(const isp_state_t * state,const char * cell)408 static void debug_print_isp_state(const isp_state_t *state, const char *cell)
409 {
410 assert(state);
411 assert(cell);
412
413 ia_css_debug_dtrace(2, "%s state:\n", cell);
414 ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "PC", state->pc);
415 ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "Status register",
416 state->status_register);
417 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is broken", state->is_broken);
418 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is idle", state->is_idle);
419 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is sleeping",
420 state->is_sleeping);
421 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is stalling",
422 state->is_stalling);
423 return;
424 }
425
ia_css_debug_dump_isp_state(void)426 void ia_css_debug_dump_isp_state(void)
427 {
428 isp_state_t state;
429 isp_stall_t stall;
430
431 isp_get_state(ISP0_ID, &state, &stall);
432
433 debug_print_isp_state(&state, "ISP");
434
435 if (state.is_stalling) {
436 if (!IS_ISP2401) {
437 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
438 "[0] if_prim_a_FIFO stalled", stall.fifo0);
439 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
440 "[1] if_prim_b_FIFO stalled", stall.fifo1);
441 }
442 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[2] dma_FIFO stalled",
443 stall.fifo2);
444
445 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[3] gdc0_FIFO stalled",
446 stall.fifo3);
447 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[4] gdc1_FIFO stalled",
448 stall.fifo4);
449 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[5] gpio_FIFO stalled",
450 stall.fifo5);
451 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[6] sp_FIFO stalled",
452 stall.fifo6);
453 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
454 "status & control stalled",
455 stall.stat_ctrl);
456 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dmem stalled",
457 stall.dmem);
458 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vmem stalled",
459 stall.vmem);
460 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem1 stalled",
461 stall.vamem1);
462 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem2 stalled",
463 stall.vamem2);
464 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem3 stalled",
465 stall.vamem3);
466 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "hmem stalled",
467 stall.hmem);
468 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "pmem stalled",
469 stall.pmem);
470 }
471 return;
472 }
473
ia_css_debug_dump_sp_state(void)474 void ia_css_debug_dump_sp_state(void)
475 {
476 sp_state_t state;
477 sp_stall_t stall;
478
479 sp_get_state(SP0_ID, &state, &stall);
480 debug_print_sp_state(&state, "SP");
481 if (state.is_stalling) {
482 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "isys_FIFO stalled",
483 stall.fifo0);
484 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "if_sec_FIFO stalled",
485 stall.fifo1);
486 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
487 "str_to_mem_FIFO stalled", stall.fifo2);
488 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dma_FIFO stalled",
489 stall.fifo3);
490 if (!IS_ISP2401)
491 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
492 "if_prim_a_FIFO stalled", stall.fifo4);
493
494 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "isp_FIFO stalled",
495 stall.fifo5);
496 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gp_FIFO stalled",
497 stall.fifo6);
498 if (!IS_ISP2401)
499 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
500 "if_prim_b_FIFO stalled", stall.fifo7);
501 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gdc0_FIFO stalled",
502 stall.fifo8);
503 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gdc1_FIFO stalled",
504 stall.fifo9);
505 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "irq FIFO stalled",
506 stall.fifoa);
507 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dmem stalled",
508 stall.dmem);
509 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
510 "control master stalled",
511 stall.control_master);
512 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
513 "i-cache master stalled",
514 stall.icache_master);
515 }
516 ia_css_debug_dump_trace();
517 return;
518 }
519
debug_print_fifo_channel_state(const fifo_channel_state_t * state,const char * descr)520 static void debug_print_fifo_channel_state(const fifo_channel_state_t *state,
521 const char *descr)
522 {
523 assert(state);
524 assert(descr);
525
526 ia_css_debug_dtrace(2, "FIFO channel: %s\n", descr);
527 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "source valid",
528 state->src_valid);
529 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "fifo accept",
530 state->fifo_accept);
531 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "fifo valid",
532 state->fifo_valid);
533 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "sink accept",
534 state->sink_accept);
535 return;
536 }
537
ia_css_debug_dump_pif_a_isp_fifo_state(void)538 void ia_css_debug_dump_pif_a_isp_fifo_state(void)
539 {
540 fifo_channel_state_t pif_to_isp, isp_to_pif;
541
542 fifo_channel_get_state(FIFO_MONITOR0_ID,
543 FIFO_CHANNEL_IF0_TO_ISP0, &pif_to_isp);
544 fifo_channel_get_state(FIFO_MONITOR0_ID,
545 FIFO_CHANNEL_ISP0_TO_IF0, &isp_to_pif);
546 debug_print_fifo_channel_state(&pif_to_isp, "Primary IF A to ISP");
547 debug_print_fifo_channel_state(&isp_to_pif, "ISP to Primary IF A");
548 }
549
ia_css_debug_dump_pif_b_isp_fifo_state(void)550 void ia_css_debug_dump_pif_b_isp_fifo_state(void)
551 {
552 fifo_channel_state_t pif_to_isp, isp_to_pif;
553
554 fifo_channel_get_state(FIFO_MONITOR0_ID,
555 FIFO_CHANNEL_IF1_TO_ISP0, &pif_to_isp);
556 fifo_channel_get_state(FIFO_MONITOR0_ID,
557 FIFO_CHANNEL_ISP0_TO_IF1, &isp_to_pif);
558 debug_print_fifo_channel_state(&pif_to_isp, "Primary IF B to ISP");
559 debug_print_fifo_channel_state(&isp_to_pif, "ISP to Primary IF B");
560 }
561
ia_css_debug_dump_str2mem_sp_fifo_state(void)562 void ia_css_debug_dump_str2mem_sp_fifo_state(void)
563 {
564 fifo_channel_state_t s2m_to_sp, sp_to_s2m;
565
566 fifo_channel_get_state(FIFO_MONITOR0_ID,
567 FIFO_CHANNEL_STREAM2MEM0_TO_SP0, &s2m_to_sp);
568 fifo_channel_get_state(FIFO_MONITOR0_ID,
569 FIFO_CHANNEL_SP0_TO_STREAM2MEM0, &sp_to_s2m);
570 debug_print_fifo_channel_state(&s2m_to_sp, "Stream-to-memory to SP");
571 debug_print_fifo_channel_state(&sp_to_s2m, "SP to stream-to-memory");
572 }
573
574 #ifndef ISP2401
debug_print_if_state(input_formatter_state_t * state,const char * id)575 static void debug_print_if_state(input_formatter_state_t *state, const char *id)
576 {
577 unsigned int val;
578
579 const char *st_vsync_active_low =
580 (state->vsync_active_low ? "low" : "high");
581 const char *st_hsync_active_low =
582 (state->hsync_active_low ? "low" : "high");
583
584 const char *fsm_sync_status_str = "unknown";
585 const char *fsm_crop_status_str = "unknown";
586 const char *fsm_padding_status_str = "unknown";
587
588 int st_stline = state->start_line;
589 int st_stcol = state->start_column;
590 int st_crpht = state->cropped_height;
591 int st_crpwd = state->cropped_width;
592 int st_verdcm = state->ver_decimation;
593 int st_hordcm = state->hor_decimation;
594 int st_ver_deinterleaving = state->ver_deinterleaving;
595 int st_hor_deinterleaving = state->hor_deinterleaving;
596 int st_leftpd = state->left_padding;
597 int st_eoloff = state->eol_offset;
598 int st_vmstartaddr = state->vmem_start_address;
599 int st_vmendaddr = state->vmem_end_address;
600 int st_vmincr = state->vmem_increment;
601 int st_yuv420 = state->is_yuv420;
602 int st_allow_fifo_overflow = state->allow_fifo_overflow;
603 int st_block_fifo_when_no_req = state->block_fifo_when_no_req;
604
605 assert(state);
606 ia_css_debug_dtrace(2, "InputFormatter State (%s):\n", id);
607
608 ia_css_debug_dtrace(2, "\tConfiguration:\n");
609
610 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Start line", st_stline);
611 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Start column", st_stcol);
612 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropped height", st_crpht);
613 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropped width", st_crpwd);
614 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Ver decimation", st_verdcm);
615 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Hor decimation", st_hordcm);
616 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
617 "Ver deinterleaving", st_ver_deinterleaving);
618 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
619 "Hor deinterleaving", st_hor_deinterleaving);
620 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Left padding", st_leftpd);
621 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
622 "EOL offset (bytes)", st_eoloff);
623 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n",
624 "VMEM start address", st_vmstartaddr);
625 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n",
626 "VMEM end address", st_vmendaddr);
627 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n",
628 "VMEM increment", st_vmincr);
629 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "YUV 420 format", st_yuv420);
630 ia_css_debug_dtrace(2, "\t\t%-32s: Active %s\n",
631 "Vsync", st_vsync_active_low);
632 ia_css_debug_dtrace(2, "\t\t%-32s: Active %s\n",
633 "Hsync", st_hsync_active_low);
634 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
635 "Allow FIFO overflow", st_allow_fifo_overflow);
636 /* Flag that tells whether the IF gives backpressure on frames */
637 /*
638 * FYI, this is only on the frame request (indicate), when the IF has
639 * synch'd on a frame it will always give back pressure
640 */
641 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
642 "Block when no request", st_block_fifo_when_no_req);
643
644 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
645 "IF_BLOCKED_FIFO_NO_REQ_ADDRESS",
646 input_formatter_reg_load(INPUT_FORMATTER0_ID,
647 HIVE_IF_BLOCK_FIFO_NO_REQ_ADDRESS)
648 );
649
650 ia_css_debug_dtrace(2, "\t%-32s:\n", "InputSwitch State");
651
652 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
653 "_REG_GP_IFMT_input_switch_lut_reg0",
654 gp_device_reg_load(GP_DEVICE0_ID,
655 _REG_GP_IFMT_input_switch_lut_reg0));
656
657 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
658 "_REG_GP_IFMT_input_switch_lut_reg1",
659 gp_device_reg_load(GP_DEVICE0_ID,
660 _REG_GP_IFMT_input_switch_lut_reg1));
661
662 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
663 "_REG_GP_IFMT_input_switch_lut_reg2",
664 gp_device_reg_load(GP_DEVICE0_ID,
665 _REG_GP_IFMT_input_switch_lut_reg2));
666
667 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
668 "_REG_GP_IFMT_input_switch_lut_reg3",
669 gp_device_reg_load(GP_DEVICE0_ID,
670 _REG_GP_IFMT_input_switch_lut_reg3));
671
672 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
673 "_REG_GP_IFMT_input_switch_lut_reg4",
674 gp_device_reg_load(GP_DEVICE0_ID,
675 _REG_GP_IFMT_input_switch_lut_reg4));
676
677 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
678 "_REG_GP_IFMT_input_switch_lut_reg5",
679 gp_device_reg_load(GP_DEVICE0_ID,
680 _REG_GP_IFMT_input_switch_lut_reg5));
681
682 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
683 "_REG_GP_IFMT_input_switch_lut_reg6",
684 gp_device_reg_load(GP_DEVICE0_ID,
685 _REG_GP_IFMT_input_switch_lut_reg6));
686
687 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
688 "_REG_GP_IFMT_input_switch_lut_reg7",
689 gp_device_reg_load(GP_DEVICE0_ID,
690 _REG_GP_IFMT_input_switch_lut_reg7));
691
692 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
693 "_REG_GP_IFMT_input_switch_fsync_lut",
694 gp_device_reg_load(GP_DEVICE0_ID,
695 _REG_GP_IFMT_input_switch_fsync_lut));
696
697 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
698 "_REG_GP_IFMT_srst",
699 gp_device_reg_load(GP_DEVICE0_ID,
700 _REG_GP_IFMT_srst));
701
702 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
703 "_REG_GP_IFMT_slv_reg_srst",
704 gp_device_reg_load(GP_DEVICE0_ID,
705 _REG_GP_IFMT_slv_reg_srst));
706
707 ia_css_debug_dtrace(2, "\tFSM Status:\n");
708
709 val = state->fsm_sync_status;
710
711 if (val > 7)
712 fsm_sync_status_str = "ERROR";
713
714 switch (val & 0x7) {
715 case 0:
716 fsm_sync_status_str = "idle";
717 break;
718 case 1:
719 fsm_sync_status_str = "request frame";
720 break;
721 case 2:
722 fsm_sync_status_str = "request lines";
723 break;
724 case 3:
725 fsm_sync_status_str = "request vectors";
726 break;
727 case 4:
728 fsm_sync_status_str = "send acknowledge";
729 break;
730 default:
731 fsm_sync_status_str = "unknown";
732 break;
733 }
734
735 ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n",
736 "FSM Synchronization Status", val,
737 fsm_sync_status_str);
738
739 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
740 "FSM Synchronization Counter",
741 state->fsm_sync_counter);
742
743 val = state->fsm_crop_status;
744
745 if (val > 7)
746 fsm_crop_status_str = "ERROR";
747
748 switch (val & 0x7) {
749 case 0:
750 fsm_crop_status_str = "idle";
751 break;
752 case 1:
753 fsm_crop_status_str = "wait line";
754 break;
755 case 2:
756 fsm_crop_status_str = "crop line";
757 break;
758 case 3:
759 fsm_crop_status_str = "crop pixel";
760 break;
761 case 4:
762 fsm_crop_status_str = "pass pixel";
763 break;
764 case 5:
765 fsm_crop_status_str = "pass line";
766 break;
767 case 6:
768 fsm_crop_status_str = "lost line";
769 break;
770 default:
771 fsm_crop_status_str = "unknown";
772 break;
773 }
774 ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n",
775 "FSM Crop Status", val, fsm_crop_status_str);
776
777 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
778 "FSM Crop Line Counter",
779 state->fsm_crop_line_counter);
780 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
781 "FSM Crop Pixel Counter",
782 state->fsm_crop_pixel_counter);
783 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
784 "FSM Deinterleaving idx buffer",
785 state->fsm_deinterleaving_index);
786 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
787 "FSM H decimation counter",
788 state->fsm_dec_h_counter);
789 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
790 "FSM V decimation counter",
791 state->fsm_dec_v_counter);
792 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
793 "FSM block V decimation counter",
794 state->fsm_dec_block_v_counter);
795
796 val = state->fsm_padding_status;
797
798 if (val > 7)
799 fsm_padding_status_str = "ERROR";
800
801 switch (val & 0x7) {
802 case 0:
803 fsm_padding_status_str = "idle";
804 break;
805 case 1:
806 fsm_padding_status_str = "left pad";
807 break;
808 case 2:
809 fsm_padding_status_str = "write";
810 break;
811 case 3:
812 fsm_padding_status_str = "right pad";
813 break;
814 case 4:
815 fsm_padding_status_str = "send end of line";
816 break;
817 default:
818 fsm_padding_status_str = "unknown";
819 break;
820 }
821
822 ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n", "FSM Padding Status",
823 val, fsm_padding_status_str);
824
825 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
826 "FSM Padding element idx counter",
827 state->fsm_padding_elem_counter);
828 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support error",
829 state->fsm_vector_support_error);
830 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support buf full",
831 state->fsm_vector_buffer_full);
832 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support",
833 state->vector_support);
834 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Fifo sensor data lost",
835 state->sensor_data_lost);
836 }
837
debug_print_if_bin_state(input_formatter_bin_state_t * state)838 static void debug_print_if_bin_state(input_formatter_bin_state_t *state)
839 {
840 ia_css_debug_dtrace(2, "Stream-to-memory state:\n");
841 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "reset", state->reset);
842 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "input endianness",
843 state->input_endianness);
844 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "output endianness",
845 state->output_endianness);
846 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "bitswap", state->bitswap);
847 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "block_synch",
848 state->block_synch);
849 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "packet_synch",
850 state->packet_synch);
851 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "readpostwrite_sync",
852 state->readpostwrite_synch);
853 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "is_2ppc", state->is_2ppc);
854 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "en_status_update",
855 state->en_status_update);
856 }
857
ia_css_debug_dump_if_state(void)858 static void ia_css_debug_dump_if_state(void)
859 {
860 input_formatter_state_t if_state;
861 input_formatter_bin_state_t if_bin_state;
862
863 input_formatter_get_state(INPUT_FORMATTER0_ID, &if_state);
864 debug_print_if_state(&if_state, "Primary IF A");
865 ia_css_debug_dump_pif_a_isp_fifo_state();
866
867 input_formatter_get_state(INPUT_FORMATTER1_ID, &if_state);
868 debug_print_if_state(&if_state, "Primary IF B");
869 ia_css_debug_dump_pif_b_isp_fifo_state();
870
871 input_formatter_bin_get_state(INPUT_FORMATTER3_ID, &if_bin_state);
872 debug_print_if_bin_state(&if_bin_state);
873 ia_css_debug_dump_str2mem_sp_fifo_state();
874 }
875 #endif
876
ia_css_debug_dump_dma_state(void)877 void ia_css_debug_dump_dma_state(void)
878 {
879 /* note: the var below is made static as it is quite large;
880 if it is not static it ends up on the stack which could
881 cause issues for drivers
882 */
883 static dma_state_t state;
884 int i, ch_id;
885
886 const char *fsm_cmd_st_lbl = "FSM Command flag state";
887 const char *fsm_ctl_st_lbl = "FSM Control flag state";
888 const char *fsm_ctl_state = NULL;
889 const char *fsm_ctl_flag = NULL;
890 const char *fsm_pack_st = NULL;
891 const char *fsm_read_st = NULL;
892 const char *fsm_write_st = NULL;
893 char last_cmd_str[64];
894
895 dma_get_state(DMA0_ID, &state);
896 /* Print header for DMA dump status */
897 ia_css_debug_dtrace(2, "DMA dump status:\n");
898
899 /* Print FSM command flag state */
900 if (state.fsm_command_idle)
901 ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, "IDLE");
902 if (state.fsm_command_run)
903 ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, "RUN");
904 if (state.fsm_command_stalling)
905 ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl,
906 "STALL");
907 if (state.fsm_command_error)
908 ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl,
909 "ERROR");
910
911 /* Print last command along with the channel */
912 ch_id = state.last_command_channel;
913
914 switch (state.last_command) {
915 case DMA_COMMAND_READ:
916 snprintf(last_cmd_str, 64,
917 "Read 2D Block [Channel: %d]", ch_id);
918 break;
919 case DMA_COMMAND_WRITE:
920 snprintf(last_cmd_str, 64,
921 "Write 2D Block [Channel: %d]", ch_id);
922 break;
923 case DMA_COMMAND_SET_CHANNEL:
924 snprintf(last_cmd_str, 64, "Set Channel [Channel: %d]", ch_id);
925 break;
926 case DMA_COMMAND_SET_PARAM:
927 snprintf(last_cmd_str, 64,
928 "Set Param: %d [Channel: %d]",
929 state.last_command_param, ch_id);
930 break;
931 case DMA_COMMAND_READ_SPECIFIC:
932 snprintf(last_cmd_str, 64,
933 "Read Specific 2D Block [Channel: %d]", ch_id);
934 break;
935 case DMA_COMMAND_WRITE_SPECIFIC:
936 snprintf(last_cmd_str, 64,
937 "Write Specific 2D Block [Channel: %d]", ch_id);
938 break;
939 case DMA_COMMAND_INIT:
940 snprintf(last_cmd_str, 64,
941 "Init 2D Block on Device A [Channel: %d]", ch_id);
942 break;
943 case DMA_COMMAND_INIT_SPECIFIC:
944 snprintf(last_cmd_str, 64,
945 "Init Specific 2D Block [Channel: %d]", ch_id);
946 break;
947 case DMA_COMMAND_RST:
948 snprintf(last_cmd_str, 64, "DMA SW Reset");
949 break;
950 case N_DMA_COMMANDS:
951 snprintf(last_cmd_str, 64, "UNKNOWN");
952 break;
953 default:
954 snprintf(last_cmd_str, 64,
955 "unknown [Channel: %d]", ch_id);
956 break;
957 }
958 ia_css_debug_dtrace(2, "\t%-32s: (0x%X : %s)\n",
959 "last command received", state.last_command,
960 last_cmd_str);
961
962 /* Print DMA registers */
963 ia_css_debug_dtrace(2, "\t%-32s\n",
964 "DMA registers, connection group 0");
965 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Command",
966 state.current_command);
967 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Address A",
968 state.current_addr_a);
969 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Address B",
970 state.current_addr_b);
971
972 if (state.fsm_ctrl_idle)
973 fsm_ctl_flag = "IDLE";
974 else if (state.fsm_ctrl_run)
975 fsm_ctl_flag = "RUN";
976 else if (state.fsm_ctrl_stalling)
977 fsm_ctl_flag = "STAL";
978 else if (state.fsm_ctrl_error)
979 fsm_ctl_flag = "ERROR";
980 else
981 fsm_ctl_flag = "UNKNOWN";
982
983 switch (state.fsm_ctrl_state) {
984 case DMA_CTRL_STATE_IDLE:
985 fsm_ctl_state = "Idle state";
986 break;
987 case DMA_CTRL_STATE_REQ_RCV:
988 fsm_ctl_state = "Req Rcv state";
989 break;
990 case DMA_CTRL_STATE_RCV:
991 fsm_ctl_state = "Rcv state";
992 break;
993 case DMA_CTRL_STATE_RCV_REQ:
994 fsm_ctl_state = "Rcv Req state";
995 break;
996 case DMA_CTRL_STATE_INIT:
997 fsm_ctl_state = "Init state";
998 break;
999 case N_DMA_CTRL_STATES:
1000 fsm_ctl_state = "Unknown";
1001 break;
1002 }
1003
1004 ia_css_debug_dtrace(2, "\t\t%-32s: %s -> %s\n", fsm_ctl_st_lbl,
1005 fsm_ctl_flag, fsm_ctl_state);
1006
1007 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source dev",
1008 state.fsm_ctrl_source_dev);
1009 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl source addr",
1010 state.fsm_ctrl_source_addr);
1011 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl source stride",
1012 state.fsm_ctrl_source_stride);
1013 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source width",
1014 state.fsm_ctrl_source_width);
1015 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source height",
1016 state.fsm_ctrl_source_height);
1017 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source dev",
1018 state.fsm_ctrl_pack_source_dev);
1019 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest dev",
1020 state.fsm_ctrl_pack_dest_dev);
1021 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl dest addr",
1022 state.fsm_ctrl_dest_addr);
1023 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl dest stride",
1024 state.fsm_ctrl_dest_stride);
1025 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source width",
1026 state.fsm_ctrl_pack_source_width);
1027 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest height",
1028 state.fsm_ctrl_pack_dest_height);
1029 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest width",
1030 state.fsm_ctrl_pack_dest_width);
1031 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source elems",
1032 state.fsm_ctrl_pack_source_elems);
1033 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest elems",
1034 state.fsm_ctrl_pack_dest_elems);
1035 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack extension",
1036 state.fsm_ctrl_pack_extension);
1037
1038 if (state.pack_idle)
1039 fsm_pack_st = "IDLE";
1040 if (state.pack_run)
1041 fsm_pack_st = "RUN";
1042 if (state.pack_stalling)
1043 fsm_pack_st = "STALL";
1044 if (state.pack_error)
1045 fsm_pack_st = "ERROR";
1046
1047 ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Pack flag state",
1048 fsm_pack_st);
1049
1050 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack cnt height",
1051 state.pack_cnt_height);
1052 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack src cnt width",
1053 state.pack_src_cnt_width);
1054 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack dest cnt width",
1055 state.pack_dest_cnt_width);
1056
1057 if (state.read_state == DMA_RW_STATE_IDLE)
1058 fsm_read_st = "Idle state";
1059 if (state.read_state == DMA_RW_STATE_REQ)
1060 fsm_read_st = "Req state";
1061 if (state.read_state == DMA_RW_STATE_NEXT_LINE)
1062 fsm_read_st = "Next line";
1063 if (state.read_state == DMA_RW_STATE_UNLOCK_CHANNEL)
1064 fsm_read_st = "Unlock channel";
1065
1066 ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Read state",
1067 fsm_read_st);
1068
1069 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Read cnt height",
1070 state.read_cnt_height);
1071 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Read cnt width",
1072 state.read_cnt_width);
1073
1074 if (state.write_state == DMA_RW_STATE_IDLE)
1075 fsm_write_st = "Idle state";
1076 if (state.write_state == DMA_RW_STATE_REQ)
1077 fsm_write_st = "Req state";
1078 if (state.write_state == DMA_RW_STATE_NEXT_LINE)
1079 fsm_write_st = "Next line";
1080 if (state.write_state == DMA_RW_STATE_UNLOCK_CHANNEL)
1081 fsm_write_st = "Unlock channel";
1082
1083 ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Write state",
1084 fsm_write_st);
1085
1086 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Write height",
1087 state.write_height);
1088 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Write width",
1089 state.write_width);
1090
1091 for (i = 0; i < HIVE_ISP_NUM_DMA_CONNS; i++) {
1092 dma_port_state_t *port = &state.port_states[i];
1093
1094 ia_css_debug_dtrace(2, "\tDMA device interface %d\n", i);
1095 ia_css_debug_dtrace(2, "\t\tDMA internal side state\n");
1096 ia_css_debug_dtrace(2,
1097 "\t\t\tCS:%d - We_n:%d - Run:%d - Ack:%d\n",
1098 port->req_cs, port->req_we_n, port->req_run,
1099 port->req_ack);
1100 ia_css_debug_dtrace(2, "\t\tMaster Output side state\n");
1101 ia_css_debug_dtrace(2,
1102 "\t\t\tCS:%d - We_n:%d - Run:%d - Ack:%d\n",
1103 port->send_cs, port->send_we_n,
1104 port->send_run, port->send_ack);
1105 ia_css_debug_dtrace(2, "\t\tFifo state\n");
1106 if (port->fifo_state == DMA_FIFO_STATE_WILL_BE_FULL)
1107 ia_css_debug_dtrace(2, "\t\t\tFiFo will be full\n");
1108 else if (port->fifo_state == DMA_FIFO_STATE_FULL)
1109 ia_css_debug_dtrace(2, "\t\t\tFifo Full\n");
1110 else if (port->fifo_state == DMA_FIFO_STATE_EMPTY)
1111 ia_css_debug_dtrace(2, "\t\t\tFifo Empty\n");
1112 else
1113 ia_css_debug_dtrace(2, "\t\t\tFifo state unknown\n");
1114
1115 ia_css_debug_dtrace(2, "\t\tFifo counter %d\n\n",
1116 port->fifo_counter);
1117 }
1118
1119 for (i = 0; i < HIVE_DMA_NUM_CHANNELS; i++) {
1120 dma_channel_state_t *ch = &state.channel_states[i];
1121
1122 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "DMA channel register",
1123 i);
1124 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Connection",
1125 ch->connection);
1126 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Sign extend",
1127 ch->sign_extend);
1128 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Stride Dev A",
1129 ch->stride_a);
1130 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Elems Dev A",
1131 ch->elems_a);
1132 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropping Dev A",
1133 ch->cropping_a);
1134 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Width Dev A",
1135 ch->width_a);
1136 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Stride Dev B",
1137 ch->stride_b);
1138 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Elems Dev B",
1139 ch->elems_b);
1140 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropping Dev B",
1141 ch->cropping_b);
1142 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Width Dev B",
1143 ch->width_b);
1144 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Height", ch->height);
1145 }
1146 ia_css_debug_dtrace(2, "\n");
1147 return;
1148 }
1149
ia_css_debug_dump_dma_sp_fifo_state(void)1150 void ia_css_debug_dump_dma_sp_fifo_state(void)
1151 {
1152 fifo_channel_state_t dma_to_sp, sp_to_dma;
1153
1154 fifo_channel_get_state(FIFO_MONITOR0_ID,
1155 FIFO_CHANNEL_DMA0_TO_SP0, &dma_to_sp);
1156 fifo_channel_get_state(FIFO_MONITOR0_ID,
1157 FIFO_CHANNEL_SP0_TO_DMA0, &sp_to_dma);
1158 debug_print_fifo_channel_state(&dma_to_sp, "DMA to SP");
1159 debug_print_fifo_channel_state(&sp_to_dma, "SP to DMA");
1160 return;
1161 }
1162
ia_css_debug_dump_dma_isp_fifo_state(void)1163 void ia_css_debug_dump_dma_isp_fifo_state(void)
1164 {
1165 fifo_channel_state_t dma_to_isp, isp_to_dma;
1166
1167 fifo_channel_get_state(FIFO_MONITOR0_ID,
1168 FIFO_CHANNEL_DMA0_TO_ISP0, &dma_to_isp);
1169 fifo_channel_get_state(FIFO_MONITOR0_ID,
1170 FIFO_CHANNEL_ISP0_TO_DMA0, &isp_to_dma);
1171 debug_print_fifo_channel_state(&dma_to_isp, "DMA to ISP");
1172 debug_print_fifo_channel_state(&isp_to_dma, "ISP to DMA");
1173 return;
1174 }
1175
ia_css_debug_dump_isp_sp_fifo_state(void)1176 void ia_css_debug_dump_isp_sp_fifo_state(void)
1177 {
1178 fifo_channel_state_t sp_to_isp, isp_to_sp;
1179
1180 fifo_channel_get_state(FIFO_MONITOR0_ID,
1181 FIFO_CHANNEL_SP0_TO_ISP0, &sp_to_isp);
1182 fifo_channel_get_state(FIFO_MONITOR0_ID,
1183 FIFO_CHANNEL_ISP0_TO_SP0, &isp_to_sp);
1184 debug_print_fifo_channel_state(&sp_to_isp, "SP to ISP");
1185 debug_print_fifo_channel_state(&isp_to_sp, "ISP to SP");
1186 return;
1187 }
1188
ia_css_debug_dump_isp_gdc_fifo_state(void)1189 void ia_css_debug_dump_isp_gdc_fifo_state(void)
1190 {
1191 fifo_channel_state_t gdc_to_isp, isp_to_gdc;
1192
1193 fifo_channel_get_state(FIFO_MONITOR0_ID,
1194 FIFO_CHANNEL_GDC0_TO_ISP0, &gdc_to_isp);
1195 fifo_channel_get_state(FIFO_MONITOR0_ID,
1196 FIFO_CHANNEL_ISP0_TO_GDC0, &isp_to_gdc);
1197 debug_print_fifo_channel_state(&gdc_to_isp, "GDC to ISP");
1198 debug_print_fifo_channel_state(&isp_to_gdc, "ISP to GDC");
1199 return;
1200 }
1201
ia_css_debug_dump_all_fifo_state(void)1202 void ia_css_debug_dump_all_fifo_state(void)
1203 {
1204 int i;
1205 fifo_monitor_state_t state;
1206
1207 fifo_monitor_get_state(FIFO_MONITOR0_ID, &state);
1208
1209 for (i = 0; i < N_FIFO_CHANNEL; i++)
1210 debug_print_fifo_channel_state(&state.fifo_channels[i],
1211 "squepfstqkt");
1212 return;
1213 }
1214
debug_binary_info_print(const struct ia_css_binary_xinfo * info)1215 static void debug_binary_info_print(const struct ia_css_binary_xinfo *info)
1216 {
1217 assert(info);
1218 ia_css_debug_dtrace(2, "id = %d\n", info->sp.id);
1219 ia_css_debug_dtrace(2, "mode = %d\n", info->sp.pipeline.mode);
1220 ia_css_debug_dtrace(2, "max_input_width = %d\n", info->sp.input.max_width);
1221 ia_css_debug_dtrace(2, "min_output_width = %d\n",
1222 info->sp.output.min_width);
1223 ia_css_debug_dtrace(2, "max_output_width = %d\n",
1224 info->sp.output.max_width);
1225 ia_css_debug_dtrace(2, "top_cropping = %d\n", info->sp.pipeline.top_cropping);
1226 ia_css_debug_dtrace(2, "left_cropping = %d\n", info->sp.pipeline.left_cropping);
1227 ia_css_debug_dtrace(2, "xmem_addr = %d\n", info->xmem_addr);
1228 ia_css_debug_dtrace(2, "enable_vf_veceven = %d\n",
1229 info->sp.enable.vf_veceven);
1230 ia_css_debug_dtrace(2, "enable_dis = %d\n", info->sp.enable.dis);
1231 ia_css_debug_dtrace(2, "enable_uds = %d\n", info->sp.enable.uds);
1232 ia_css_debug_dtrace(2, "enable ds = %d\n", info->sp.enable.ds);
1233 ia_css_debug_dtrace(2, "s3atbl_use_dmem = %d\n", info->sp.s3a.s3atbl_use_dmem);
1234 return;
1235 }
1236
ia_css_debug_binary_print(const struct ia_css_binary * bi)1237 void ia_css_debug_binary_print(const struct ia_css_binary *bi)
1238 {
1239 unsigned int i;
1240
1241 debug_binary_info_print(bi->info);
1242 ia_css_debug_dtrace(2,
1243 "input: %dx%d, format = %d, padded width = %d\n",
1244 bi->in_frame_info.res.width,
1245 bi->in_frame_info.res.height,
1246 bi->in_frame_info.format,
1247 bi->in_frame_info.padded_width);
1248 ia_css_debug_dtrace(2,
1249 "internal :%dx%d, format = %d, padded width = %d\n",
1250 bi->internal_frame_info.res.width,
1251 bi->internal_frame_info.res.height,
1252 bi->internal_frame_info.format,
1253 bi->internal_frame_info.padded_width);
1254 for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) {
1255 if (bi->out_frame_info[i].res.width != 0) {
1256 ia_css_debug_dtrace(2,
1257 "out%d: %dx%d, format = %d, padded width = %d\n",
1258 i,
1259 bi->out_frame_info[i].res.width,
1260 bi->out_frame_info[i].res.height,
1261 bi->out_frame_info[i].format,
1262 bi->out_frame_info[i].padded_width);
1263 }
1264 }
1265 ia_css_debug_dtrace(2,
1266 "vf out: %dx%d, format = %d, padded width = %d\n",
1267 bi->vf_frame_info.res.width,
1268 bi->vf_frame_info.res.height,
1269 bi->vf_frame_info.format,
1270 bi->vf_frame_info.padded_width);
1271 ia_css_debug_dtrace(2, "online = %d\n", bi->online);
1272 ia_css_debug_dtrace(2, "input_buf_vectors = %d\n",
1273 bi->input_buf_vectors);
1274 ia_css_debug_dtrace(2, "deci_factor_log2 = %d\n", bi->deci_factor_log2);
1275 ia_css_debug_dtrace(2, "vf_downscale_log2 = %d\n",
1276 bi->vf_downscale_log2);
1277 ia_css_debug_dtrace(2, "dis_deci_factor_log2 = %d\n",
1278 bi->dis.deci_factor_log2);
1279 ia_css_debug_dtrace(2, "dis hor coef num = %d\n",
1280 bi->dis.coef.pad.width);
1281 ia_css_debug_dtrace(2, "dis ver coef num = %d\n",
1282 bi->dis.coef.pad.height);
1283 ia_css_debug_dtrace(2, "dis hor proj num = %d\n",
1284 bi->dis.proj.pad.height);
1285 ia_css_debug_dtrace(2, "sctbl_width_per_color = %d\n",
1286 bi->sctbl_width_per_color);
1287 ia_css_debug_dtrace(2, "s3atbl_width = %d\n", bi->s3atbl_width);
1288 ia_css_debug_dtrace(2, "s3atbl_height = %d\n", bi->s3atbl_height);
1289 return;
1290 }
1291
ia_css_debug_frame_print(const struct ia_css_frame * frame,const char * descr)1292 void ia_css_debug_frame_print(const struct ia_css_frame *frame,
1293 const char *descr)
1294 {
1295 char *data = NULL;
1296
1297 assert(frame);
1298 assert(descr);
1299
1300 data = (char *)HOST_ADDRESS(frame->data);
1301 ia_css_debug_dtrace(2, "frame %s (%p):\n", descr, frame);
1302 ia_css_debug_dtrace(2, " resolution = %dx%d\n",
1303 frame->frame_info.res.width, frame->frame_info.res.height);
1304 ia_css_debug_dtrace(2, " padded width = %d\n",
1305 frame->frame_info.padded_width);
1306 ia_css_debug_dtrace(2, " format = %d\n", frame->frame_info.format);
1307 switch (frame->frame_info.format) {
1308 case IA_CSS_FRAME_FORMAT_NV12:
1309 case IA_CSS_FRAME_FORMAT_NV16:
1310 case IA_CSS_FRAME_FORMAT_NV21:
1311 case IA_CSS_FRAME_FORMAT_NV61:
1312 ia_css_debug_dtrace(2, " Y = %p\n",
1313 data + frame->planes.nv.y.offset);
1314 ia_css_debug_dtrace(2, " UV = %p\n",
1315 data + frame->planes.nv.uv.offset);
1316 break;
1317 case IA_CSS_FRAME_FORMAT_YUYV:
1318 case IA_CSS_FRAME_FORMAT_UYVY:
1319 case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8:
1320 case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8:
1321 case IA_CSS_FRAME_FORMAT_YUV_LINE:
1322 ia_css_debug_dtrace(2, " YUYV = %p\n",
1323 data + frame->planes.yuyv.offset);
1324 break;
1325 case IA_CSS_FRAME_FORMAT_YUV420:
1326 case IA_CSS_FRAME_FORMAT_YUV422:
1327 case IA_CSS_FRAME_FORMAT_YUV444:
1328 case IA_CSS_FRAME_FORMAT_YV12:
1329 case IA_CSS_FRAME_FORMAT_YV16:
1330 case IA_CSS_FRAME_FORMAT_YUV420_16:
1331 case IA_CSS_FRAME_FORMAT_YUV422_16:
1332 ia_css_debug_dtrace(2, " Y = %p\n",
1333 data + frame->planes.yuv.y.offset);
1334 ia_css_debug_dtrace(2, " U = %p\n",
1335 data + frame->planes.yuv.u.offset);
1336 ia_css_debug_dtrace(2, " V = %p\n",
1337 data + frame->planes.yuv.v.offset);
1338 break;
1339 case IA_CSS_FRAME_FORMAT_RAW_PACKED:
1340 ia_css_debug_dtrace(2, " RAW PACKED = %p\n",
1341 data + frame->planes.raw.offset);
1342 break;
1343 case IA_CSS_FRAME_FORMAT_RAW:
1344 ia_css_debug_dtrace(2, " RAW = %p\n",
1345 data + frame->planes.raw.offset);
1346 break;
1347 case IA_CSS_FRAME_FORMAT_RGBA888:
1348 case IA_CSS_FRAME_FORMAT_RGB565:
1349 ia_css_debug_dtrace(2, " RGB = %p\n",
1350 data + frame->planes.rgb.offset);
1351 break;
1352 case IA_CSS_FRAME_FORMAT_QPLANE6:
1353 ia_css_debug_dtrace(2, " R = %p\n",
1354 data + frame->planes.plane6.r.offset);
1355 ia_css_debug_dtrace(2, " RatB = %p\n",
1356 data + frame->planes.plane6.r_at_b.offset);
1357 ia_css_debug_dtrace(2, " Gr = %p\n",
1358 data + frame->planes.plane6.gr.offset);
1359 ia_css_debug_dtrace(2, " Gb = %p\n",
1360 data + frame->planes.plane6.gb.offset);
1361 ia_css_debug_dtrace(2, " B = %p\n",
1362 data + frame->planes.plane6.b.offset);
1363 ia_css_debug_dtrace(2, " BatR = %p\n",
1364 data + frame->planes.plane6.b_at_r.offset);
1365 break;
1366 case IA_CSS_FRAME_FORMAT_BINARY_8:
1367 ia_css_debug_dtrace(2, " Binary data = %p\n",
1368 data + frame->planes.binary.data.offset);
1369 break;
1370 default:
1371 ia_css_debug_dtrace(2, " unknown frame type\n");
1372 break;
1373 }
1374 return;
1375 }
1376
1377 #if SP_DEBUG != SP_DEBUG_NONE
1378
ia_css_debug_print_sp_debug_state(const struct sh_css_sp_debug_state * state)1379 void ia_css_debug_print_sp_debug_state(const struct sh_css_sp_debug_state
1380 *state)
1381 {
1382 #endif
1383
1384 #if SP_DEBUG == SP_DEBUG_DUMP
1385
1386 assert(state);
1387 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1388 "current SP software counter: %d\n",
1389 state->debug[0]);
1390 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1391 "empty output buffer queue head: 0x%x\n",
1392 state->debug[1]);
1393 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1394 "empty output buffer queue tail: 0x%x\n",
1395 state->debug[2]);
1396 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1397 "empty s3a buffer queue head: 0x%x\n",
1398 state->debug[3]);
1399 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1400 "empty s3a buffer queue tail: 0x%x\n",
1401 state->debug[4]);
1402 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1403 "full output buffer queue head: 0x%x\n",
1404 state->debug[5]);
1405 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1406 "full output buffer queue tail: 0x%x\n",
1407 state->debug[6]);
1408 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1409 "full s3a buffer queue head: 0x%x\n",
1410 state->debug[7]);
1411 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1412 "full s3a buffer queue tail: 0x%x\n",
1413 state->debug[8]);
1414 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "event queue head: 0x%x\n",
1415 state->debug[9]);
1416 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "event queue tail: 0x%x\n",
1417 state->debug[10]);
1418 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1419 "num of stages of current pipeline: 0x%x\n",
1420 state->debug[11]);
1421 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "DDR address of stage 1: 0x%x\n",
1422 state->debug[12]);
1423 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "DDR address of stage 2: 0x%x\n",
1424 state->debug[13]);
1425 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1426 "current stage out_vf buffer idx: 0x%x\n",
1427 state->debug[14]);
1428 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1429 "current stage output buffer idx: 0x%x\n",
1430 state->debug[15]);
1431 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1432 "current stage s3a buffer idx: 0x%x\n",
1433 state->debug[16]);
1434 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1435 "first char of current stage name: 0x%x\n",
1436 state->debug[17]);
1437 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "current SP thread id: 0x%x\n",
1438 state->debug[18]);
1439 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1440 "empty output buffer address 1: 0x%x\n",
1441 state->debug[19]);
1442 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1443 "empty output buffer address 2: 0x%x\n",
1444 state->debug[20]);
1445 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1446 "empty out_vf buffer address 1: 0x%x\n",
1447 state->debug[21]);
1448 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1449 "empty out_vf buffer address 2: 0x%x\n",
1450 state->debug[22]);
1451 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1452 "empty s3a_hi buffer address 1: 0x%x\n",
1453 state->debug[23]);
1454 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1455 "empty s3a_hi buffer address 2: 0x%x\n",
1456 state->debug[24]);
1457 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1458 "empty s3a_lo buffer address 1: 0x%x\n",
1459 state->debug[25]);
1460 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1461 "empty s3a_lo buffer address 2: 0x%x\n",
1462 state->debug[26]);
1463 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1464 "empty dis_hor buffer address 1: 0x%x\n",
1465 state->debug[27]);
1466 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1467 "empty dis_hor buffer address 2: 0x%x\n",
1468 state->debug[28]);
1469 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1470 "empty dis_ver buffer address 1: 0x%x\n",
1471 state->debug[29]);
1472 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1473 "empty dis_ver buffer address 2: 0x%x\n",
1474 state->debug[30]);
1475 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1476 "empty param buffer address: 0x%x\n",
1477 state->debug[31]);
1478 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1479 "first incorrect frame address: 0x%x\n",
1480 state->debug[32]);
1481 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1482 "first incorrect frame container address: 0x%x\n",
1483 state->debug[33]);
1484 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1485 "first incorrect frame container payload: 0x%x\n",
1486 state->debug[34]);
1487 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1488 "first incorrect s3a_hi address: 0x%x\n",
1489 state->debug[35]);
1490 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1491 "first incorrect s3a_hi container address: 0x%x\n",
1492 state->debug[36]);
1493 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1494 "first incorrect s3a_hi container payload: 0x%x\n",
1495 state->debug[37]);
1496 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1497 "first incorrect s3a_lo address: 0x%x\n",
1498 state->debug[38]);
1499 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1500 "first incorrect s3a_lo container address: 0x%x\n",
1501 state->debug[39]);
1502 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1503 "first incorrect s3a_lo container payload: 0x%x\n",
1504 state->debug[40]);
1505 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1506 "number of calling flash start function: 0x%x\n",
1507 state->debug[41]);
1508 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1509 "number of calling flash close function: 0x%x\n",
1510 state->debug[42]);
1511 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "number of flashed frame: 0x%x\n",
1512 state->debug[43]);
1513 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "flash in use flag: 0x%x\n",
1514 state->debug[44]);
1515 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1516 "number of update frame flashed flag: 0x%x\n",
1517 state->debug[46]);
1518 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1519 "number of active threads: 0x%x\n",
1520 state->debug[45]);
1521
1522 #elif SP_DEBUG == SP_DEBUG_COPY
1523
1524 /* Remember last_index because we only want to print new entries */
1525 static int last_index;
1526 int sp_index = state->index;
1527 int n;
1528
1529 assert(state);
1530 if (sp_index < last_index) {
1531 /* SP has been reset */
1532 last_index = 0;
1533 }
1534
1535 if (last_index == 0) {
1536 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1537 "copy-trace init: sp_dbg_if_start_line=%d, sp_dbg_if_start_column=%d, sp_dbg_if_cropped_height=%d, sp_debg_if_cropped_width=%d\n",
1538 state->if_start_line,
1539 state->if_start_column,
1540 state->if_cropped_height,
1541 state->if_cropped_width);
1542 }
1543
1544 if ((last_index + SH_CSS_SP_DBG_TRACE_DEPTH) < sp_index) {
1545 /* last index can be multiple rounds behind */
1546 /* while trace size is only SH_CSS_SP_DBG_TRACE_DEPTH */
1547 last_index = sp_index - SH_CSS_SP_DBG_TRACE_DEPTH;
1548 }
1549
1550 for (n = last_index; n < sp_index; n++) {
1551 int i = n % SH_CSS_SP_DBG_TRACE_DEPTH;
1552
1553 if (state->trace[i].frame != 0) {
1554 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1555 "copy-trace: frame=%d, line=%d, pixel_distance=%d, mipi_used_dword=%d, sp_index=%d\n",
1556 state->trace[i].frame,
1557 state->trace[i].line,
1558 state->trace[i].pixel_distance,
1559 state->trace[i].mipi_used_dword,
1560 state->trace[i].sp_index);
1561 }
1562 }
1563
1564 last_index = sp_index;
1565
1566 #elif SP_DEBUG == SP_DEBUG_TRACE
1567
1568 /*
1569 * This is just an example how TRACE_FILE_ID (see ia_css_debug.sp.h) will
1570 * me mapped on the file name string.
1571 *
1572 * Adjust this to your trace case!
1573 */
1574 static char const *const id2filename[8] = {
1575 "param_buffer.sp.c | tagger.sp.c | pipe_data.sp.c",
1576 "isp_init.sp.c",
1577 "sp_raw_copy.hive.c",
1578 "dma_configure.sp.c",
1579 "sp.hive.c",
1580 "event_proxy_sp.hive.c",
1581 "circular_buffer.sp.c",
1582 "frame_buffer.sp.c"
1583 };
1584
1585 /* Example SH_CSS_SP_DBG_NR_OF_TRACES==1 */
1586 /* Adjust this to your trace case */
1587 static char const *trace_name[SH_CSS_SP_DBG_NR_OF_TRACES] = {
1588 "default"
1589 };
1590
1591 /* Remember host_index_last because we only want to print new entries */
1592 static int host_index_last[SH_CSS_SP_DBG_NR_OF_TRACES] = { 0 };
1593 int t, n;
1594
1595 assert(state);
1596
1597 for (t = 0; t < SH_CSS_SP_DBG_NR_OF_TRACES; t++) {
1598 int sp_index_last = state->index_last[t];
1599
1600 if (sp_index_last < host_index_last[t]) {
1601 /* SP has been reset */
1602 host_index_last[t] = 0;
1603 }
1604
1605 if ((host_index_last[t] + SH_CSS_SP_DBG_TRACE_DEPTH) <
1606 sp_index_last) {
1607 /* last index can be multiple rounds behind */
1608 /* while trace size is only SH_CSS_SP_DBG_TRACE_DEPTH */
1609 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1610 "Warning: trace %s has gap of %d traces\n",
1611 trace_name[t],
1612 (sp_index_last -
1613 (host_index_last[t] +
1614 SH_CSS_SP_DBG_TRACE_DEPTH)));
1615
1616 host_index_last[t] =
1617 sp_index_last - SH_CSS_SP_DBG_TRACE_DEPTH;
1618 }
1619
1620 for (n = host_index_last[t]; n < sp_index_last; n++) {
1621 int i = n % SH_CSS_SP_DBG_TRACE_DEPTH;
1622 int l = state->trace[t][i].location &
1623 ((1 << SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS) - 1);
1624 int fid = state->trace[t][i].location >>
1625 SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS;
1626 int ts = state->trace[t][i].time_stamp;
1627
1628 if (ts) {
1629 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1630 "%05d trace=%s, file=%s:%d, data=0x%08x\n",
1631 ts,
1632 trace_name[t],
1633 id2filename[fid], l,
1634 state->trace[t][i].data);
1635 }
1636 }
1637 host_index_last[t] = sp_index_last;
1638 }
1639
1640 #elif SP_DEBUG == SP_DEBUG_MINIMAL
1641 int i;
1642 int base = 0;
1643 int limit = SH_CSS_NUM_SP_DEBUG;
1644 int step = 1;
1645
1646 assert(state);
1647
1648 for (i = base; i < limit; i += step) {
1649 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1650 "sp_dbg_trace[%d] = %d\n",
1651 i, state->debug[i]);
1652 }
1653 #endif
1654
1655 #if SP_DEBUG != SP_DEBUG_NONE
1656
1657 return;
1658 }
1659 #endif
1660
1661 #if !defined(ISP2401)
debug_print_rx_mipi_port_state(mipi_port_state_t * state)1662 static void debug_print_rx_mipi_port_state(mipi_port_state_t *state)
1663 {
1664 int i;
1665 unsigned int bits, infos;
1666
1667 assert(state);
1668
1669 bits = state->irq_status;
1670 infos = ia_css_isys_rx_translate_irq_infos(bits);
1671
1672 ia_css_debug_dtrace(2, "\t\t%-32s: (irq reg = 0x%X)\n",
1673 "receiver errors", bits);
1674
1675 if (infos & IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN)
1676 ia_css_debug_dtrace(2, "\t\t\tbuffer overrun\n");
1677 if (infos & IA_CSS_RX_IRQ_INFO_ERR_SOT)
1678 ia_css_debug_dtrace(2, "\t\t\tstart-of-transmission error\n");
1679 if (infos & IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC)
1680 ia_css_debug_dtrace(2, "\t\t\tstart-of-transmission sync error\n");
1681 if (infos & IA_CSS_RX_IRQ_INFO_ERR_CONTROL)
1682 ia_css_debug_dtrace(2, "\t\t\tcontrol error\n");
1683 if (infos & IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE)
1684 ia_css_debug_dtrace(2, "\t\t\t2 or more ECC errors\n");
1685 if (infos & IA_CSS_RX_IRQ_INFO_ERR_CRC)
1686 ia_css_debug_dtrace(2, "\t\t\tCRC mismatch\n");
1687 if (infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID)
1688 ia_css_debug_dtrace(2, "\t\t\tunknown error\n");
1689 if (infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC)
1690 ia_css_debug_dtrace(2, "\t\t\tframe sync error\n");
1691 if (infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA)
1692 ia_css_debug_dtrace(2, "\t\t\tframe data error\n");
1693 if (infos & IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT)
1694 ia_css_debug_dtrace(2, "\t\t\tdata timeout\n");
1695 if (infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC)
1696 ia_css_debug_dtrace(2, "\t\t\tunknown escape command entry\n");
1697 if (infos & IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC)
1698 ia_css_debug_dtrace(2, "\t\t\tline sync error\n");
1699
1700 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1701 "device_ready", state->device_ready);
1702
1703 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1704 "irq_status", state->irq_status);
1705
1706 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1707 "irq_enable", state->irq_enable);
1708
1709 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1710 "timeout_count", state->timeout_count);
1711
1712 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1713 "init_count", state->init_count);
1714
1715 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw16_18", state->raw16_18);
1716
1717 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1718 "sync_count", state->sync_count);
1719
1720 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "rx_count", state->rx_count);
1721
1722 for (i = 0; i < MIPI_4LANE_CFG; i++) {
1723 ia_css_debug_dtrace(2, "\t\t%-32s%d%-32s: %d\n",
1724 "lane_sync_count[", i, "]",
1725 state->lane_sync_count[i]);
1726 }
1727
1728 for (i = 0; i < MIPI_4LANE_CFG; i++) {
1729 ia_css_debug_dtrace(2, "\t\t%-32s%d%-32s: %d\n",
1730 "lane_rx_count[", i, "]",
1731 state->lane_rx_count[i]);
1732 }
1733
1734 return;
1735 }
1736
debug_print_rx_channel_state(rx_channel_state_t * state)1737 static void debug_print_rx_channel_state(rx_channel_state_t *state)
1738 {
1739 int i;
1740
1741 assert(state);
1742 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1743 "compression_scheme0", state->comp_scheme0);
1744
1745 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1746 "compression_scheme1", state->comp_scheme1);
1747
1748 for (i = 0; i < N_MIPI_FORMAT_CUSTOM; i++) {
1749 ia_css_debug_dtrace(2, "\t\t%-32s%d: %d\n",
1750 "MIPI Predictor ", i, state->pred[i]);
1751 }
1752
1753 for (i = 0; i < N_MIPI_FORMAT_CUSTOM; i++) {
1754 ia_css_debug_dtrace(2, "\t\t%-32s%d: %d\n",
1755 "MIPI Compressor ", i, state->comp[i]);
1756 }
1757
1758 return;
1759 }
1760
debug_print_rx_state(receiver_state_t * state)1761 static void debug_print_rx_state(receiver_state_t *state)
1762 {
1763 int i;
1764
1765 assert(state);
1766 ia_css_debug_dtrace(2, "CSI Receiver State:\n");
1767
1768 ia_css_debug_dtrace(2, "\tConfiguration:\n");
1769
1770 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1771 "fs_to_ls_delay", state->fs_to_ls_delay);
1772
1773 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1774 "ls_to_data_delay", state->ls_to_data_delay);
1775
1776 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1777 "data_to_le_delay", state->data_to_le_delay);
1778
1779 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1780 "le_to_fe_delay", state->le_to_fe_delay);
1781
1782 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1783 "fe_to_fs_delay", state->fe_to_fs_delay);
1784
1785 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1786 "le_to_fs_delay", state->le_to_fs_delay);
1787
1788 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1789 "is_two_ppc", state->is_two_ppc);
1790
1791 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1792 "backend_rst", state->backend_rst);
1793
1794 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw18", state->raw18);
1795
1796 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1797 "force_raw8", state->force_raw8);
1798
1799 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw16", state->raw16);
1800
1801 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1802 "be_gsp_acc_ovl", state->be_gsp_acc_ovl);
1803
1804 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "be_srst", state->be_srst);
1805
1806 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1807 "be_is_two_ppc", state->be_is_two_ppc);
1808
1809 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1810 "be_comp_format0", state->be_comp_format0);
1811
1812 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1813 "be_comp_format1", state->be_comp_format1);
1814
1815 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1816 "be_comp_format2", state->be_comp_format2);
1817
1818 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1819 "be_comp_format3", state->be_comp_format3);
1820
1821 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "be_sel", state->be_sel);
1822
1823 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1824 "be_raw16_config", state->be_raw16_config);
1825
1826 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1827 "be_raw18_config", state->be_raw18_config);
1828
1829 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1830 "be_force_raw8", state->be_force_raw8);
1831
1832 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1833 "be_irq_status", state->be_irq_status);
1834
1835 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1836 "be_irq_clear", state->be_irq_clear);
1837
1838 /* mipi port state */
1839 for (i = 0; i < N_MIPI_PORT_ID; i++) {
1840 ia_css_debug_dtrace(2, "\tMIPI Port %d State:\n", i);
1841
1842 debug_print_rx_mipi_port_state(&state->mipi_port_state[i]);
1843 }
1844 /* end of mipi port state */
1845
1846 /* rx channel state */
1847 for (i = 0; i < N_RX_CHANNEL_ID; i++) {
1848 ia_css_debug_dtrace(2, "\tRX Channel %d State:\n", i);
1849
1850 debug_print_rx_channel_state(&state->rx_channel_state[i]);
1851 }
1852 /* end of rx channel state */
1853
1854 return;
1855 }
1856 #endif
1857
ia_css_debug_dump_rx_state(void)1858 void ia_css_debug_dump_rx_state(void)
1859 {
1860 #if !defined(ISP2401)
1861 receiver_state_t state;
1862
1863 receiver_get_state(RX0_ID, &state);
1864 debug_print_rx_state(&state);
1865 #endif
1866 }
1867
ia_css_debug_dump_sp_sw_debug_info(void)1868 void ia_css_debug_dump_sp_sw_debug_info(void)
1869 {
1870 #if SP_DEBUG != SP_DEBUG_NONE
1871 struct sh_css_sp_debug_state state;
1872
1873 sh_css_sp_get_debug_state(&state);
1874 ia_css_debug_print_sp_debug_state(&state);
1875 #endif
1876 ia_css_bufq_dump_queue_info();
1877 ia_css_pipeline_dump_thread_map_info();
1878 return;
1879 }
1880
1881 #if !defined(ISP2401)
debug_print_isys_capture_unit_state(capture_unit_state_t * state)1882 static void debug_print_isys_capture_unit_state(capture_unit_state_t *state)
1883 {
1884 assert(state);
1885 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1886 "Packet_Length", state->Packet_Length);
1887
1888 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1889 "Received_Length", state->Received_Length);
1890
1891 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1892 "Received_Short_Packets",
1893 state->Received_Short_Packets);
1894
1895 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1896 "Received_Long_Packets",
1897 state->Received_Long_Packets);
1898
1899 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1900 "Last_Command", state->Last_Command);
1901
1902 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1903 "Next_Command", state->Next_Command);
1904
1905 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1906 "Last_Acknowledge", state->Last_Acknowledge);
1907
1908 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1909 "Next_Acknowledge", state->Next_Acknowledge);
1910
1911 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1912 "FSM_State_Info", state->FSM_State_Info);
1913
1914 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1915 "StartMode", state->StartMode);
1916
1917 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1918 "Start_Addr", state->Start_Addr);
1919
1920 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1921 "Mem_Region_Size", state->Mem_Region_Size);
1922
1923 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1924 "Num_Mem_Regions", state->Num_Mem_Regions);
1925 return;
1926 }
1927
debug_print_isys_acquisition_unit_state(acquisition_unit_state_t * state)1928 static void debug_print_isys_acquisition_unit_state(
1929 acquisition_unit_state_t *state)
1930 {
1931 assert(state);
1932
1933 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1934 "Received_Short_Packets",
1935 state->Received_Short_Packets);
1936
1937 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1938 "Received_Long_Packets",
1939 state->Received_Long_Packets);
1940
1941 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1942 "Last_Command", state->Last_Command);
1943
1944 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1945 "Next_Command", state->Next_Command);
1946
1947 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1948 "Last_Acknowledge", state->Last_Acknowledge);
1949
1950 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1951 "Next_Acknowledge", state->Next_Acknowledge);
1952
1953 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1954 "FSM_State_Info", state->FSM_State_Info);
1955
1956 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1957 "Int_Cntr_Info", state->Int_Cntr_Info);
1958
1959 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1960 "Start_Addr", state->Start_Addr);
1961
1962 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1963 "Mem_Region_Size", state->Mem_Region_Size);
1964
1965 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1966 "Num_Mem_Regions", state->Num_Mem_Regions);
1967 }
1968
debug_print_isys_ctrl_unit_state(ctrl_unit_state_t * state)1969 static void debug_print_isys_ctrl_unit_state(ctrl_unit_state_t *state)
1970 {
1971 assert(state);
1972 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "last_cmd", state->last_cmd);
1973
1974 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "next_cmd", state->next_cmd);
1975
1976 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "last_ack", state->last_ack);
1977
1978 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "next_ack", state->next_ack);
1979
1980 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1981 "top_fsm_state", state->top_fsm_state);
1982
1983 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1984 "captA_fsm_state", state->captA_fsm_state);
1985
1986 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1987 "captB_fsm_state", state->captB_fsm_state);
1988
1989 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1990 "captC_fsm_state", state->captC_fsm_state);
1991
1992 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1993 "acq_fsm_state", state->acq_fsm_state);
1994
1995 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1996 "captA_start_addr", state->captA_start_addr);
1997
1998 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1999 "captB_start_addr", state->captB_start_addr);
2000
2001 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2002 "captC_start_addr", state->captC_start_addr);
2003
2004 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2005 "captA_mem_region_size",
2006 state->captA_mem_region_size);
2007
2008 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2009 "captB_mem_region_size",
2010 state->captB_mem_region_size);
2011
2012 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2013 "captC_mem_region_size",
2014 state->captC_mem_region_size);
2015
2016 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2017 "captA_num_mem_regions",
2018 state->captA_num_mem_regions);
2019
2020 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2021 "captB_num_mem_regions",
2022 state->captB_num_mem_regions);
2023
2024 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2025 "captC_num_mem_regions",
2026 state->captC_num_mem_regions);
2027
2028 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2029 "acq_start_addr", state->acq_start_addr);
2030
2031 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2032 "acq_mem_region_size", state->acq_mem_region_size);
2033
2034 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2035 "acq_num_mem_regions", state->acq_num_mem_regions);
2036
2037 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2038 "capt_reserve_one_mem_region",
2039 state->capt_reserve_one_mem_region);
2040
2041 return;
2042 }
2043
debug_print_isys_state(input_system_state_t * state)2044 static void debug_print_isys_state(input_system_state_t *state)
2045 {
2046 int i;
2047
2048 assert(state);
2049 ia_css_debug_dtrace(2, "InputSystem State:\n");
2050
2051 /* configuration */
2052 ia_css_debug_dtrace(2, "\tConfiguration:\n");
2053
2054 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2055 "str_multiCastA_sel", state->str_multicastA_sel);
2056
2057 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2058 "str_multicastB_sel", state->str_multicastB_sel);
2059
2060 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2061 "str_multicastC_sel", state->str_multicastC_sel);
2062
2063 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2064 "str_mux_sel", state->str_mux_sel);
2065
2066 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2067 "str_mon_status", state->str_mon_status);
2068
2069 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2070 "str_mon_irq_cond", state->str_mon_irq_cond);
2071
2072 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2073 "str_mon_irq_en", state->str_mon_irq_en);
2074
2075 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2076 "isys_srst", state->isys_srst);
2077
2078 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2079 "isys_slv_reg_srst", state->isys_slv_reg_srst);
2080
2081 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2082 "str_deint_portA_cnt", state->str_deint_portA_cnt);
2083
2084 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2085 "str_deint_portB_cnd", state->str_deint_portB_cnt);
2086 /* end of configuration */
2087
2088 /* capture unit state */
2089 for (i = 0; i < N_CAPTURE_UNIT_ID; i++) {
2090 capture_unit_state_t *capture_unit_state;
2091
2092 ia_css_debug_dtrace(2, "\tCaptureUnit %d State:\n", i);
2093
2094 capture_unit_state = &state->capture_unit[i];
2095 debug_print_isys_capture_unit_state(capture_unit_state);
2096 }
2097 /* end of capture unit state */
2098
2099 /* acquisition unit state */
2100 for (i = 0; i < N_ACQUISITION_UNIT_ID; i++) {
2101 acquisition_unit_state_t *acquisition_unit_state;
2102
2103 ia_css_debug_dtrace(2, "\tAcquisitionUnit %d State:\n", i);
2104
2105 acquisition_unit_state = &state->acquisition_unit[i];
2106 debug_print_isys_acquisition_unit_state(acquisition_unit_state);
2107 }
2108 /* end of acquisition unit state */
2109
2110 /* control unit state */
2111 for (i = 0; i < N_CTRL_UNIT_ID; i++) {
2112 ia_css_debug_dtrace(2, "\tControlUnit %d State:\n", i);
2113
2114 debug_print_isys_ctrl_unit_state(&state->ctrl_unit_state[i]);
2115 }
2116 /* end of control unit state */
2117 }
2118 #endif
2119
ia_css_debug_dump_isys_state(void)2120 void ia_css_debug_dump_isys_state(void)
2121 {
2122 static input_system_state_t state;
2123
2124 input_system_get_state(INPUT_SYSTEM0_ID, &state);
2125
2126 #ifndef ISP2401
2127 debug_print_isys_state(&state);
2128 #else
2129 input_system_dump_state(INPUT_SYSTEM0_ID, &state);
2130 #endif
2131 }
2132
ia_css_debug_dump_debug_info(const char * context)2133 void ia_css_debug_dump_debug_info(const char *context)
2134 {
2135 if (!context)
2136 context = "No Context provided";
2137
2138 ia_css_debug_dtrace(2, "CSS Debug Info dump [Context = %s]\n", context);
2139 if (!IS_ISP2401)
2140 ia_css_debug_dump_rx_state();
2141
2142 #ifndef ISP2401
2143 ia_css_debug_dump_if_state();
2144 #endif
2145 ia_css_debug_dump_isp_state();
2146 ia_css_debug_dump_isp_sp_fifo_state();
2147 ia_css_debug_dump_isp_gdc_fifo_state();
2148 ia_css_debug_dump_sp_state();
2149 ia_css_debug_dump_perf_counters();
2150
2151 #ifdef HAS_WATCHDOG_SP_THREAD_DEBUG
2152 sh_css_dump_thread_wait_info();
2153 sh_css_dump_pipe_stage_info();
2154 sh_css_dump_pipe_stripe_info();
2155 #endif
2156 ia_css_debug_dump_dma_isp_fifo_state();
2157 ia_css_debug_dump_dma_sp_fifo_state();
2158 ia_css_debug_dump_dma_state();
2159
2160 if (!IS_ISP2401) {
2161 struct irq_controller_state state;
2162
2163 ia_css_debug_dump_isys_state();
2164
2165 irq_controller_get_state(IRQ2_ID, &state);
2166
2167 ia_css_debug_dtrace(2, "\t%-32s:\n",
2168 "Input System IRQ Controller State");
2169
2170 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2171 "irq_edge", state.irq_edge);
2172
2173 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2174 "irq_mask", state.irq_mask);
2175
2176 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2177 "irq_status", state.irq_status);
2178
2179 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2180 "irq_enable", state.irq_enable);
2181
2182 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2183 "irq_level_not_pulse",
2184 state.irq_level_not_pulse);
2185 } else {
2186 ia_css_debug_dump_isys_state();
2187 }
2188
2189 ia_css_debug_tagger_state();
2190
2191 return;
2192 }
2193
2194 /* this function is for debug use, it can make SP go to sleep
2195 state after each frame, then user can dump the stable SP dmem.
2196 this function can be called after ia_css_start_sp()
2197 and before sh_css_init_buffer_queues()
2198 */
ia_css_debug_enable_sp_sleep_mode(enum ia_css_sp_sleep_mode mode)2199 void ia_css_debug_enable_sp_sleep_mode(enum ia_css_sp_sleep_mode mode)
2200 {
2201 const struct ia_css_fw_info *fw;
2202 unsigned int HIVE_ADDR_sp_sleep_mode;
2203
2204 fw = &sh_css_sp_fw;
2205 HIVE_ADDR_sp_sleep_mode = fw->info.sp.sleep_mode;
2206
2207 (void)HIVE_ADDR_sp_sleep_mode; /* Suppres warnings in CRUN */
2208
2209 sp_dmem_store_uint32(SP0_ID,
2210 (unsigned int)sp_address_of(sp_sleep_mode),
2211 (uint32_t)mode);
2212 }
2213
ia_css_debug_wake_up_sp(void)2214 void ia_css_debug_wake_up_sp(void)
2215 {
2216 /*hrt_ctl_start(SP); */
2217 sp_ctrl_setbit(SP0_ID, SP_SC_REG, SP_START_BIT);
2218 }
2219
2220 #define FIND_DMEM_PARAMS_TYPE(stream, kernel, type) \
2221 (struct HRTCAT(HRTCAT(sh_css_isp_, type), _params) *) \
2222 findf_dmem_params(stream, offsetof(struct ia_css_memory_offsets, dmem.kernel))
2223
2224 #define FIND_DMEM_PARAMS(stream, kernel) FIND_DMEM_PARAMS_TYPE(stream, kernel, kernel)
2225
2226 /* Find a stage that support the kernel and return the parameters for that kernel */
2227 static char *
findf_dmem_params(struct ia_css_stream * stream,short idx)2228 findf_dmem_params(struct ia_css_stream *stream, short idx)
2229 {
2230 int i;
2231
2232 for (i = 0; i < stream->num_pipes; i++) {
2233 struct ia_css_pipe *pipe = stream->pipes[i];
2234 struct ia_css_pipeline *pipeline = ia_css_pipe_get_pipeline(pipe);
2235 struct ia_css_pipeline_stage *stage;
2236
2237 for (stage = pipeline->stages; stage; stage = stage->next) {
2238 struct ia_css_binary *binary = stage->binary;
2239 short *offsets = (short *)&binary->info->mem_offsets.offsets.param->dmem;
2240 short dmem_offset = offsets[idx];
2241 const struct ia_css_host_data *isp_data =
2242 ia_css_isp_param_get_mem_init(&binary->mem_params,
2243 IA_CSS_PARAM_CLASS_PARAM, IA_CSS_ISP_DMEM0);
2244 if (dmem_offset < 0)
2245 continue;
2246 return &isp_data->address[dmem_offset];
2247 }
2248 }
2249 return NULL;
2250 }
2251
ia_css_debug_dump_isp_params(struct ia_css_stream * stream,unsigned int enable)2252 void ia_css_debug_dump_isp_params(struct ia_css_stream *stream,
2253 unsigned int enable)
2254 {
2255 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "ISP PARAMETERS:\n");
2256
2257 assert(stream);
2258 if ((enable & IA_CSS_DEBUG_DUMP_FPN)
2259 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2260 ia_css_fpn_dump(FIND_DMEM_PARAMS(stream, fpn), IA_CSS_DEBUG_VERBOSE);
2261 }
2262 if ((enable & IA_CSS_DEBUG_DUMP_OB)
2263 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2264 ia_css_ob_dump(FIND_DMEM_PARAMS(stream, ob), IA_CSS_DEBUG_VERBOSE);
2265 }
2266 if ((enable & IA_CSS_DEBUG_DUMP_SC)
2267 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2268 ia_css_sc_dump(FIND_DMEM_PARAMS(stream, sc), IA_CSS_DEBUG_VERBOSE);
2269 }
2270 if ((enable & IA_CSS_DEBUG_DUMP_WB)
2271 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2272 ia_css_wb_dump(FIND_DMEM_PARAMS(stream, wb), IA_CSS_DEBUG_VERBOSE);
2273 }
2274 if ((enable & IA_CSS_DEBUG_DUMP_DP)
2275 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2276 ia_css_dp_dump(FIND_DMEM_PARAMS(stream, dp), IA_CSS_DEBUG_VERBOSE);
2277 }
2278 if ((enable & IA_CSS_DEBUG_DUMP_BNR)
2279 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2280 ia_css_bnr_dump(FIND_DMEM_PARAMS(stream, bnr), IA_CSS_DEBUG_VERBOSE);
2281 }
2282 if ((enable & IA_CSS_DEBUG_DUMP_S3A)
2283 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2284 ia_css_s3a_dump(FIND_DMEM_PARAMS(stream, s3a), IA_CSS_DEBUG_VERBOSE);
2285 }
2286 if ((enable & IA_CSS_DEBUG_DUMP_DE)
2287 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2288 ia_css_de_dump(FIND_DMEM_PARAMS(stream, de), IA_CSS_DEBUG_VERBOSE);
2289 }
2290 if ((enable & IA_CSS_DEBUG_DUMP_YNR)
2291 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2292 ia_css_nr_dump(FIND_DMEM_PARAMS_TYPE(stream, nr, ynr), IA_CSS_DEBUG_VERBOSE);
2293 ia_css_yee_dump(FIND_DMEM_PARAMS(stream, yee), IA_CSS_DEBUG_VERBOSE);
2294 }
2295 if ((enable & IA_CSS_DEBUG_DUMP_CSC)
2296 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2297 ia_css_csc_dump(FIND_DMEM_PARAMS(stream, csc), IA_CSS_DEBUG_VERBOSE);
2298 ia_css_yuv2rgb_dump(FIND_DMEM_PARAMS_TYPE(stream, yuv2rgb, csc),
2299 IA_CSS_DEBUG_VERBOSE);
2300 ia_css_rgb2yuv_dump(FIND_DMEM_PARAMS_TYPE(stream, rgb2yuv, csc),
2301 IA_CSS_DEBUG_VERBOSE);
2302 }
2303 if ((enable & IA_CSS_DEBUG_DUMP_GC)
2304 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2305 ia_css_gc_dump(FIND_DMEM_PARAMS(stream, gc), IA_CSS_DEBUG_VERBOSE);
2306 }
2307 if ((enable & IA_CSS_DEBUG_DUMP_TNR)
2308 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2309 ia_css_tnr_dump(FIND_DMEM_PARAMS(stream, tnr), IA_CSS_DEBUG_VERBOSE);
2310 }
2311 if ((enable & IA_CSS_DEBUG_DUMP_ANR)
2312 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2313 ia_css_anr_dump(FIND_DMEM_PARAMS(stream, anr), IA_CSS_DEBUG_VERBOSE);
2314 }
2315 if ((enable & IA_CSS_DEBUG_DUMP_CE)
2316 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2317 ia_css_ce_dump(FIND_DMEM_PARAMS(stream, ce), IA_CSS_DEBUG_VERBOSE);
2318 }
2319 }
2320
sh_css_dump_sp_raw_copy_linecount(bool reduced)2321 void sh_css_dump_sp_raw_copy_linecount(bool reduced)
2322 {
2323 const struct ia_css_fw_info *fw;
2324 unsigned int HIVE_ADDR_raw_copy_line_count;
2325 s32 raw_copy_line_count;
2326 static s32 prev_raw_copy_line_count = -1;
2327
2328 fw = &sh_css_sp_fw;
2329 HIVE_ADDR_raw_copy_line_count =
2330 fw->info.sp.raw_copy_line_count;
2331
2332 (void)HIVE_ADDR_raw_copy_line_count;
2333
2334 sp_dmem_load(SP0_ID,
2335 (unsigned int)sp_address_of(raw_copy_line_count),
2336 &raw_copy_line_count,
2337 sizeof(raw_copy_line_count));
2338
2339 /* only indicate if copy loop is active */
2340 if (reduced)
2341 raw_copy_line_count = (raw_copy_line_count < 0) ? raw_copy_line_count : 1;
2342 /* do the handling */
2343 if (prev_raw_copy_line_count != raw_copy_line_count) {
2344 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
2345 "sh_css_dump_sp_raw_copy_linecount() line_count=%d\n",
2346 raw_copy_line_count);
2347 prev_raw_copy_line_count = raw_copy_line_count;
2348 }
2349 }
2350
ia_css_debug_dump_isp_binary(void)2351 void ia_css_debug_dump_isp_binary(void)
2352 {
2353 const struct ia_css_fw_info *fw;
2354 unsigned int HIVE_ADDR_pipeline_sp_curr_binary_id;
2355 u32 curr_binary_id;
2356 static u32 prev_binary_id = 0xFFFFFFFF;
2357 static u32 sample_count;
2358
2359 fw = &sh_css_sp_fw;
2360 HIVE_ADDR_pipeline_sp_curr_binary_id = fw->info.sp.curr_binary_id;
2361
2362 (void)HIVE_ADDR_pipeline_sp_curr_binary_id;
2363
2364 sp_dmem_load(SP0_ID,
2365 (unsigned int)sp_address_of(pipeline_sp_curr_binary_id),
2366 &curr_binary_id,
2367 sizeof(curr_binary_id));
2368
2369 /* do the handling */
2370 sample_count++;
2371 if (prev_binary_id != curr_binary_id) {
2372 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
2373 "sh_css_dump_isp_binary() pipe_id=%d, binary_id=%d, sample_count=%d\n",
2374 (curr_binary_id >> 16),
2375 (curr_binary_id & 0x0ffff),
2376 sample_count);
2377 sample_count = 0;
2378 prev_binary_id = curr_binary_id;
2379 }
2380 }
2381
ia_css_debug_dump_perf_counters(void)2382 void ia_css_debug_dump_perf_counters(void)
2383 {
2384 const struct ia_css_fw_info *fw;
2385 int i;
2386 unsigned int HIVE_ADDR_ia_css_isys_sp_error_cnt;
2387 /* N_MIPI_PORT_ID + 1: 3 Capture Units and 1 Acquire Unit. */
2388 s32 ia_css_sp_input_system_error_cnt[N_MIPI_PORT_ID + 1];
2389
2390 if (IS_ISP2401)
2391 return;
2392
2393 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "Input System Error Counters:\n");
2394
2395 fw = &sh_css_sp_fw;
2396 HIVE_ADDR_ia_css_isys_sp_error_cnt =
2397 fw->info.sp.perf_counter_input_system_error;
2398
2399 (void)HIVE_ADDR_ia_css_isys_sp_error_cnt;
2400
2401 sp_dmem_load(SP0_ID,
2402 (unsigned int)sp_address_of(ia_css_isys_sp_error_cnt),
2403 &ia_css_sp_input_system_error_cnt,
2404 sizeof(ia_css_sp_input_system_error_cnt));
2405
2406 for (i = 0; i < N_MIPI_PORT_ID + 1; i++) {
2407 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\tport[%d] = %d\n",
2408 i, ia_css_sp_input_system_error_cnt[i]);
2409 }
2410 }
2411
2412 /*
2413 * @brief Initialize the debug mode.
2414 * Refer to "ia_css_debug.h" for more details.
2415 */
ia_css_debug_mode_init(void)2416 bool ia_css_debug_mode_init(void)
2417 {
2418 bool rc;
2419
2420 rc = sh_css_sp_init_dma_sw_reg(0);
2421 return rc;
2422 }
2423
2424 /*
2425 * @brief Disable the DMA channel.
2426 * Refer to "ia_css_debug.h" for more details.
2427 */
2428 bool
ia_css_debug_mode_disable_dma_channel(int dma_id,int channel_id,int request_type)2429 ia_css_debug_mode_disable_dma_channel(int dma_id,
2430 int channel_id, int request_type)
2431 {
2432 bool rc;
2433
2434 rc = sh_css_sp_set_dma_sw_reg(dma_id, channel_id, request_type, false);
2435
2436 return rc;
2437 }
2438
2439 /*
2440 * @brief Enable the DMA channel.
2441 * Refer to "ia_css_debug.h" for more details.
2442 */
2443 bool
ia_css_debug_mode_enable_dma_channel(int dma_id,int channel_id,int request_type)2444 ia_css_debug_mode_enable_dma_channel(int dma_id,
2445 int channel_id, int request_type)
2446 {
2447 bool rc;
2448
2449 rc = sh_css_sp_set_dma_sw_reg(dma_id, channel_id, request_type, true);
2450
2451 return rc;
2452 }
2453
dtrace_dot(const char * fmt,...)2454 static void __printf(1, 2) dtrace_dot(const char *fmt, ...)
2455 {
2456 va_list ap;
2457
2458 assert(fmt);
2459 va_start(ap, fmt);
2460
2461 ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_START);
2462 ia_css_debug_vdtrace(IA_CSS_DEBUG_INFO, fmt, ap);
2463 ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_END);
2464 va_end(ap);
2465 }
2466
2467 #ifdef HAS_WATCHDOG_SP_THREAD_DEBUG
sh_css_dump_thread_wait_info(void)2468 void sh_css_dump_thread_wait_info(void)
2469 {
2470 const struct ia_css_fw_info *fw;
2471 int i;
2472 unsigned int HIVE_ADDR_sp_thread_wait;
2473 s32 sp_thread_wait[MAX_THREAD_NUM];
2474
2475 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "SEM WAITS:\n");
2476
2477 fw = &sh_css_sp_fw;
2478 HIVE_ADDR_sp_thread_wait =
2479 fw->info.sp.debug_wait;
2480
2481 (void)HIVE_ADDR_sp_thread_wait;
2482
2483 sp_dmem_load(SP0_ID,
2484 (unsigned int)sp_address_of(sp_thread_wait),
2485 &sp_thread_wait,
2486 sizeof(sp_thread_wait));
2487 for (i = 0; i < MAX_THREAD_NUM; i++) {
2488 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
2489 "\twait[%d] = 0x%X\n",
2490 i, sp_thread_wait[i]);
2491 }
2492 }
2493
sh_css_dump_pipe_stage_info(void)2494 void sh_css_dump_pipe_stage_info(void)
2495 {
2496 const struct ia_css_fw_info *fw;
2497 int i;
2498 unsigned int HIVE_ADDR_sp_pipe_stage;
2499 s32 sp_pipe_stage[MAX_THREAD_NUM];
2500
2501 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "PIPE STAGE:\n");
2502
2503 fw = &sh_css_sp_fw;
2504 HIVE_ADDR_sp_pipe_stage =
2505 fw->info.sp.debug_stage;
2506
2507 (void)HIVE_ADDR_sp_pipe_stage;
2508
2509 sp_dmem_load(SP0_ID,
2510 (unsigned int)sp_address_of(sp_pipe_stage),
2511 &sp_pipe_stage,
2512 sizeof(sp_pipe_stage));
2513 for (i = 0; i < MAX_THREAD_NUM; i++) {
2514 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
2515 "\tstage[%d] = %d\n",
2516 i, sp_pipe_stage[i]);
2517 }
2518 }
2519
sh_css_dump_pipe_stripe_info(void)2520 void sh_css_dump_pipe_stripe_info(void)
2521 {
2522 const struct ia_css_fw_info *fw;
2523 int i;
2524 unsigned int HIVE_ADDR_sp_pipe_stripe;
2525 s32 sp_pipe_stripe[MAX_THREAD_NUM];
2526
2527 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "PIPE STRIPE:\n");
2528
2529 fw = &sh_css_sp_fw;
2530 HIVE_ADDR_sp_pipe_stripe =
2531 fw->info.sp.debug_stripe;
2532
2533 (void)HIVE_ADDR_sp_pipe_stripe;
2534
2535 sp_dmem_load(SP0_ID,
2536 (unsigned int)sp_address_of(sp_pipe_stripe),
2537 &sp_pipe_stripe,
2538 sizeof(sp_pipe_stripe));
2539 for (i = 0; i < MAX_THREAD_NUM; i++) {
2540 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
2541 "\tstripe[%d] = %d\n",
2542 i, sp_pipe_stripe[i]);
2543 }
2544 }
2545 #endif
2546
2547 static void
ia_css_debug_pipe_graph_dump_frame(const struct ia_css_frame * frame,enum ia_css_pipe_id id,char const * blob_name,char const * frame_name,bool in_frame)2548 ia_css_debug_pipe_graph_dump_frame(
2549 const struct ia_css_frame *frame,
2550 enum ia_css_pipe_id id,
2551 char const *blob_name,
2552 char const *frame_name,
2553 bool in_frame)
2554 {
2555 char bufinfo[100];
2556
2557 if (frame->dynamic_queue_id == SH_CSS_INVALID_QUEUE_ID) {
2558 snprintf(bufinfo, sizeof(bufinfo), "Internal");
2559 } else {
2560 snprintf(bufinfo, sizeof(bufinfo), "Queue: %s %s",
2561 pipe_id_to_str[id],
2562 queue_id_to_str[frame->dynamic_queue_id]);
2563 }
2564 dtrace_dot(
2565 "node [shape = box, fixedsize=true, width=2, height=0.7]; \"%p\" [label = \"%s\\n%d(%d) x %d, %dbpp\\n%s\"];",
2566 frame,
2567 debug_frame_format2str(frame->frame_info.format),
2568 frame->frame_info.res.width,
2569 frame->frame_info.padded_width,
2570 frame->frame_info.res.height,
2571 frame->frame_info.raw_bit_depth,
2572 bufinfo);
2573
2574 if (in_frame) {
2575 dtrace_dot(
2576 "\"%p\"->\"%s(pipe%d)\" [label = %s_frame];",
2577 frame,
2578 blob_name, id, frame_name);
2579 } else {
2580 dtrace_dot(
2581 "\"%s(pipe%d)\"->\"%p\" [label = %s_frame];",
2582 blob_name, id,
2583 frame,
2584 frame_name);
2585 }
2586 }
2587
2588 void
ia_css_debug_pipe_graph_dump_prologue(void)2589 ia_css_debug_pipe_graph_dump_prologue(void)
2590 {
2591 dtrace_dot("digraph sh_css_pipe_graph {");
2592 dtrace_dot("rankdir=LR;");
2593
2594 dtrace_dot("fontsize=9;");
2595 dtrace_dot("label = \"\\nEnable options: rp=reduced pipe, vfve=vf_veceven, dvse=dvs_envelope, dvs6=dvs_6axis, bo=block_out, fbds=fixed_bayer_ds, bf6=bayer_fir_6db, rawb=raw_binning, cont=continuous, disc=dis_crop\\n"
2596 "dp2a=dp_2adjacent, outp=output, outt=out_table, reff=ref_frame, par=params, gam=gamma, cagdc=ca_gdc, ispa=isp_addresses, inf=in_frame, outf=out_frame, hs=high_speed, inpc=input_chunking\"");
2597 }
2598
ia_css_debug_pipe_graph_dump_epilogue(void)2599 void ia_css_debug_pipe_graph_dump_epilogue(void)
2600 {
2601 if (strlen(ring_buffer) > 0) {
2602 dtrace_dot(ring_buffer);
2603 }
2604
2605 if (pg_inst.stream_format != N_ATOMISP_INPUT_FORMAT) {
2606 /* An input stream format has been set so assume we have
2607 * an input system and sensor
2608 */
2609
2610 dtrace_dot(
2611 "node [shape = doublecircle, fixedsize=true, width=2.5]; \"input_system\" [label = \"Input system\"];");
2612
2613 dtrace_dot(
2614 "\"input_system\"->\"%s\" [label = \"%s\"];",
2615 dot_id_input_bin, debug_stream_format2str(pg_inst.stream_format));
2616
2617 dtrace_dot(
2618 "node [shape = doublecircle, fixedsize=true, width=2.5]; \"sensor\" [label = \"Sensor\"];");
2619
2620 dtrace_dot(
2621 "\"sensor\"->\"input_system\" [label = \"%s\\n%d x %d\\n(%d x %d)\"];",
2622 debug_stream_format2str(pg_inst.stream_format),
2623 pg_inst.width, pg_inst.height,
2624 pg_inst.eff_width, pg_inst.eff_height);
2625 }
2626
2627 dtrace_dot("}");
2628
2629 /* Reset temp strings */
2630 memset(dot_id_input_bin, 0, sizeof(dot_id_input_bin));
2631 memset(ring_buffer, 0, sizeof(ring_buffer));
2632
2633 pg_inst.do_init = true;
2634 pg_inst.width = 0;
2635 pg_inst.height = 0;
2636 pg_inst.eff_width = 0;
2637 pg_inst.eff_height = 0;
2638 pg_inst.stream_format = N_ATOMISP_INPUT_FORMAT;
2639 }
2640
2641 void
ia_css_debug_pipe_graph_dump_stage(struct ia_css_pipeline_stage * stage,enum ia_css_pipe_id id)2642 ia_css_debug_pipe_graph_dump_stage(
2643 struct ia_css_pipeline_stage *stage,
2644 enum ia_css_pipe_id id)
2645 {
2646 char blob_name[SH_CSS_MAX_BINARY_NAME + 10] = "<unknown type>";
2647 char const *bin_type = "<unknown type>";
2648 int i;
2649
2650 assert(stage);
2651 if (stage->sp_func != IA_CSS_PIPELINE_NO_FUNC)
2652 return;
2653
2654 if (pg_inst.do_init) {
2655 ia_css_debug_pipe_graph_dump_prologue();
2656 pg_inst.do_init = false;
2657 }
2658
2659 if (stage->binary) {
2660 bin_type = "binary";
2661 if (stage->binary->info->blob)
2662 snprintf(blob_name, sizeof(blob_name), "%s_stage%d",
2663 stage->binary->info->blob->name, stage->stage_num);
2664 } else if (stage->firmware) {
2665 bin_type = "firmware";
2666
2667 strscpy(blob_name, IA_CSS_EXT_ISP_PROG_NAME(stage->firmware),
2668 sizeof(blob_name));
2669 }
2670
2671 /* Guard in case of binaries that don't have any binary_info */
2672 if (stage->binary_info) {
2673 char enable_info1[100];
2674 char enable_info2[100];
2675 char enable_info3[100];
2676 char enable_info[200];
2677 struct ia_css_binary_info *bi = stage->binary_info;
2678
2679 /* Split it in 2 function-calls to keep the amount of
2680 * parameters per call "reasonable"
2681 */
2682 snprintf(enable_info1, sizeof(enable_info1),
2683 "%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
2684 bi->enable.reduced_pipe ? "rp," : "",
2685 bi->enable.vf_veceven ? "vfve," : "",
2686 bi->enable.dis ? "dis," : "",
2687 bi->enable.dvs_envelope ? "dvse," : "",
2688 bi->enable.uds ? "uds," : "",
2689 bi->enable.dvs_6axis ? "dvs6," : "",
2690 bi->enable.block_output ? "bo," : "",
2691 bi->enable.ds ? "ds," : "",
2692 bi->enable.bayer_fir_6db ? "bf6," : "",
2693 bi->enable.raw_binning ? "rawb," : "",
2694 bi->enable.continuous ? "cont," : "",
2695 bi->enable.s3a ? "s3a," : "",
2696 bi->enable.fpnr ? "fpnr," : "",
2697 bi->enable.sc ? "sc," : ""
2698 );
2699
2700 snprintf(enable_info2, sizeof(enable_info2),
2701 "%s%s%s%s%s%s%s%s%s%s%s",
2702 bi->enable.macc ? "macc," : "",
2703 bi->enable.output ? "outp," : "",
2704 bi->enable.ref_frame ? "reff," : "",
2705 bi->enable.tnr ? "tnr," : "",
2706 bi->enable.xnr ? "xnr," : "",
2707 bi->enable.params ? "par," : "",
2708 bi->enable.ca_gdc ? "cagdc," : "",
2709 bi->enable.isp_addresses ? "ispa," : "",
2710 bi->enable.in_frame ? "inf," : "",
2711 bi->enable.out_frame ? "outf," : "",
2712 bi->enable.high_speed ? "hs," : ""
2713 );
2714
2715 /* And merge them into one string */
2716 snprintf(enable_info, sizeof(enable_info), "%s%s",
2717 enable_info1, enable_info2);
2718 {
2719 int l, p;
2720 char *ei = enable_info;
2721
2722 l = strlen(ei);
2723
2724 /* Replace last ',' with \0 if present */
2725 if (l && enable_info[l - 1] == ',')
2726 enable_info[--l] = '\0';
2727
2728 if (l > ENABLE_LINE_MAX_LENGTH) {
2729 /* Too big for one line, find last comma */
2730 p = ENABLE_LINE_MAX_LENGTH;
2731 while (ei[p] != ',')
2732 p--;
2733 /* Last comma found, copy till that comma */
2734 strscpy(enable_info1, ei,
2735 p > sizeof(enable_info1) ? sizeof(enable_info1) : p);
2736
2737 ei += p + 1;
2738 l = strlen(ei);
2739
2740 if (l <= ENABLE_LINE_MAX_LENGTH) {
2741 /* The 2nd line fits */
2742 /* we cannot use ei as argument because
2743 * it is not guaranteed dword aligned
2744 */
2745
2746 strscpy(enable_info2, ei,
2747 l > sizeof(enable_info2) ? sizeof(enable_info2) : l);
2748
2749 snprintf(enable_info, sizeof(enable_info), "%s\\n%s",
2750 enable_info1, enable_info2);
2751
2752 } else {
2753 /* 2nd line is still too long */
2754 p = ENABLE_LINE_MAX_LENGTH;
2755 while (ei[p] != ',')
2756 p--;
2757
2758 strscpy(enable_info2, ei,
2759 p > sizeof(enable_info2) ? sizeof(enable_info2) : p);
2760
2761 ei += p + 1;
2762 l = strlen(ei);
2763
2764 if (l <= ENABLE_LINE_MAX_LENGTH) {
2765 /* The 3rd line fits */
2766 /* we cannot use ei as argument because
2767 * it is not guaranteed dword aligned
2768 */
2769 strscpy(enable_info3, ei,
2770 sizeof(enable_info3));
2771 snprintf(enable_info, sizeof(enable_info),
2772 "%s\\n%s\\n%s",
2773 enable_info1, enable_info2,
2774 enable_info3);
2775 } else {
2776 /* 3rd line is still too long */
2777 p = ENABLE_LINE_MAX_LENGTH;
2778 while (ei[p] != ',')
2779 p--;
2780 strscpy(enable_info3, ei,
2781 p > sizeof(enable_info3) ? sizeof(enable_info3) : p);
2782 ei += p + 1;
2783 strscpy(enable_info3, ei,
2784 sizeof(enable_info3));
2785 snprintf(enable_info, sizeof(enable_info),
2786 "%s\\n%s\\n%s",
2787 enable_info1, enable_info2,
2788 enable_info3);
2789 }
2790 }
2791 }
2792 }
2793
2794 dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, label=\"%s\\n%s\\n\\n%s\"]; \"%s(pipe%d)\"",
2795 bin_type, blob_name, enable_info, blob_name, id);
2796 } else {
2797 dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, label=\"%s\\n%s\\n\"]; \"%s(pipe%d)\"",
2798 bin_type, blob_name, blob_name, id);
2799 }
2800
2801 if (stage->stage_num == 0) {
2802 /*
2803 * There are some implicite assumptions about which bin is the
2804 * input binary e.g. which one is connected to the input system
2805 * Priority:
2806 * 1) sp_raw_copy bin has highest priority
2807 * 2) First stage==0 binary of preview, video or capture
2808 */
2809 if (strlen(dot_id_input_bin) == 0) {
2810 snprintf(dot_id_input_bin, sizeof(dot_id_input_bin),
2811 "%s(pipe%d)", blob_name, id);
2812 }
2813 }
2814
2815 if (stage->args.in_frame) {
2816 ia_css_debug_pipe_graph_dump_frame(
2817 stage->args.in_frame, id, blob_name,
2818 "in", true);
2819 }
2820
2821 for (i = 0; i < NUM_VIDEO_TNR_FRAMES; i++) {
2822 if (stage->args.tnr_frames[i]) {
2823 ia_css_debug_pipe_graph_dump_frame(
2824 stage->args.tnr_frames[i], id,
2825 blob_name, "tnr_frame", true);
2826 }
2827 }
2828
2829 for (i = 0; i < MAX_NUM_VIDEO_DELAY_FRAMES; i++) {
2830 if (stage->args.delay_frames[i]) {
2831 ia_css_debug_pipe_graph_dump_frame(
2832 stage->args.delay_frames[i], id,
2833 blob_name, "delay_frame", true);
2834 }
2835 }
2836
2837 for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) {
2838 if (stage->args.out_frame[i]) {
2839 ia_css_debug_pipe_graph_dump_frame(
2840 stage->args.out_frame[i], id, blob_name,
2841 "out", false);
2842 }
2843 }
2844
2845 if (stage->args.out_vf_frame) {
2846 ia_css_debug_pipe_graph_dump_frame(
2847 stage->args.out_vf_frame, id, blob_name,
2848 "out_vf", false);
2849 }
2850 }
2851
2852 void
ia_css_debug_pipe_graph_dump_sp_raw_copy(struct ia_css_frame * out_frame)2853 ia_css_debug_pipe_graph_dump_sp_raw_copy(
2854 struct ia_css_frame *out_frame)
2855 {
2856 assert(out_frame);
2857 if (pg_inst.do_init) {
2858 ia_css_debug_pipe_graph_dump_prologue();
2859 pg_inst.do_init = false;
2860 }
2861
2862 dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, label=\"%s\\n%s\"]; \"%s(pipe%d)\"",
2863 "sp-binary", "sp_raw_copy", "sp_raw_copy", 1);
2864
2865 snprintf(ring_buffer, sizeof(ring_buffer),
2866 "node [shape = box, fixedsize=true, width=2, height=0.7]; \"%p\" [label = \"%s\\n%d(%d) x %d\\nRingbuffer\"];",
2867 out_frame,
2868 debug_frame_format2str(out_frame->frame_info.format),
2869 out_frame->frame_info.res.width,
2870 out_frame->frame_info.padded_width,
2871 out_frame->frame_info.res.height);
2872
2873 dtrace_dot(ring_buffer);
2874
2875 dtrace_dot(
2876 "\"%s(pipe%d)\"->\"%p\" [label = out_frame];",
2877 "sp_raw_copy", 1, out_frame);
2878
2879 snprintf(dot_id_input_bin, sizeof(dot_id_input_bin), "%s(pipe%d)",
2880 "sp_raw_copy", 1);
2881 }
2882
2883 void
ia_css_debug_pipe_graph_dump_stream_config(const struct ia_css_stream_config * stream_config)2884 ia_css_debug_pipe_graph_dump_stream_config(
2885 const struct ia_css_stream_config *stream_config)
2886 {
2887 pg_inst.width = stream_config->input_config.input_res.width;
2888 pg_inst.height = stream_config->input_config.input_res.height;
2889 pg_inst.eff_width = stream_config->input_config.effective_res.width;
2890 pg_inst.eff_height = stream_config->input_config.effective_res.height;
2891 pg_inst.stream_format = stream_config->input_config.format;
2892 }
2893
2894 void
ia_css_debug_dump_resolution(const struct ia_css_resolution * res,const char * label)2895 ia_css_debug_dump_resolution(
2896 const struct ia_css_resolution *res,
2897 const char *label)
2898 {
2899 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s: =%d x =%d\n",
2900 label, res->width, res->height);
2901 }
2902
2903 void
ia_css_debug_dump_frame_info(const struct ia_css_frame_info * info,const char * label)2904 ia_css_debug_dump_frame_info(
2905 const struct ia_css_frame_info *info,
2906 const char *label)
2907 {
2908 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s\n", label);
2909 ia_css_debug_dump_resolution(&info->res, "res");
2910 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "padded_width: %d\n",
2911 info->padded_width);
2912 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "format: %d\n", info->format);
2913 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "raw_bit_depth: %d\n",
2914 info->raw_bit_depth);
2915 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "raw_bayer_order: %d\n",
2916 info->raw_bayer_order);
2917 }
2918
2919 void
ia_css_debug_dump_capture_config(const struct ia_css_capture_config * config)2920 ia_css_debug_dump_capture_config(
2921 const struct ia_css_capture_config *config)
2922 {
2923 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s\n", __func__);
2924 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", config->mode);
2925 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_xnr: %d\n",
2926 config->enable_xnr);
2927 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_raw_output: %d\n",
2928 config->enable_raw_output);
2929 }
2930
2931 void
ia_css_debug_dump_pipe_extra_config(const struct ia_css_pipe_extra_config * extra_config)2932 ia_css_debug_dump_pipe_extra_config(
2933 const struct ia_css_pipe_extra_config *extra_config)
2934 {
2935 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s\n", __func__);
2936 if (extra_config) {
2937 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
2938 "enable_raw_binning: %d\n",
2939 extra_config->enable_raw_binning);
2940 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_yuv_ds: %d\n",
2941 extra_config->enable_yuv_ds);
2942 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
2943 "enable_high_speed: %d\n",
2944 extra_config->enable_high_speed);
2945 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
2946 "enable_dvs_6axis: %d\n",
2947 extra_config->enable_dvs_6axis);
2948 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
2949 "enable_reduced_pipe: %d\n",
2950 extra_config->enable_reduced_pipe);
2951 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
2952 "enable_fractional_ds: %d\n",
2953 extra_config->enable_fractional_ds);
2954 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "disable_vf_pp: %d\n",
2955 extra_config->disable_vf_pp);
2956 }
2957 }
2958
2959 void
ia_css_debug_dump_pipe_config(const struct ia_css_pipe_config * config)2960 ia_css_debug_dump_pipe_config(
2961 const struct ia_css_pipe_config *config)
2962 {
2963 unsigned int i;
2964
2965 IA_CSS_ENTER_PRIVATE("config = %p", config);
2966 if (!config) {
2967 IA_CSS_ERROR("NULL input parameter");
2968 IA_CSS_LEAVE_PRIVATE("");
2969 return;
2970 }
2971 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", config->mode);
2972 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "isp_pipe_version: %d\n",
2973 config->isp_pipe_version);
2974 ia_css_debug_dump_resolution(&config->bayer_ds_out_res,
2975 "bayer_ds_out_res");
2976 ia_css_debug_dump_resolution(&config->capt_pp_in_res,
2977 "capt_pp_in_res");
2978 ia_css_debug_dump_resolution(&config->vf_pp_in_res, "vf_pp_in_res");
2979
2980 if (IS_ISP2401) {
2981 ia_css_debug_dump_resolution(&config->output_system_in_res,
2982 "output_system_in_res");
2983 }
2984 ia_css_debug_dump_resolution(&config->dvs_crop_out_res,
2985 "dvs_crop_out_res");
2986 for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) {
2987 ia_css_debug_dump_frame_info(&config->output_info[i], "output_info");
2988 ia_css_debug_dump_frame_info(&config->vf_output_info[i],
2989 "vf_output_info");
2990 }
2991 ia_css_debug_dump_capture_config(&config->default_capture_config);
2992 ia_css_debug_dump_resolution(&config->dvs_envelope, "dvs_envelope");
2993 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "dvs_frame_delay: %d\n",
2994 config->dvs_frame_delay);
2995 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_dz: %d\n",
2996 config->enable_dz);
2997 IA_CSS_LEAVE_PRIVATE("");
2998 }
2999
3000 void
ia_css_debug_dump_stream_config_source(const struct ia_css_stream_config * config)3001 ia_css_debug_dump_stream_config_source(
3002 const struct ia_css_stream_config *config)
3003 {
3004 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__);
3005 switch (config->mode) {
3006 case IA_CSS_INPUT_MODE_SENSOR:
3007 case IA_CSS_INPUT_MODE_BUFFERED_SENSOR:
3008 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "source.port\n");
3009 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "port: %d\n",
3010 config->source.port.port);
3011 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "num_lanes: %d\n",
3012 config->source.port.num_lanes);
3013 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "timeout: %d\n",
3014 config->source.port.timeout);
3015 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "compression: %d\n",
3016 config->source.port.compression.type);
3017 break;
3018 case IA_CSS_INPUT_MODE_TPG:
3019 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "source.tpg\n");
3020 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "id: %d\n",
3021 config->source.tpg.id);
3022 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n",
3023 config->source.tpg.mode);
3024 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "x_mask: 0x%x\n",
3025 config->source.tpg.x_mask);
3026 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "x_delta: %d\n",
3027 config->source.tpg.x_delta);
3028 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "y_mask: 0x%x\n",
3029 config->source.tpg.y_mask);
3030 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "y_delta: %d\n",
3031 config->source.tpg.y_delta);
3032 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "xy_mask: 0x%x\n",
3033 config->source.tpg.xy_mask);
3034 break;
3035 case IA_CSS_INPUT_MODE_PRBS:
3036 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "source.prbs\n");
3037 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "id: %d\n",
3038 config->source.prbs.id);
3039 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "h_blank: %d\n",
3040 config->source.prbs.h_blank);
3041 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "v_blank: %d\n",
3042 config->source.prbs.v_blank);
3043 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "seed: 0x%x\n",
3044 config->source.prbs.seed);
3045 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "seed1: 0x%x\n",
3046 config->source.prbs.seed1);
3047 break;
3048 default:
3049 case IA_CSS_INPUT_MODE_FIFO:
3050 case IA_CSS_INPUT_MODE_MEMORY:
3051 break;
3052 }
3053 }
3054
3055 void
ia_css_debug_dump_mipi_buffer_config(const struct ia_css_mipi_buffer_config * config)3056 ia_css_debug_dump_mipi_buffer_config(
3057 const struct ia_css_mipi_buffer_config *config)
3058 {
3059 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__);
3060 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "size_mem_words: %d\n",
3061 config->size_mem_words);
3062 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "nof_mipi_buffers: %d\n",
3063 config->nof_mipi_buffers);
3064 }
3065
3066 void
ia_css_debug_dump_metadata_config(const struct ia_css_metadata_config * config)3067 ia_css_debug_dump_metadata_config(
3068 const struct ia_css_metadata_config *config)
3069 {
3070 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__);
3071 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "data_type: %d\n",
3072 config->data_type);
3073 ia_css_debug_dump_resolution(&config->resolution, "resolution");
3074 }
3075
3076 void
ia_css_debug_dump_stream_config(const struct ia_css_stream_config * config,int num_pipes)3077 ia_css_debug_dump_stream_config(
3078 const struct ia_css_stream_config *config,
3079 int num_pipes)
3080 {
3081 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__);
3082 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "num_pipes: %d\n", num_pipes);
3083 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", config->mode);
3084 ia_css_debug_dump_stream_config_source(config);
3085 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "channel_id: %d\n",
3086 config->channel_id);
3087 ia_css_debug_dump_resolution(&config->input_config.input_res, "input_res");
3088 ia_css_debug_dump_resolution(&config->input_config.effective_res,
3089 "effective_res");
3090 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "format: %d\n",
3091 config->input_config.format);
3092 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "bayer_order: %d\n",
3093 config->input_config.bayer_order);
3094 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sensor_binning_factor: %d\n",
3095 config->sensor_binning_factor);
3096 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "pixels_per_clock: %d\n",
3097 config->pixels_per_clock);
3098 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "online: %d\n",
3099 config->online);
3100 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "init_num_cont_raw_buf: %d\n",
3101 config->init_num_cont_raw_buf);
3102 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
3103 "target_num_cont_raw_buf: %d\n",
3104 config->target_num_cont_raw_buf);
3105 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "pack_raw_pixels: %d\n",
3106 config->pack_raw_pixels);
3107 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "continuous: %d\n",
3108 config->continuous);
3109 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "flash_gpio_pin: %d\n",
3110 config->flash_gpio_pin);
3111 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "left_padding: %d\n",
3112 config->left_padding);
3113 ia_css_debug_dump_mipi_buffer_config(&config->mipi_buffer_config);
3114 ia_css_debug_dump_metadata_config(&config->metadata_config);
3115 }
3116
3117 /*
3118 Trace support.
3119
3120 This tracer is using a buffer to trace the flow of the FW and dump misc values (see below for details).
3121 Currently, support is only for SKC.
3122 To enable support for other platforms:
3123 - Allocate a buffer for tracing in DMEM. The longer the better.
3124 - Use the DBG_init routine in sp.hive.c to initiatilize the tracer with the address and size selected.
3125 - Add trace points in the SP code wherever needed.
3126 - Enable the dump below with the required address and required adjustments.
3127 Dump is called at the end of ia_css_debug_dump_sp_state().
3128 */
3129
3130 /*
3131 dump_trace() : dump the trace points from DMEM2.
3132 for every trace point, the following are printed: index, major:minor and the 16-bit attached value.
3133 The routine looks for the first 0, and then prints from it cyclically.
3134 Data forma in DMEM2:
3135 first 4 DWORDS: header
3136 DWORD 0: data description
3137 byte 0: version
3138 byte 1: number of threads (for future use)
3139 byte 2+3: number ot TPs
3140 DWORD 1: command byte + data (for future use)
3141 byte 0: command
3142 byte 1-3: command signature
3143 DWORD 2-3: additional data (for future use)
3144 Following data is 4-byte oriented:
3145 byte 0: major
3146 byte 1: minor
3147 byte 2-3: data
3148 */
3149 #if TRACE_ENABLE_SP0 || TRACE_ENABLE_SP1 || TRACE_ENABLE_ISP
debug_dump_one_trace(enum TRACE_CORE_ID proc_id)3150 static void debug_dump_one_trace(enum TRACE_CORE_ID proc_id)
3151 {
3152 #if defined(HAS_TRACER_V2)
3153 u32 start_addr;
3154 u32 start_addr_data;
3155 u32 item_size;
3156 u32 tmp;
3157 u8 tid_val;
3158 enum TRACE_DUMP_FORMAT dump_format;
3159
3160 int i, j, max_trace_points, point_num, limit = -1;
3161 /* using a static buffer here as the driver has issues allocating memory */
3162 static u32 trace_read_buf[TRACE_BUFF_SIZE] = {0};
3163 static struct trace_header_t header;
3164 u8 *header_arr;
3165
3166 /* read the header and parse it */
3167 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "~~~ Tracer ");
3168 switch (proc_id) {
3169 case TRACE_SP0_ID:
3170 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP0");
3171 start_addr = TRACE_SP0_ADDR;
3172 start_addr_data = TRACE_SP0_DATA_ADDR;
3173 item_size = TRACE_SP0_ITEM_SIZE;
3174 max_trace_points = TRACE_SP0_MAX_POINTS;
3175 break;
3176 case TRACE_SP1_ID:
3177 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP1");
3178 start_addr = TRACE_SP1_ADDR;
3179 start_addr_data = TRACE_SP1_DATA_ADDR;
3180 item_size = TRACE_SP1_ITEM_SIZE;
3181 max_trace_points = TRACE_SP1_MAX_POINTS;
3182 break;
3183 case TRACE_ISP_ID:
3184 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ISP");
3185 start_addr = TRACE_ISP_ADDR;
3186 start_addr_data = TRACE_ISP_DATA_ADDR;
3187 item_size = TRACE_ISP_ITEM_SIZE;
3188 max_trace_points = TRACE_ISP_MAX_POINTS;
3189 break;
3190 default:
3191 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
3192 "\t\ttraces are not supported for this processor ID - exiting\n");
3193 return;
3194 }
3195
3196 if (!IS_ISP2401) {
3197 tmp = ia_css_device_load_uint32(start_addr);
3198 point_num = (tmp >> 16) & 0xFFFF;
3199
3200 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, " ver %d %d points\n", tmp & 0xFF,
3201 point_num);
3202 } else {
3203 /* Loading byte-by-byte as using the master routine had issues */
3204 header_arr = (uint8_t *)&header;
3205 for (i = 0; i < (int)sizeof(struct trace_header_t); i++)
3206 header_arr[i] = ia_css_device_load_uint8(start_addr + (i));
3207
3208 point_num = header.max_tracer_points;
3209
3210 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, " ver %d %d points\n", header.version,
3211 point_num);
3212
3213 tmp = header.version;
3214 }
3215 if ((tmp & 0xFF) != TRACER_VER) {
3216 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\tUnknown version - exiting\n");
3217 return;
3218 }
3219 if (point_num > max_trace_points) {
3220 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\tToo many points - exiting\n");
3221 return;
3222 }
3223 /* copy the TPs and find the first 0 */
3224 for (i = 0; i < point_num; i++) {
3225 trace_read_buf[i] = ia_css_device_load_uint32(start_addr_data +
3226 (i * item_size));
3227 if ((limit == (-1)) && (trace_read_buf[i] == 0))
3228 limit = i;
3229 }
3230 if (IS_ISP2401) {
3231 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "Status:\n");
3232 for (i = 0; i < SH_CSS_MAX_SP_THREADS; i++)
3233 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
3234 "\tT%d: %3d (%02x) %6d (%04x) %10d (%08x)\n", i,
3235 header.thr_status_byte[i], header.thr_status_byte[i],
3236 header.thr_status_word[i], header.thr_status_word[i],
3237 header.thr_status_dword[i], header.thr_status_dword[i]);
3238 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "Scratch:\n");
3239 for (i = 0; i < MAX_SCRATCH_DATA; i++)
3240 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%10d (%08x) ",
3241 header.scratch_debug[i], header.scratch_debug[i]);
3242 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\n");
3243 }
3244 /* two 0s in the beginning: empty buffer */
3245 if ((trace_read_buf[0] == 0) && (trace_read_buf[1] == 0)) {
3246 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\tEmpty tracer - exiting\n");
3247 return;
3248 }
3249 /* no overrun: start from 0 */
3250 if ((limit == point_num - 1) ||
3251 /* first 0 is at the end - border case */
3252 (trace_read_buf[limit + 1] ==
3253 0)) /* did not make a full cycle after the memset */
3254 limit = 0;
3255 /* overrun: limit is the first non-zero after the first zero */
3256 else
3257 limit++;
3258
3259 /* print the TPs */
3260 for (i = 0; i < point_num; i++) {
3261 j = (limit + i) % point_num;
3262 if (trace_read_buf[j]) {
3263 if (!IS_ISP2401) {
3264 TRACE_DUMP_FORMAT dump_format = FIELD_FORMAT_UNPACK(trace_read_buf[j]);
3265 } else {
3266 tid_val = FIELD_TID_UNPACK(trace_read_buf[j]);
3267 dump_format = TRACE_DUMP_FORMAT_POINT;
3268
3269 /*
3270 * When tid value is 111b, the data will be interpreted differently:
3271 * tid val is ignored, major field contains 2 bits (msb) for format type
3272 */
3273 if (tid_val == FIELD_TID_SEL_FORMAT_PAT) {
3274 dump_format = FIELD_FORMAT_UNPACK(trace_read_buf[j]);
3275 }
3276 }
3277 switch (dump_format) {
3278 case TRACE_DUMP_FORMAT_POINT:
3279 ia_css_debug_dtrace(
3280 IA_CSS_DEBUG_TRACE, "\t\t%d %d:%d value - %d\n",
3281 j, FIELD_MAJOR_UNPACK(trace_read_buf[j]),
3282 FIELD_MINOR_UNPACK(trace_read_buf[j]),
3283 FIELD_VALUE_UNPACK(trace_read_buf[j]));
3284 break;
3285 /* ISP2400 */
3286 case TRACE_DUMP_FORMAT_VALUE24_HEX:
3287 ia_css_debug_dtrace(
3288 IA_CSS_DEBUG_TRACE, "\t\t%d, %d, 24bit value %x H\n",
3289 j,
3290 FIELD_MAJOR_UNPACK(trace_read_buf[j]),
3291 FIELD_VALUE_24_UNPACK(trace_read_buf[j]));
3292 break;
3293 /* ISP2400 */
3294 case TRACE_DUMP_FORMAT_VALUE24_DEC:
3295 ia_css_debug_dtrace(
3296 IA_CSS_DEBUG_TRACE, "\t\t%d, %d, 24bit value %d D\n",
3297 j,
3298 FIELD_MAJOR_UNPACK(trace_read_buf[j]),
3299 FIELD_VALUE_24_UNPACK(trace_read_buf[j]));
3300 break;
3301 /* ISP2401 */
3302 case TRACE_DUMP_FORMAT_POINT_NO_TID:
3303 ia_css_debug_dtrace(
3304 IA_CSS_DEBUG_TRACE, "\t\t%d %d:%d value - %x (%d)\n",
3305 j,
3306 FIELD_MAJOR_W_FMT_UNPACK(trace_read_buf[j]),
3307 FIELD_MINOR_UNPACK(trace_read_buf[j]),
3308 FIELD_VALUE_UNPACK(trace_read_buf[j]),
3309 FIELD_VALUE_UNPACK(trace_read_buf[j]));
3310 break;
3311 /* ISP2401 */
3312 case TRACE_DUMP_FORMAT_VALUE24:
3313 ia_css_debug_dtrace(
3314 IA_CSS_DEBUG_TRACE, "\t\t%d, %d, 24bit value %x (%d)\n",
3315 j,
3316 FIELD_MAJOR_UNPACK(trace_read_buf[j]),
3317 FIELD_MAJOR_W_FMT_UNPACK(trace_read_buf[j]),
3318 FIELD_VALUE_24_UNPACK(trace_read_buf[j]),
3319 FIELD_VALUE_24_UNPACK(trace_read_buf[j]));
3320 break;
3321 case TRACE_DUMP_FORMAT_VALUE24_TIMING:
3322 ia_css_debug_dtrace(
3323 IA_CSS_DEBUG_TRACE, "\t\t%d, %d, timing %x\n",
3324 j,
3325 FIELD_MAJOR_UNPACK(trace_read_buf[j]),
3326 FIELD_VALUE_24_UNPACK(trace_read_buf[j]));
3327 break;
3328 case TRACE_DUMP_FORMAT_VALUE24_TIMING_DELTA:
3329 ia_css_debug_dtrace(
3330 IA_CSS_DEBUG_TRACE, "\t\t%d, %d, timing delta %x\n",
3331 j,
3332 FIELD_MAJOR_UNPACK(trace_read_buf[j]),
3333 FIELD_VALUE_24_UNPACK(trace_read_buf[j]));
3334 break;
3335 default:
3336 ia_css_debug_dtrace(
3337 IA_CSS_DEBUG_TRACE,
3338 "no such trace dump format %d",
3339 dump_format);
3340 break;
3341 }
3342 }
3343 }
3344 #else
3345 (void)proc_id;
3346 #endif /* HAS_TRACER_V2 */
3347 }
3348 #endif /* TRACE_ENABLE_SP0 || TRACE_ENABLE_SP1 || TRACE_ENABLE_ISP */
3349
ia_css_debug_dump_trace(void)3350 void ia_css_debug_dump_trace(void)
3351 {
3352 #if TRACE_ENABLE_SP0
3353 debug_dump_one_trace(TRACE_SP0_ID);
3354 #endif
3355 #if TRACE_ENABLE_SP1
3356 debug_dump_one_trace(TRACE_SP1_ID);
3357 #endif
3358 #if TRACE_ENABLE_ISP
3359 debug_dump_one_trace(TRACE_ISP_ID);
3360 #endif
3361 }
3362
3363 /* Tagger state dump function. The tagger is only available when the CSS
3364 * contains an input system (2400 or 2401). */
ia_css_debug_tagger_state(void)3365 void ia_css_debug_tagger_state(void)
3366 {
3367 unsigned int i;
3368 unsigned int HIVE_ADDR_tagger_frames;
3369 ia_css_tagger_buf_sp_elem_t tbuf_frames[MAX_CB_ELEMS_FOR_TAGGER];
3370
3371 HIVE_ADDR_tagger_frames = sh_css_sp_fw.info.sp.tagger_frames_addr;
3372
3373 /* This variable is not used in crun */
3374 (void)HIVE_ADDR_tagger_frames;
3375
3376 /* 2400 and 2401 only have 1 SP, so the tagger lives on SP0 */
3377 sp_dmem_load(SP0_ID,
3378 (unsigned int)sp_address_of(tagger_frames),
3379 tbuf_frames,
3380 sizeof(tbuf_frames));
3381
3382 ia_css_debug_dtrace(2, "Tagger Info:\n");
3383 for (i = 0; i < MAX_CB_ELEMS_FOR_TAGGER; i++) {
3384 ia_css_debug_dtrace(2, "\t tagger frame[%d]: exp_id=%d, marked=%d, locked=%d\n",
3385 i, tbuf_frames[i].exp_id, tbuf_frames[i].mark, tbuf_frames[i].lock);
3386 }
3387 }
3388
3389 /* ISP2401 */
ia_css_debug_pc_dump(sp_ID_t id,unsigned int num_of_dumps)3390 void ia_css_debug_pc_dump(sp_ID_t id, unsigned int num_of_dumps)
3391 {
3392 unsigned int pc;
3393 unsigned int i;
3394 hrt_data sc = sp_ctrl_load(id, SP_SC_REG);
3395
3396 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d Status reg: 0x%X\n", id, sc);
3397 sc = sp_ctrl_load(id, SP_CTRL_SINK_REG);
3398 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d Stall reg: 0x%X\n", id, sc);
3399 for (i = 0; i < num_of_dumps; i++) {
3400 pc = sp_ctrl_load(id, SP_PC_REG);
3401 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d PC: 0x%X\n", id, pc);
3402 }
3403 }
3404