1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef DRIVERS_PCI_H
3 #define DRIVERS_PCI_H
4
5 #include <linux/pci.h>
6 #include <linux/android_kabi.h>
7
8 /* Number of possible devfns: 0.0 to 1f.7 inclusive */
9 #define MAX_NR_DEVFNS 256
10
11 #define PCI_FIND_CAP_TTL 48
12
13 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
14
15 #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000
16
17 /*
18 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
19 * Recommends 1ms to 10ms timeout to check L2 ready.
20 */
21 #define PCIE_PME_TO_L2_TIMEOUT_US 10000
22
23 extern const unsigned char pcie_link_speed[];
24 extern bool pci_early_dump;
25
26 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
27 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev);
28 bool pcie_cap_has_rtctl(const struct pci_dev *dev);
29
30 /* Functions internal to the PCI core code */
31
32 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
33 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
34 void pci_cleanup_rom(struct pci_dev *dev);
35 #ifdef CONFIG_DMI
36 extern const struct attribute_group pci_dev_smbios_attr_group;
37 #endif
38
39 enum pci_mmap_api {
40 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
41 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
42 };
43 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
44 enum pci_mmap_api mmap_api);
45
46 bool pci_reset_supported(struct pci_dev *dev);
47 void pci_init_reset_methods(struct pci_dev *dev);
48 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
49 int pci_bus_error_reset(struct pci_dev *dev);
50
51 struct pci_cap_saved_data {
52 u16 cap_nr;
53 bool cap_extended;
54 unsigned int size;
55 u32 data[];
56 };
57
58 struct pci_cap_saved_state {
59 struct hlist_node next;
60 struct pci_cap_saved_data cap;
61 };
62
63 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
64 void pci_free_cap_save_buffers(struct pci_dev *dev);
65 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
66 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
67 u16 cap, unsigned int size);
68 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
69 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
70 u16 cap);
71
72 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
73 #define PCI_PM_D3HOT_WAIT 10 /* msec */
74 #define PCI_PM_D3COLD_WAIT 100 /* msec */
75
76 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
77 void pci_refresh_power_state(struct pci_dev *dev);
78 int pci_power_up(struct pci_dev *dev);
79 void pci_disable_enabled_device(struct pci_dev *dev);
80 int pci_finish_runtime_suspend(struct pci_dev *dev);
81 void pcie_clear_device_status(struct pci_dev *dev);
82 void pcie_clear_root_pme_status(struct pci_dev *dev);
83 bool pci_check_pme_status(struct pci_dev *dev);
84 void pci_pme_wakeup_bus(struct pci_bus *bus);
85 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
86 void pci_pme_restore(struct pci_dev *dev);
87 bool pci_dev_need_resume(struct pci_dev *dev);
88 void pci_dev_adjust_pme(struct pci_dev *dev);
89 void pci_dev_complete_resume(struct pci_dev *pci_dev);
90 void pci_config_pm_runtime_get(struct pci_dev *dev);
91 void pci_config_pm_runtime_put(struct pci_dev *dev);
92 void pci_pm_init(struct pci_dev *dev);
93 void pci_ea_init(struct pci_dev *dev);
94 void pci_msi_init(struct pci_dev *dev);
95 void pci_msix_init(struct pci_dev *dev);
96 bool pci_bridge_d3_possible(struct pci_dev *dev);
97 void pci_bridge_d3_update(struct pci_dev *dev);
98 void pci_bridge_reconfigure_ltr(struct pci_dev *dev);
99 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type);
100
pci_wakeup_event(struct pci_dev * dev)101 static inline void pci_wakeup_event(struct pci_dev *dev)
102 {
103 /* Wait 100 ms before the system can be put into a sleep state. */
104 pm_wakeup_event(&dev->dev, 100);
105 }
106
pci_has_subordinate(struct pci_dev * pci_dev)107 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
108 {
109 return !!(pci_dev->subordinate);
110 }
111
pci_power_manageable(struct pci_dev * pci_dev)112 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
113 {
114 /*
115 * Currently we allow normal PCI devices and PCI bridges transition
116 * into D3 if their bridge_d3 is set.
117 */
118 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
119 }
120
pcie_downstream_port(const struct pci_dev * dev)121 static inline bool pcie_downstream_port(const struct pci_dev *dev)
122 {
123 int type = pci_pcie_type(dev);
124
125 return type == PCI_EXP_TYPE_ROOT_PORT ||
126 type == PCI_EXP_TYPE_DOWNSTREAM ||
127 type == PCI_EXP_TYPE_PCIE_BRIDGE;
128 }
129
130 void pci_vpd_init(struct pci_dev *dev);
131 void pci_vpd_release(struct pci_dev *dev);
132 extern const struct attribute_group pci_dev_vpd_attr_group;
133
134 /* PCI Virtual Channel */
135 int pci_save_vc_state(struct pci_dev *dev);
136 void pci_restore_vc_state(struct pci_dev *dev);
137 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
138
139 /* PCI /proc functions */
140 #ifdef CONFIG_PROC_FS
141 int pci_proc_attach_device(struct pci_dev *dev);
142 int pci_proc_detach_device(struct pci_dev *dev);
143 int pci_proc_detach_bus(struct pci_bus *bus);
144 #else
pci_proc_attach_device(struct pci_dev * dev)145 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
pci_proc_detach_device(struct pci_dev * dev)146 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
pci_proc_detach_bus(struct pci_bus * bus)147 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
148 #endif
149
150 /* Functions for PCI Hotplug drivers to use */
151 int pci_hp_add_bridge(struct pci_dev *dev);
152
153 #ifdef HAVE_PCI_LEGACY
154 void pci_create_legacy_files(struct pci_bus *bus);
155 void pci_remove_legacy_files(struct pci_bus *bus);
156 #else
pci_create_legacy_files(struct pci_bus * bus)157 static inline void pci_create_legacy_files(struct pci_bus *bus) { }
pci_remove_legacy_files(struct pci_bus * bus)158 static inline void pci_remove_legacy_files(struct pci_bus *bus) { }
159 #endif
160
161 /* Lock for read/write access to pci device and bus lists */
162 extern struct rw_semaphore pci_bus_sem;
163 extern struct mutex pci_slot_mutex;
164
165 extern raw_spinlock_t pci_lock;
166
167 extern unsigned int pci_pm_d3hot_delay;
168
169 #ifdef CONFIG_PCI_MSI
170 void pci_no_msi(void);
171 #else
pci_no_msi(void)172 static inline void pci_no_msi(void) { }
173 #endif
174
175 void pci_realloc_get_opt(char *);
176
pci_no_d1d2(struct pci_dev * dev)177 static inline int pci_no_d1d2(struct pci_dev *dev)
178 {
179 unsigned int parent_dstates = 0;
180
181 if (dev->bus->self)
182 parent_dstates = dev->bus->self->no_d1d2;
183 return (dev->no_d1d2 || parent_dstates);
184
185 }
186 extern const struct attribute_group *pci_dev_groups[];
187 extern const struct attribute_group *pcibus_groups[];
188 extern const struct device_type pci_dev_type;
189 extern const struct attribute_group *pci_bus_groups[];
190
191 extern unsigned long pci_hotplug_io_size;
192 extern unsigned long pci_hotplug_mmio_size;
193 extern unsigned long pci_hotplug_mmio_pref_size;
194 extern unsigned long pci_hotplug_bus_size;
195
196 /**
197 * pci_match_one_device - Tell if a PCI device structure has a matching
198 * PCI device id structure
199 * @id: single PCI device id structure to match
200 * @dev: the PCI device structure to match against
201 *
202 * Returns the matching pci_device_id structure or %NULL if there is no match.
203 */
204 static inline const struct pci_device_id *
pci_match_one_device(const struct pci_device_id * id,const struct pci_dev * dev)205 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
206 {
207 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
208 (id->device == PCI_ANY_ID || id->device == dev->device) &&
209 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
210 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
211 !((id->class ^ dev->class) & id->class_mask))
212 return id;
213 return NULL;
214 }
215
216 /* PCI slot sysfs helper code */
217 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
218
219 extern struct kset *pci_slots_kset;
220
221 struct pci_slot_attribute {
222 struct attribute attr;
223 ssize_t (*show)(struct pci_slot *, char *);
224 ssize_t (*store)(struct pci_slot *, const char *, size_t);
225 };
226 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
227
228 enum pci_bar_type {
229 pci_bar_unknown, /* Standard PCI BAR probe */
230 pci_bar_io, /* An I/O port BAR */
231 pci_bar_mem32, /* A 32-bit memory BAR */
232 pci_bar_mem64, /* A 64-bit memory BAR */
233 };
234
235 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
236 void pci_put_host_bridge_device(struct device *dev);
237
238 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
239 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
240 int crs_timeout);
241 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
242 int crs_timeout);
243 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
244
245 int pci_setup_device(struct pci_dev *dev);
246 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
247 struct resource *res, unsigned int reg);
248 void pci_configure_ari(struct pci_dev *dev);
249 void __pci_bus_size_bridges(struct pci_bus *bus,
250 struct list_head *realloc_head);
251 void __pci_bus_assign_resources(const struct pci_bus *bus,
252 struct list_head *realloc_head,
253 struct list_head *fail_head);
254 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
255
256 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
257 void pci_disable_bridge_window(struct pci_dev *dev);
258 struct pci_bus *pci_bus_get(struct pci_bus *bus);
259 void pci_bus_put(struct pci_bus *bus);
260
261 /* PCIe link information from Link Capabilities 2 */
262 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
263 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
264 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
265 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
266 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
267 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
268 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
269 PCI_SPEED_UNKNOWN)
270
271 /* PCIe speed to Mb/s reduced by encoding overhead */
272 #define PCIE_SPEED2MBS_ENC(speed) \
273 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \
274 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
275 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
276 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
277 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
278 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
279 0)
280
281 const char *pci_speed_string(enum pci_bus_speed speed);
282 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
283 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
284 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
285 enum pcie_link_width *width);
286 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
287 void pcie_report_downtraining(struct pci_dev *dev);
288 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
289
290 /* Single Root I/O Virtualization */
291 struct pci_sriov {
292 int pos; /* Capability position */
293 int nres; /* Number of resources */
294 u32 cap; /* SR-IOV Capabilities */
295 u16 ctrl; /* SR-IOV Control */
296 u16 total_VFs; /* Total VFs associated with the PF */
297 u16 initial_VFs; /* Initial VFs associated with the PF */
298 u16 num_VFs; /* Number of VFs available */
299 u16 offset; /* First VF Routing ID offset */
300 u16 stride; /* Following VF stride */
301 u16 vf_device; /* VF device ID */
302 u32 pgsz; /* Page size for BAR alignment */
303 u8 link; /* Function Dependency Link */
304 u8 max_VF_buses; /* Max buses consumed by VFs */
305 u16 driver_max_VFs; /* Max num VFs driver supports */
306 struct pci_dev *dev; /* Lowest numbered PF */
307 struct pci_dev *self; /* This PF */
308 u32 class; /* VF device */
309 u8 hdr_type; /* VF header type */
310 u16 subsystem_vendor; /* VF subsystem vendor */
311 u16 subsystem_device; /* VF subsystem device */
312 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
313 bool drivers_autoprobe; /* Auto probing of VFs by driver */
314
315 ANDROID_KABI_RESERVE(1);
316 ANDROID_KABI_RESERVE(2);
317 ANDROID_KABI_RESERVE(3);
318 ANDROID_KABI_RESERVE(4);
319 };
320
321 #ifdef CONFIG_PCI_DOE
322 void pci_doe_init(struct pci_dev *pdev);
323 void pci_doe_destroy(struct pci_dev *pdev);
324 void pci_doe_disconnected(struct pci_dev *pdev);
325 #else
pci_doe_init(struct pci_dev * pdev)326 static inline void pci_doe_init(struct pci_dev *pdev) { }
pci_doe_destroy(struct pci_dev * pdev)327 static inline void pci_doe_destroy(struct pci_dev *pdev) { }
pci_doe_disconnected(struct pci_dev * pdev)328 static inline void pci_doe_disconnected(struct pci_dev *pdev) { }
329 #endif
330
331 /**
332 * pci_dev_set_io_state - Set the new error state if possible.
333 *
334 * @dev: PCI device to set new error_state
335 * @new: the state we want dev to be in
336 *
337 * If the device is experiencing perm_failure, it has to remain in that state.
338 * Any other transition is allowed.
339 *
340 * Returns true if state has been changed to the requested state.
341 */
pci_dev_set_io_state(struct pci_dev * dev,pci_channel_state_t new)342 static inline bool pci_dev_set_io_state(struct pci_dev *dev,
343 pci_channel_state_t new)
344 {
345 pci_channel_state_t old;
346
347 switch (new) {
348 case pci_channel_io_perm_failure:
349 xchg(&dev->error_state, pci_channel_io_perm_failure);
350 return true;
351 case pci_channel_io_frozen:
352 old = cmpxchg(&dev->error_state, pci_channel_io_normal,
353 pci_channel_io_frozen);
354 return old != pci_channel_io_perm_failure;
355 case pci_channel_io_normal:
356 old = cmpxchg(&dev->error_state, pci_channel_io_frozen,
357 pci_channel_io_normal);
358 return old != pci_channel_io_perm_failure;
359 default:
360 return false;
361 }
362 }
363
pci_dev_set_disconnected(struct pci_dev * dev,void * unused)364 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
365 {
366 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
367 pci_doe_disconnected(dev);
368
369 return 0;
370 }
371
372 /* pci_dev priv_flags */
373 #define PCI_DEV_ADDED 0
374 #define PCI_DPC_RECOVERED 1
375 #define PCI_DPC_RECOVERING 2
376
pci_dev_assign_added(struct pci_dev * dev,bool added)377 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
378 {
379 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
380 }
381
pci_dev_is_added(const struct pci_dev * dev)382 static inline bool pci_dev_is_added(const struct pci_dev *dev)
383 {
384 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
385 }
386
387 #ifdef CONFIG_PCIEAER
388 #include <linux/aer.h>
389
390 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
391
392 struct aer_err_info {
393 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
394 int error_dev_num;
395
396 unsigned int id:16;
397
398 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
399 unsigned int __pad1:5;
400 unsigned int multi_error_valid:1;
401
402 unsigned int first_error:5;
403 unsigned int __pad2:2;
404 unsigned int tlp_header_valid:1;
405
406 unsigned int status; /* COR/UNCOR Error Status */
407 unsigned int mask; /* COR/UNCOR Error Mask */
408 struct aer_header_log_regs tlp; /* TLP Header */
409 };
410
411 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
412 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
413 #endif /* CONFIG_PCIEAER */
414
415 #ifdef CONFIG_PCIEPORTBUS
416 /* Cached RCEC Endpoint Association */
417 struct rcec_ea {
418 u8 nextbusn;
419 u8 lastbusn;
420 u32 bitmap;
421 };
422 #endif
423
424 #ifdef CONFIG_PCIE_DPC
425 void pci_save_dpc_state(struct pci_dev *dev);
426 void pci_restore_dpc_state(struct pci_dev *dev);
427 void pci_dpc_init(struct pci_dev *pdev);
428 void dpc_process_error(struct pci_dev *pdev);
429 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
430 bool pci_dpc_recovered(struct pci_dev *pdev);
431 #else
pci_save_dpc_state(struct pci_dev * dev)432 static inline void pci_save_dpc_state(struct pci_dev *dev) { }
pci_restore_dpc_state(struct pci_dev * dev)433 static inline void pci_restore_dpc_state(struct pci_dev *dev) { }
pci_dpc_init(struct pci_dev * pdev)434 static inline void pci_dpc_init(struct pci_dev *pdev) { }
pci_dpc_recovered(struct pci_dev * pdev)435 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
436 #endif
437
438 #ifdef CONFIG_PCIEPORTBUS
439 void pci_rcec_init(struct pci_dev *dev);
440 void pci_rcec_exit(struct pci_dev *dev);
441 void pcie_link_rcec(struct pci_dev *rcec);
442 void pcie_walk_rcec(struct pci_dev *rcec,
443 int (*cb)(struct pci_dev *, void *),
444 void *userdata);
445 #else
pci_rcec_init(struct pci_dev * dev)446 static inline void pci_rcec_init(struct pci_dev *dev) { }
pci_rcec_exit(struct pci_dev * dev)447 static inline void pci_rcec_exit(struct pci_dev *dev) { }
pcie_link_rcec(struct pci_dev * rcec)448 static inline void pcie_link_rcec(struct pci_dev *rcec) { }
pcie_walk_rcec(struct pci_dev * rcec,int (* cb)(struct pci_dev *,void *),void * userdata)449 static inline void pcie_walk_rcec(struct pci_dev *rcec,
450 int (*cb)(struct pci_dev *, void *),
451 void *userdata) { }
452 #endif
453
454 #ifdef CONFIG_PCI_ATS
455 /* Address Translation Service */
456 void pci_ats_init(struct pci_dev *dev);
457 void pci_restore_ats_state(struct pci_dev *dev);
458 #else
pci_ats_init(struct pci_dev * d)459 static inline void pci_ats_init(struct pci_dev *d) { }
pci_restore_ats_state(struct pci_dev * dev)460 static inline void pci_restore_ats_state(struct pci_dev *dev) { }
461 #endif /* CONFIG_PCI_ATS */
462
463 #ifdef CONFIG_PCI_PRI
464 void pci_pri_init(struct pci_dev *dev);
465 void pci_restore_pri_state(struct pci_dev *pdev);
466 #else
pci_pri_init(struct pci_dev * dev)467 static inline void pci_pri_init(struct pci_dev *dev) { }
pci_restore_pri_state(struct pci_dev * pdev)468 static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
469 #endif
470
471 #ifdef CONFIG_PCI_PASID
472 void pci_pasid_init(struct pci_dev *dev);
473 void pci_restore_pasid_state(struct pci_dev *pdev);
474 #else
pci_pasid_init(struct pci_dev * dev)475 static inline void pci_pasid_init(struct pci_dev *dev) { }
pci_restore_pasid_state(struct pci_dev * pdev)476 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
477 #endif
478
479 #ifdef CONFIG_PCI_IOV
480 int pci_iov_init(struct pci_dev *dev);
481 void pci_iov_release(struct pci_dev *dev);
482 void pci_iov_remove(struct pci_dev *dev);
483 void pci_iov_update_resource(struct pci_dev *dev, int resno);
484 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
485 void pci_restore_iov_state(struct pci_dev *dev);
486 int pci_iov_bus_range(struct pci_bus *bus);
487 extern const struct attribute_group sriov_pf_dev_attr_group;
488 extern const struct attribute_group sriov_vf_dev_attr_group;
489 #else
pci_iov_init(struct pci_dev * dev)490 static inline int pci_iov_init(struct pci_dev *dev)
491 {
492 return -ENODEV;
493 }
pci_iov_release(struct pci_dev * dev)494 static inline void pci_iov_release(struct pci_dev *dev) { }
pci_iov_remove(struct pci_dev * dev)495 static inline void pci_iov_remove(struct pci_dev *dev) { }
pci_restore_iov_state(struct pci_dev * dev)496 static inline void pci_restore_iov_state(struct pci_dev *dev) { }
pci_iov_bus_range(struct pci_bus * bus)497 static inline int pci_iov_bus_range(struct pci_bus *bus)
498 {
499 return 0;
500 }
501
502 #endif /* CONFIG_PCI_IOV */
503
504 #ifdef CONFIG_PCIE_PTM
505 void pci_ptm_init(struct pci_dev *dev);
506 void pci_save_ptm_state(struct pci_dev *dev);
507 void pci_restore_ptm_state(struct pci_dev *dev);
508 void pci_suspend_ptm(struct pci_dev *dev);
509 void pci_resume_ptm(struct pci_dev *dev);
510 #else
pci_ptm_init(struct pci_dev * dev)511 static inline void pci_ptm_init(struct pci_dev *dev) { }
pci_save_ptm_state(struct pci_dev * dev)512 static inline void pci_save_ptm_state(struct pci_dev *dev) { }
pci_restore_ptm_state(struct pci_dev * dev)513 static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
pci_suspend_ptm(struct pci_dev * dev)514 static inline void pci_suspend_ptm(struct pci_dev *dev) { }
pci_resume_ptm(struct pci_dev * dev)515 static inline void pci_resume_ptm(struct pci_dev *dev) { }
516 #endif
517
518 unsigned long pci_cardbus_resource_alignment(struct resource *);
519
pci_resource_alignment(struct pci_dev * dev,struct resource * res)520 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
521 struct resource *res)
522 {
523 #ifdef CONFIG_PCI_IOV
524 int resno = res - dev->resource;
525
526 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
527 return pci_sriov_resource_alignment(dev, resno);
528 #endif
529 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
530 return pci_cardbus_resource_alignment(res);
531 return resource_alignment(res);
532 }
533
534 void pci_acs_init(struct pci_dev *dev);
535 #ifdef CONFIG_PCI_QUIRKS
536 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
537 int pci_dev_specific_enable_acs(struct pci_dev *dev);
538 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
539 bool pcie_failed_link_retrain(struct pci_dev *dev);
540 #else
pci_dev_specific_acs_enabled(struct pci_dev * dev,u16 acs_flags)541 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
542 u16 acs_flags)
543 {
544 return -ENOTTY;
545 }
pci_dev_specific_enable_acs(struct pci_dev * dev)546 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
547 {
548 return -ENOTTY;
549 }
pci_dev_specific_disable_acs_redir(struct pci_dev * dev)550 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
551 {
552 return -ENOTTY;
553 }
pcie_failed_link_retrain(struct pci_dev * dev)554 static inline bool pcie_failed_link_retrain(struct pci_dev *dev)
555 {
556 return false;
557 }
558 #endif
559
560 /* PCI error reporting and recovery */
561 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
562 pci_channel_state_t state,
563 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
564
565 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
566 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt);
567 #ifdef CONFIG_PCIEASPM
568 void pcie_aspm_init_link_state(struct pci_dev *pdev);
569 void pcie_aspm_exit_link_state(struct pci_dev *pdev);
570 void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked);
571 void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
572 #else
pcie_aspm_init_link_state(struct pci_dev * pdev)573 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
pcie_aspm_exit_link_state(struct pci_dev * pdev)574 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
pcie_aspm_pm_state_change(struct pci_dev * pdev,bool locked)575 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { }
pcie_aspm_powersave_config_link(struct pci_dev * pdev)576 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
577 #endif
578
579 #ifdef CONFIG_PCIE_ECRC
580 void pcie_set_ecrc_checking(struct pci_dev *dev);
581 void pcie_ecrc_get_policy(char *str);
582 #else
pcie_set_ecrc_checking(struct pci_dev * dev)583 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
pcie_ecrc_get_policy(char * str)584 static inline void pcie_ecrc_get_policy(char *str) { }
585 #endif
586
587 struct pci_dev_reset_methods {
588 u16 vendor;
589 u16 device;
590 int (*reset)(struct pci_dev *dev, bool probe);
591 };
592
593 struct pci_reset_fn_method {
594 int (*reset_fn)(struct pci_dev *pdev, bool probe);
595 char *name;
596 };
597
598 #ifdef CONFIG_PCI_QUIRKS
599 int pci_dev_specific_reset(struct pci_dev *dev, bool probe);
600 #else
pci_dev_specific_reset(struct pci_dev * dev,bool probe)601 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
602 {
603 return -ENOTTY;
604 }
605 #endif
606
607 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
608 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
609 struct resource *res);
610 #else
acpi_get_rc_resources(struct device * dev,const char * hid,u16 segment,struct resource * res)611 static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
612 u16 segment, struct resource *res)
613 {
614 return -ENODEV;
615 }
616 #endif
617
618 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
619 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
pci_rebar_size_to_bytes(int size)620 static inline u64 pci_rebar_size_to_bytes(int size)
621 {
622 return 1ULL << (size + 20);
623 }
624
625 struct device_node;
626
627 #ifdef CONFIG_OF
628 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
629 int of_get_pci_domain_nr(struct device_node *node);
630 int of_pci_get_max_link_speed(struct device_node *node);
631 u32 of_pci_get_slot_power_limit(struct device_node *node,
632 u8 *slot_power_limit_value,
633 u8 *slot_power_limit_scale);
634 int pci_set_of_node(struct pci_dev *dev);
635 void pci_release_of_node(struct pci_dev *dev);
636 void pci_set_bus_of_node(struct pci_bus *bus);
637 void pci_release_bus_of_node(struct pci_bus *bus);
638
639 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
640
641 #else
642 static inline int
of_pci_parse_bus_range(struct device_node * node,struct resource * res)643 of_pci_parse_bus_range(struct device_node *node, struct resource *res)
644 {
645 return -EINVAL;
646 }
647
648 static inline int
of_get_pci_domain_nr(struct device_node * node)649 of_get_pci_domain_nr(struct device_node *node)
650 {
651 return -1;
652 }
653
654 static inline int
of_pci_get_max_link_speed(struct device_node * node)655 of_pci_get_max_link_speed(struct device_node *node)
656 {
657 return -EINVAL;
658 }
659
660 static inline u32
of_pci_get_slot_power_limit(struct device_node * node,u8 * slot_power_limit_value,u8 * slot_power_limit_scale)661 of_pci_get_slot_power_limit(struct device_node *node,
662 u8 *slot_power_limit_value,
663 u8 *slot_power_limit_scale)
664 {
665 if (slot_power_limit_value)
666 *slot_power_limit_value = 0;
667 if (slot_power_limit_scale)
668 *slot_power_limit_scale = 0;
669 return 0;
670 }
671
pci_set_of_node(struct pci_dev * dev)672 static inline int pci_set_of_node(struct pci_dev *dev) { return 0; }
pci_release_of_node(struct pci_dev * dev)673 static inline void pci_release_of_node(struct pci_dev *dev) { }
pci_set_bus_of_node(struct pci_bus * bus)674 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
pci_release_bus_of_node(struct pci_bus * bus)675 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
676
devm_of_pci_bridge_init(struct device * dev,struct pci_host_bridge * bridge)677 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
678 {
679 return 0;
680 }
681
682 #endif /* CONFIG_OF */
683
684 struct of_changeset;
685
686 #ifdef CONFIG_PCI_DYNAMIC_OF_NODES
687 void of_pci_make_dev_node(struct pci_dev *pdev);
688 void of_pci_remove_node(struct pci_dev *pdev);
689 int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs,
690 struct device_node *np);
691 #else
of_pci_make_dev_node(struct pci_dev * pdev)692 static inline void of_pci_make_dev_node(struct pci_dev *pdev) { }
of_pci_remove_node(struct pci_dev * pdev)693 static inline void of_pci_remove_node(struct pci_dev *pdev) { }
694 #endif
695
696 #ifdef CONFIG_PCIEAER
697 void pci_no_aer(void);
698 void pci_aer_init(struct pci_dev *dev);
699 void pci_aer_exit(struct pci_dev *dev);
700 extern const struct attribute_group aer_stats_attr_group;
701 void pci_aer_clear_fatal_status(struct pci_dev *dev);
702 int pci_aer_clear_status(struct pci_dev *dev);
703 int pci_aer_raw_clear_status(struct pci_dev *dev);
704 void pci_save_aer_state(struct pci_dev *dev);
705 void pci_restore_aer_state(struct pci_dev *dev);
706 #else
pci_no_aer(void)707 static inline void pci_no_aer(void) { }
pci_aer_init(struct pci_dev * d)708 static inline void pci_aer_init(struct pci_dev *d) { }
pci_aer_exit(struct pci_dev * d)709 static inline void pci_aer_exit(struct pci_dev *d) { }
pci_aer_clear_fatal_status(struct pci_dev * dev)710 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
pci_aer_clear_status(struct pci_dev * dev)711 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
pci_aer_raw_clear_status(struct pci_dev * dev)712 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
pci_save_aer_state(struct pci_dev * dev)713 static inline void pci_save_aer_state(struct pci_dev *dev) { }
pci_restore_aer_state(struct pci_dev * dev)714 static inline void pci_restore_aer_state(struct pci_dev *dev) { }
715 #endif
716
717 #ifdef CONFIG_ACPI
718 int pci_acpi_program_hp_params(struct pci_dev *dev);
719 extern const struct attribute_group pci_dev_acpi_attr_group;
720 void pci_set_acpi_fwnode(struct pci_dev *dev);
721 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe);
722 bool acpi_pci_power_manageable(struct pci_dev *dev);
723 bool acpi_pci_bridge_d3(struct pci_dev *dev);
724 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state);
725 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev);
726 void acpi_pci_refresh_power_state(struct pci_dev *dev);
727 int acpi_pci_wakeup(struct pci_dev *dev, bool enable);
728 bool acpi_pci_need_resume(struct pci_dev *dev);
729 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev);
730 #else
pci_dev_acpi_reset(struct pci_dev * dev,bool probe)731 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
732 {
733 return -ENOTTY;
734 }
pci_set_acpi_fwnode(struct pci_dev * dev)735 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { }
pci_acpi_program_hp_params(struct pci_dev * dev)736 static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
737 {
738 return -ENODEV;
739 }
acpi_pci_power_manageable(struct pci_dev * dev)740 static inline bool acpi_pci_power_manageable(struct pci_dev *dev)
741 {
742 return false;
743 }
acpi_pci_bridge_d3(struct pci_dev * dev)744 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev)
745 {
746 return false;
747 }
acpi_pci_set_power_state(struct pci_dev * dev,pci_power_t state)748 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
749 {
750 return -ENODEV;
751 }
acpi_pci_get_power_state(struct pci_dev * dev)752 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
753 {
754 return PCI_UNKNOWN;
755 }
acpi_pci_refresh_power_state(struct pci_dev * dev)756 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { }
acpi_pci_wakeup(struct pci_dev * dev,bool enable)757 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
758 {
759 return -ENODEV;
760 }
acpi_pci_need_resume(struct pci_dev * dev)761 static inline bool acpi_pci_need_resume(struct pci_dev *dev)
762 {
763 return false;
764 }
acpi_pci_choose_state(struct pci_dev * pdev)765 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
766 {
767 return PCI_POWER_ERROR;
768 }
769 #endif
770
771 #ifdef CONFIG_PCIEASPM
772 extern const struct attribute_group aspm_ctrl_attr_group;
773 #endif
774
775 extern const struct attribute_group pci_dev_reset_method_attr_group;
776
777 #ifdef CONFIG_X86_INTEL_MID
778 bool pci_use_mid_pm(void);
779 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
780 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev);
781 #else
pci_use_mid_pm(void)782 static inline bool pci_use_mid_pm(void)
783 {
784 return false;
785 }
mid_pci_set_power_state(struct pci_dev * pdev,pci_power_t state)786 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
787 {
788 return -ENODEV;
789 }
mid_pci_get_power_state(struct pci_dev * pdev)790 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
791 {
792 return PCI_UNKNOWN;
793 }
794 #endif
795
796 /*
797 * Config Address for PCI Configuration Mechanism #1
798 *
799 * See PCI Local Bus Specification, Revision 3.0,
800 * Section 3.2.2.3.2, Figure 3-2, p. 50.
801 */
802
803 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */
804 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */
805 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */
806
807 #define PCI_CONF1_BUS_MASK 0xff
808 #define PCI_CONF1_DEV_MASK 0x1f
809 #define PCI_CONF1_FUNC_MASK 0x7
810 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */
811
812 #define PCI_CONF1_ENABLE BIT(31)
813 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
814 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
815 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
816 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
817
818 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
819 (PCI_CONF1_ENABLE | \
820 PCI_CONF1_BUS(bus) | \
821 PCI_CONF1_DEV(dev) | \
822 PCI_CONF1_FUNC(func) | \
823 PCI_CONF1_REG(reg))
824
825 /*
826 * Extension of PCI Config Address for accessing extended PCIe registers
827 *
828 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
829 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address
830 * are used for specifying additional 4 high bits of PCI Express register.
831 */
832
833 #define PCI_CONF1_EXT_REG_SHIFT 16
834 #define PCI_CONF1_EXT_REG_MASK 0xf00
835 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
836
837 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
838 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
839 PCI_CONF1_EXT_REG(reg))
840
841 #endif /* DRIVERS_PCI_H */
842