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1 /*
2  * Broadcom NetXtreme-E RoCE driver.
3  *
4  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
5  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6  *
7  * This software is available to you under a choice of one of two
8  * licenses.  You may choose to be licensed under the terms of the GNU
9  * General Public License (GPL) Version 2, available from the file
10  * COPYING in the main directory of this source tree, or the
11  * BSD license below:
12  *
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions
15  * are met:
16  *
17  * 1. Redistributions of source code must retain the above copyright
18  *    notice, this list of conditions and the following disclaimer.
19  * 2. Redistributions in binary form must reproduce the above copyright
20  *    notice, this list of conditions and the following disclaimer in
21  *    the documentation and/or other materials provided with the
22  *    distribution.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  *
36  * Description: QPLib resource manager (header)
37  */
38 
39 #ifndef __BNXT_QPLIB_RES_H__
40 #define __BNXT_QPLIB_RES_H__
41 
42 extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero;
43 
44 #define CHIP_NUM_57508		0x1750
45 #define CHIP_NUM_57504		0x1751
46 #define CHIP_NUM_57502		0x1752
47 
48 struct bnxt_qplib_drv_modes {
49 	u8	wqe_mode;
50 	bool db_push;
51 	bool dbr_pacing;
52 };
53 
54 struct bnxt_qplib_chip_ctx {
55 	u16	chip_num;
56 	u8	chip_rev;
57 	u8	chip_metal;
58 	u16	hw_stats_size;
59 	u16	hwrm_cmd_max_timeout;
60 	struct bnxt_qplib_drv_modes modes;
61 	u64	hwrm_intf_ver;
62 	u32     dbr_stat_db_fifo;
63 };
64 
65 struct bnxt_qplib_db_pacing_data {
66 	u32 do_pacing;
67 	u32 pacing_th;
68 	u32 alarm_th;
69 	u32 fifo_max_depth;
70 	u32 fifo_room_mask;
71 	u32 fifo_room_shift;
72 	u32 grc_reg_offset;
73 };
74 
75 #define BNXT_QPLIB_DBR_PF_DB_OFFSET     0x10000
76 #define BNXT_QPLIB_DBR_VF_DB_OFFSET     0x4000
77 
78 #define PTR_CNT_PER_PG		(PAGE_SIZE / sizeof(void *))
79 #define PTR_MAX_IDX_PER_PG	(PTR_CNT_PER_PG - 1)
80 #define PTR_PG(x)		(((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG)
81 #define PTR_IDX(x)		((x) & PTR_MAX_IDX_PER_PG)
82 
83 #define HWQ_CMP(idx, hwq)	((idx) & ((hwq)->max_elements - 1))
84 
85 #define HWQ_FREE_SLOTS(hwq)	(hwq->max_elements - \
86 				((HWQ_CMP(hwq->prod, hwq)\
87 				- HWQ_CMP(hwq->cons, hwq))\
88 				& (hwq->max_elements - 1)))
89 enum bnxt_qplib_hwq_type {
90 	HWQ_TYPE_CTX,
91 	HWQ_TYPE_QUEUE,
92 	HWQ_TYPE_L2_CMPL,
93 	HWQ_TYPE_MR
94 };
95 
96 #define MAX_PBL_LVL_0_PGS		1
97 #define MAX_PBL_LVL_1_PGS		512
98 #define MAX_PBL_LVL_1_PGS_SHIFT		9
99 #define MAX_PBL_LVL_1_PGS_FOR_LVL_2	256
100 #define MAX_PBL_LVL_2_PGS		(256 * 512)
101 #define MAX_PDL_LVL_SHIFT               9
102 
103 enum bnxt_qplib_pbl_lvl {
104 	PBL_LVL_0,
105 	PBL_LVL_1,
106 	PBL_LVL_2,
107 	PBL_LVL_MAX
108 };
109 
110 #define ROCE_PG_SIZE_4K		(4 * 1024)
111 #define ROCE_PG_SIZE_8K		(8 * 1024)
112 #define ROCE_PG_SIZE_64K	(64 * 1024)
113 #define ROCE_PG_SIZE_2M		(2 * 1024 * 1024)
114 #define ROCE_PG_SIZE_8M		(8 * 1024 * 1024)
115 #define ROCE_PG_SIZE_1G		(1024 * 1024 * 1024)
116 
117 enum bnxt_qplib_hwrm_pg_size {
118 	BNXT_QPLIB_HWRM_PG_SIZE_4K	= 0,
119 	BNXT_QPLIB_HWRM_PG_SIZE_8K	= 1,
120 	BNXT_QPLIB_HWRM_PG_SIZE_64K	= 2,
121 	BNXT_QPLIB_HWRM_PG_SIZE_2M	= 3,
122 	BNXT_QPLIB_HWRM_PG_SIZE_8M	= 4,
123 	BNXT_QPLIB_HWRM_PG_SIZE_1G	= 5,
124 };
125 
126 struct bnxt_qplib_reg_desc {
127 	u8		bar_id;
128 	resource_size_t	bar_base;
129 	unsigned long	offset;
130 	void __iomem	*bar_reg;
131 	size_t		len;
132 };
133 
134 struct bnxt_qplib_pbl {
135 	u32				pg_count;
136 	u32				pg_size;
137 	void				**pg_arr;
138 	dma_addr_t			*pg_map_arr;
139 };
140 
141 struct bnxt_qplib_sg_info {
142 	struct ib_umem			*umem;
143 	u32				npages;
144 	u32				pgshft;
145 	u32				pgsize;
146 	bool				nopte;
147 };
148 
149 struct bnxt_qplib_hwq_attr {
150 	struct bnxt_qplib_res		*res;
151 	struct bnxt_qplib_sg_info	*sginfo;
152 	enum bnxt_qplib_hwq_type	type;
153 	u32				depth;
154 	u32				stride;
155 	u32				aux_stride;
156 	u32				aux_depth;
157 };
158 
159 struct bnxt_qplib_hwq {
160 	struct pci_dev			*pdev;
161 	/* lock to protect qplib_hwq */
162 	spinlock_t			lock;
163 	struct bnxt_qplib_pbl		pbl[PBL_LVL_MAX + 1];
164 	enum bnxt_qplib_pbl_lvl		level;		/* 0, 1, or 2 */
165 	/* ptr for easy access to the PBL entries */
166 	void				**pbl_ptr;
167 	/* ptr for easy access to the dma_addr */
168 	dma_addr_t			*pbl_dma_ptr;
169 	u32				max_elements;
170 	u32				depth;
171 	u16				element_size;	/* Size of each entry */
172 	u16				qe_ppg;	/* queue entry per page */
173 
174 	u32				prod;		/* raw */
175 	u32				cons;		/* raw */
176 	u8				cp_bit;
177 	u8				is_user;
178 	u64				*pad_pg;
179 	u32				pad_stride;
180 	u32				pad_pgofft;
181 };
182 
183 struct bnxt_qplib_db_info {
184 	void __iomem		*db;
185 	void __iomem		*priv_db;
186 	struct bnxt_qplib_hwq	*hwq;
187 	u32			xid;
188 	u32			max_slot;
189 	u32                     flags;
190 };
191 
192 enum bnxt_qplib_db_info_flags_mask {
193 	BNXT_QPLIB_FLAG_EPOCH_CONS_SHIFT        = 0x0UL,
194 	BNXT_QPLIB_FLAG_EPOCH_PROD_SHIFT        = 0x1UL,
195 	BNXT_QPLIB_FLAG_EPOCH_CONS_MASK         = 0x1UL,
196 	BNXT_QPLIB_FLAG_EPOCH_PROD_MASK         = 0x2UL,
197 };
198 
199 /* Tables */
200 struct bnxt_qplib_pd_tbl {
201 	unsigned long			*tbl;
202 	u32				max;
203 };
204 
205 struct bnxt_qplib_sgid_tbl {
206 	struct bnxt_qplib_gid_info	*tbl;
207 	u16				*hw_id;
208 	u16				max;
209 	u16				active;
210 	void				*ctx;
211 	u8				*vlan;
212 };
213 
214 enum {
215 	BNXT_QPLIB_DPI_TYPE_KERNEL      = 0,
216 	BNXT_QPLIB_DPI_TYPE_UC          = 1,
217 	BNXT_QPLIB_DPI_TYPE_WC          = 2
218 };
219 
220 struct bnxt_qplib_dpi {
221 	u32				dpi;
222 	u32				bit;
223 	void __iomem			*dbr;
224 	u64				umdbr;
225 	u8				type;
226 };
227 
228 struct bnxt_qplib_dpi_tbl {
229 	void				**app_tbl;
230 	unsigned long			*tbl;
231 	u16				max;
232 	struct bnxt_qplib_reg_desc	ucreg; /* Hold entire DB bar. */
233 	struct bnxt_qplib_reg_desc	wcreg;
234 	void __iomem			*priv_db;
235 };
236 
237 struct bnxt_qplib_stats {
238 	dma_addr_t			dma_map;
239 	void				*dma;
240 	u32				size;
241 	u32				fw_id;
242 };
243 
244 struct bnxt_qplib_vf_res {
245 	u32 max_qp_per_vf;
246 	u32 max_mrw_per_vf;
247 	u32 max_srq_per_vf;
248 	u32 max_cq_per_vf;
249 	u32 max_gid_per_vf;
250 };
251 
252 #define BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE	448
253 #define BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE	64
254 #define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE	64
255 #define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE	128
256 
257 #define MAX_TQM_ALLOC_REQ               48
258 #define MAX_TQM_ALLOC_BLK_SIZE          8
259 struct bnxt_qplib_tqm_ctx {
260 	struct bnxt_qplib_hwq           pde;
261 	u8                              pde_level; /* Original level */
262 	struct bnxt_qplib_hwq           qtbl[MAX_TQM_ALLOC_REQ];
263 	u8                              qcount[MAX_TQM_ALLOC_REQ];
264 };
265 
266 struct bnxt_qplib_ctx {
267 	u32				qpc_count;
268 	struct bnxt_qplib_hwq		qpc_tbl;
269 	u32				mrw_count;
270 	struct bnxt_qplib_hwq		mrw_tbl;
271 	u32				srqc_count;
272 	struct bnxt_qplib_hwq		srqc_tbl;
273 	u32				cq_count;
274 	struct bnxt_qplib_hwq		cq_tbl;
275 	struct bnxt_qplib_hwq		tim_tbl;
276 	struct bnxt_qplib_tqm_ctx	tqm_ctx;
277 	struct bnxt_qplib_stats		stats;
278 	struct bnxt_qplib_vf_res	vf_res;
279 };
280 
281 struct bnxt_qplib_res {
282 	struct pci_dev			*pdev;
283 	struct bnxt_qplib_chip_ctx	*cctx;
284 	struct bnxt_qplib_dev_attr      *dattr;
285 	struct net_device		*netdev;
286 	struct bnxt_qplib_rcfw		*rcfw;
287 	struct bnxt_qplib_pd_tbl	pd_tbl;
288 	/* To protect the pd table bit map */
289 	struct mutex			pd_tbl_lock;
290 	struct bnxt_qplib_sgid_tbl	sgid_tbl;
291 	struct bnxt_qplib_dpi_tbl	dpi_tbl;
292 	/* To protect the dpi table bit map */
293 	struct mutex                    dpi_tbl_lock;
294 	bool				prio;
295 	bool                            is_vf;
296 	struct bnxt_qplib_db_pacing_data *pacing_data;
297 };
298 
bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx * cctx)299 static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx)
300 {
301 	return (cctx->chip_num == CHIP_NUM_57508 ||
302 		cctx->chip_num == CHIP_NUM_57504 ||
303 		cctx->chip_num == CHIP_NUM_57502);
304 }
305 
bnxt_qplib_get_hwq_type(struct bnxt_qplib_res * res)306 static inline u8 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res *res)
307 {
308 	return bnxt_qplib_is_chip_gen_p5(res->cctx) ?
309 					HWQ_TYPE_QUEUE : HWQ_TYPE_L2_CMPL;
310 }
311 
bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx * cctx)312 static inline u8 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx *cctx)
313 {
314 	return bnxt_qplib_is_chip_gen_p5(cctx) ?
315 	       RING_ALLOC_REQ_RING_TYPE_NQ :
316 	       RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL;
317 }
318 
bnxt_qplib_base_pg_size(struct bnxt_qplib_hwq * hwq)319 static inline u8 bnxt_qplib_base_pg_size(struct bnxt_qplib_hwq *hwq)
320 {
321 	u8 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K;
322 	struct bnxt_qplib_pbl *pbl;
323 
324 	pbl = &hwq->pbl[PBL_LVL_0];
325 	switch (pbl->pg_size) {
326 	case ROCE_PG_SIZE_4K:
327 		pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K;
328 		break;
329 	case ROCE_PG_SIZE_8K:
330 		pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8K;
331 		break;
332 	case ROCE_PG_SIZE_64K:
333 		pg_size = BNXT_QPLIB_HWRM_PG_SIZE_64K;
334 		break;
335 	case ROCE_PG_SIZE_2M:
336 		pg_size = BNXT_QPLIB_HWRM_PG_SIZE_2M;
337 		break;
338 	case ROCE_PG_SIZE_8M:
339 		pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8M;
340 		break;
341 	case ROCE_PG_SIZE_1G:
342 		pg_size = BNXT_QPLIB_HWRM_PG_SIZE_1G;
343 		break;
344 	default:
345 		break;
346 	}
347 
348 	return pg_size;
349 }
350 
bnxt_qplib_get_qe(struct bnxt_qplib_hwq * hwq,u32 indx,u64 * pg)351 static inline void *bnxt_qplib_get_qe(struct bnxt_qplib_hwq *hwq,
352 				      u32 indx, u64 *pg)
353 {
354 	u32 pg_num, pg_idx;
355 
356 	pg_num = (indx / hwq->qe_ppg);
357 	pg_idx = (indx % hwq->qe_ppg);
358 	if (pg)
359 		*pg = (u64)&hwq->pbl_ptr[pg_num];
360 	return (void *)(hwq->pbl_ptr[pg_num] + hwq->element_size * pg_idx);
361 }
362 
bnxt_qplib_get_prod_qe(struct bnxt_qplib_hwq * hwq,u32 idx)363 static inline void *bnxt_qplib_get_prod_qe(struct bnxt_qplib_hwq *hwq, u32 idx)
364 {
365 	idx += hwq->prod;
366 	if (idx >= hwq->depth)
367 		idx -= hwq->depth;
368 	return bnxt_qplib_get_qe(hwq, idx, NULL);
369 }
370 
371 #define to_bnxt_qplib(ptr, type, member)	\
372 	container_of(ptr, type, member)
373 
374 struct bnxt_qplib_pd;
375 struct bnxt_qplib_dev_attr;
376 
377 void bnxt_qplib_free_hwq(struct bnxt_qplib_res *res,
378 			 struct bnxt_qplib_hwq *hwq);
379 int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq,
380 			      struct bnxt_qplib_hwq_attr *hwq_attr);
381 int bnxt_qplib_alloc_pd(struct bnxt_qplib_res *res,
382 			struct bnxt_qplib_pd *pd);
383 int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res,
384 			  struct bnxt_qplib_pd_tbl *pd_tbl,
385 			  struct bnxt_qplib_pd *pd);
386 int bnxt_qplib_alloc_dpi(struct bnxt_qplib_res *res,
387 			 struct bnxt_qplib_dpi *dpi,
388 			 void *app, u8 type);
389 int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res,
390 			   struct bnxt_qplib_dpi *dpi);
391 void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res);
392 int bnxt_qplib_init_res(struct bnxt_qplib_res *res);
393 void bnxt_qplib_free_res(struct bnxt_qplib_res *res);
394 int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev,
395 			 struct net_device *netdev,
396 			 struct bnxt_qplib_dev_attr *dev_attr);
397 void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res,
398 			 struct bnxt_qplib_ctx *ctx);
399 int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res,
400 			 struct bnxt_qplib_ctx *ctx,
401 			 bool virt_fn, bool is_p5);
402 int bnxt_qplib_map_db_bar(struct bnxt_qplib_res *res);
403 void bnxt_qplib_unmap_db_bar(struct bnxt_qplib_res *res);
404 
405 int bnxt_qplib_determine_atomics(struct pci_dev *dev);
406 
bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_db_info * dbinfo,struct bnxt_qplib_hwq * hwq,u32 cnt)407 static inline void bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_db_info *dbinfo,
408 					    struct bnxt_qplib_hwq *hwq, u32 cnt)
409 {
410 	/* move prod and update toggle/epoch if wrap around */
411 	hwq->prod += cnt;
412 	if (hwq->prod >= hwq->depth) {
413 		hwq->prod %= hwq->depth;
414 		dbinfo->flags ^= 1UL << BNXT_QPLIB_FLAG_EPOCH_PROD_SHIFT;
415 	}
416 }
417 
bnxt_qplib_hwq_incr_cons(u32 max_elements,u32 * cons,u32 cnt,u32 * dbinfo_flags)418 static inline void bnxt_qplib_hwq_incr_cons(u32 max_elements, u32 *cons, u32 cnt,
419 					    u32 *dbinfo_flags)
420 {
421 	/* move cons and update toggle/epoch if wrap around */
422 	*cons += cnt;
423 	if (*cons >= max_elements) {
424 		*cons %= max_elements;
425 		*dbinfo_flags ^= 1UL << BNXT_QPLIB_FLAG_EPOCH_CONS_SHIFT;
426 	}
427 }
428 
bnxt_qplib_ring_db32(struct bnxt_qplib_db_info * info,bool arm)429 static inline void bnxt_qplib_ring_db32(struct bnxt_qplib_db_info *info,
430 					bool arm)
431 {
432 	u32 key = 0;
433 
434 	key |= info->hwq->cons | (CMPL_DOORBELL_IDX_VALID |
435 		(CMPL_DOORBELL_KEY_CMPL & CMPL_DOORBELL_KEY_MASK));
436 	if (!arm)
437 		key |= CMPL_DOORBELL_MASK;
438 	writel(key, info->db);
439 }
440 
bnxt_qplib_ring_db(struct bnxt_qplib_db_info * info,u32 type)441 static inline void bnxt_qplib_ring_db(struct bnxt_qplib_db_info *info,
442 				      u32 type)
443 {
444 	u64 key = 0;
445 
446 	key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
447 	key <<= 32;
448 	key |= (info->hwq->cons & DBC_DBC_INDEX_MASK);
449 	writeq(key, info->db);
450 }
451 
bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info * info,u32 type)452 static inline void bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info *info,
453 					   u32 type)
454 {
455 	u64 key = 0;
456 
457 	key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
458 	key <<= 32;
459 	key |= ((info->hwq->prod / info->max_slot)) & DBC_DBC_INDEX_MASK;
460 	writeq(key, info->db);
461 }
462 
bnxt_qplib_armen_db(struct bnxt_qplib_db_info * info,u32 type)463 static inline void bnxt_qplib_armen_db(struct bnxt_qplib_db_info *info,
464 				       u32 type)
465 {
466 	u64 key = 0;
467 
468 	key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
469 	key <<= 32;
470 	writeq(key, info->priv_db);
471 }
472 
bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info * info,u32 th)473 static inline void bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info *info,
474 					 u32 th)
475 {
476 	u64 key = 0;
477 
478 	key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | th;
479 	key <<= 32;
480 	key |=  th & DBC_DBC_INDEX_MASK;
481 	writeq(key, info->priv_db);
482 }
483 
bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info * info,struct bnxt_qplib_chip_ctx * cctx,bool arm)484 static inline void bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info *info,
485 					 struct bnxt_qplib_chip_ctx *cctx,
486 					 bool arm)
487 {
488 	u32 type;
489 
490 	type = arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ;
491 	if (bnxt_qplib_is_chip_gen_p5(cctx))
492 		bnxt_qplib_ring_db(info, type);
493 	else
494 		bnxt_qplib_ring_db32(info, arm);
495 }
496 
_is_ext_stats_supported(u16 dev_cap_flags)497 static inline bool _is_ext_stats_supported(u16 dev_cap_flags)
498 {
499 	return dev_cap_flags &
500 		CREQ_QUERY_FUNC_RESP_SB_EXT_STATS;
501 }
502 
_is_hw_retx_supported(u16 dev_cap_flags)503 static inline bool _is_hw_retx_supported(u16 dev_cap_flags)
504 {
505 	return dev_cap_flags &
506 		(CREQ_QUERY_FUNC_RESP_SB_HW_REQUESTER_RETX_ENABLED |
507 		 CREQ_QUERY_FUNC_RESP_SB_HW_RESPONDER_RETX_ENABLED);
508 }
509 
510 #define BNXT_RE_HW_RETX(a) _is_hw_retx_supported((a))
511 
bnxt_qplib_dbr_pacing_en(struct bnxt_qplib_chip_ctx * cctx)512 static inline u8 bnxt_qplib_dbr_pacing_en(struct bnxt_qplib_chip_ctx *cctx)
513 {
514 	return cctx->modes.dbr_pacing;
515 }
516 
517 #endif /* __BNXT_QPLIB_RES_H__ */
518