1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2021, MediaTek Inc.
4 * Copyright (c) 2021-2022, Intel Corporation.
5 *
6 * Authors:
7 * Haijun Liu <haijun.liu@mediatek.com>
8 * Sreehari Kancharla <sreehari.kancharla@intel.com>
9 *
10 * Contributors:
11 * Amir Hanania <amir.hanania@intel.com>
12 * Ricardo Martinez <ricardo.martinez@linux.intel.com>
13 */
14
15 #include <linux/bits.h>
16 #include <linux/completion.h>
17 #include <linux/dev_printk.h>
18 #include <linux/io.h>
19 #include <linux/irqreturn.h>
20
21 #include "t7xx_mhccif.h"
22 #include "t7xx_modem_ops.h"
23 #include "t7xx_pci.h"
24 #include "t7xx_pcie_mac.h"
25 #include "t7xx_reg.h"
26
27 #define D2H_INT_SR_ACK (D2H_INT_SUSPEND_ACK | \
28 D2H_INT_RESUME_ACK | \
29 D2H_INT_SUSPEND_ACK_AP | \
30 D2H_INT_RESUME_ACK_AP)
31
t7xx_mhccif_clear_interrupts(struct t7xx_pci_dev * t7xx_dev,u32 mask)32 static void t7xx_mhccif_clear_interrupts(struct t7xx_pci_dev *t7xx_dev, u32 mask)
33 {
34 void __iomem *mhccif_pbase = t7xx_dev->base_addr.mhccif_rc_base;
35
36 /* Clear level 2 interrupt */
37 iowrite32(mask, mhccif_pbase + REG_EP2RC_SW_INT_ACK);
38 /* Ensure write is complete */
39 t7xx_mhccif_read_sw_int_sts(t7xx_dev);
40 /* Clear level 1 interrupt */
41 t7xx_pcie_mac_clear_int_status(t7xx_dev, MHCCIF_INT);
42 }
43
t7xx_mhccif_isr_thread(int irq,void * data)44 static irqreturn_t t7xx_mhccif_isr_thread(int irq, void *data)
45 {
46 struct t7xx_pci_dev *t7xx_dev = data;
47 u32 int_status, val;
48
49 val = T7XX_L1_1_BIT(1) | T7XX_L1_2_BIT(1);
50 iowrite32(val, IREG_BASE(t7xx_dev) + DISABLE_ASPM_LOWPWR);
51
52 int_status = t7xx_mhccif_read_sw_int_sts(t7xx_dev);
53 if (int_status & D2H_SW_INT_MASK) {
54 int ret = t7xx_pci_mhccif_isr(t7xx_dev);
55
56 if (ret)
57 dev_err(&t7xx_dev->pdev->dev, "PCI MHCCIF ISR failure: %d", ret);
58 }
59
60 t7xx_mhccif_clear_interrupts(t7xx_dev, int_status);
61
62 if (int_status & D2H_INT_DS_LOCK_ACK)
63 complete_all(&t7xx_dev->sleep_lock_acquire);
64
65 if (int_status & D2H_INT_SR_ACK)
66 complete(&t7xx_dev->pm_sr_ack);
67
68 iowrite32(T7XX_L1_BIT(1), IREG_BASE(t7xx_dev) + ENABLE_ASPM_LOWPWR);
69
70 int_status = t7xx_mhccif_read_sw_int_sts(t7xx_dev);
71 if (!int_status) {
72 val = T7XX_L1_1_BIT(1) | T7XX_L1_2_BIT(1);
73 iowrite32(val, IREG_BASE(t7xx_dev) + ENABLE_ASPM_LOWPWR);
74 }
75
76 t7xx_pcie_mac_set_int(t7xx_dev, MHCCIF_INT);
77 return IRQ_HANDLED;
78 }
79
t7xx_mhccif_read_sw_int_sts(struct t7xx_pci_dev * t7xx_dev)80 u32 t7xx_mhccif_read_sw_int_sts(struct t7xx_pci_dev *t7xx_dev)
81 {
82 return ioread32(t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_STS);
83 }
84
t7xx_mhccif_mask_set(struct t7xx_pci_dev * t7xx_dev,u32 val)85 void t7xx_mhccif_mask_set(struct t7xx_pci_dev *t7xx_dev, u32 val)
86 {
87 iowrite32(val, t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_EAP_MASK_SET);
88 }
89
t7xx_mhccif_mask_clr(struct t7xx_pci_dev * t7xx_dev,u32 val)90 void t7xx_mhccif_mask_clr(struct t7xx_pci_dev *t7xx_dev, u32 val)
91 {
92 iowrite32(val, t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_EAP_MASK_CLR);
93 }
94
t7xx_mhccif_mask_get(struct t7xx_pci_dev * t7xx_dev)95 u32 t7xx_mhccif_mask_get(struct t7xx_pci_dev *t7xx_dev)
96 {
97 return ioread32(t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_EAP_MASK);
98 }
99
t7xx_mhccif_isr_handler(int irq,void * data)100 static irqreturn_t t7xx_mhccif_isr_handler(int irq, void *data)
101 {
102 return IRQ_WAKE_THREAD;
103 }
104
t7xx_mhccif_init(struct t7xx_pci_dev * t7xx_dev)105 void t7xx_mhccif_init(struct t7xx_pci_dev *t7xx_dev)
106 {
107 t7xx_dev->base_addr.mhccif_rc_base = t7xx_dev->base_addr.pcie_ext_reg_base +
108 MHCCIF_RC_DEV_BASE -
109 t7xx_dev->base_addr.pcie_dev_reg_trsl_addr;
110
111 t7xx_dev->intr_handler[MHCCIF_INT] = t7xx_mhccif_isr_handler;
112 t7xx_dev->intr_thread[MHCCIF_INT] = t7xx_mhccif_isr_thread;
113 t7xx_dev->callback_param[MHCCIF_INT] = t7xx_dev;
114 }
115
t7xx_mhccif_h2d_swint_trigger(struct t7xx_pci_dev * t7xx_dev,u32 channel)116 void t7xx_mhccif_h2d_swint_trigger(struct t7xx_pci_dev *t7xx_dev, u32 channel)
117 {
118 void __iomem *mhccif_pbase = t7xx_dev->base_addr.mhccif_rc_base;
119
120 iowrite32(BIT(channel), mhccif_pbase + REG_RC2EP_SW_BSY);
121 iowrite32(channel, mhccif_pbase + REG_RC2EP_SW_TCHNUM);
122 }
123