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/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
4 PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
8 When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
12 gpio driver to configure a pin.
14 GPIO bank can have one of the two possible types of interrupt-wirings.
16 First type is via irqmux, single interrupt is used by multiple gpio banks. This
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
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Dsamsung,pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
22 - External GPIO interrupts (see interrupts property in pin controller node);
24 - External wake-up interrupts - multiplexed (capable of waking up the system
25 see interrupts property in external wake-up interrupt controller node -
26 samsung,pinctrl-wakeup-interrupt.yaml);
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Dsamsung,pinctrl-gpio-bank.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-gpio-bank.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C/S5P/Exynos SoC pin controller - gpio bank
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
18 GPIO bank description for Samsung S3C/S5P/Exynos SoC pin controller.
24 '#gpio-cells':
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Dmicrochip,sparx5-sgpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microsemi/Microchip Serial GPIO controller
10 - Lars Povlsen <lars.povlsen@microchip.com>
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
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Dpinctrl-sirf.txt4 - compatible : "sirf,prima2-pinctrl"
5 - reg : Address range of the pinctrl registers
6 - interrupts : Interrupts used by every GPIO group
7 - gpio-controller : Indicates this device is a GPIO controller
8 - interrupt-controller : Marks the device node as an interrupt controller
10 - sirf,pullups : if n-th bit of m-th bank is set, set a pullup on GPIO-n of bank m
11 - sirf,pulldowns : if n-th bit of m-th bank is set, set a pulldown on GPIO-n of bank m
13 Please refer to pinctrl-bindings.txt in this directory for details of the common
19 Required subnode-properties:
20 - sirf,pins : An array of strings. Each string contains the name of a group.
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Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: STM32 GPIO and Pin Mux/Config controller
11 - Alexandre TORGUE <alexandre.torgue@foss.st.com>
14 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
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Datmel,at91-pinctrl.txt10 Please refer to pinctrl-bindings.txt in this directory for details of the
18 such as pull-up, multi drive, etc.
21 - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
22 or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
23 - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
24 configured in this periph mode. All the periph and bank need to be describe.
29 Each line will represent a pio bank
33 Bank: 3 (A, B and C)
41 For each peripheral/bank we will describe in a u32 if a pin can be
45 From the datasheet Table 10-2.
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Dpinctrl-mcp23s08.txt2 8-/16-bit I/O expander with serial interface (I2C/SPI)
5 - compatible : Should be
6 - "mcp,mcp23s08" (DEPRECATED) for 8 GPIO SPI version
7 - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version
8 - "mcp,mcp23008" (DEPRECATED) for 8 GPIO I2C version or
9 - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip
11 - "microchip,mcp23s08" for 8 GPIO SPI version
12 - "microchip,mcp23s17" for 16 GPIO SPI version
13 - "microchip,mcp23s18" for 16 GPIO SPI version
14 - "microchip,mcp23008" for 8 GPIO I2C version or
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Dallwinner,sun4i-a10-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/allwinner,sun4i-a10-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#gpio-cells":
17 GPIO consumers must use three arguments, first the number of the
18 bank, then the pin number inside that bank, and finally the GPIO
21 "#interrupt-cells":
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Dnuvoton,npcm7xx-pinctrl.txt3 The Nuvoton BMC NPCM7XX Pin Controller multi-function routed through
4 the multiplexing block, Each pin supports GPIO functionality (GPIOx)
9 - #address-cells : should be 1.
10 - #size-cells : should be 1.
11 - compatible : "nuvoton,npcm750-pinctrl" for Poleg NPCM7XX.
12 - ranges : defines mapping ranges between pin controller node (parent)
13 to GPIO bank node (children).
15 === GPIO Bank Subnode ===
17 The NPCM7XX has 8 GPIO Banks each GPIO bank supports 32 GPIO.
19 Required GPIO Bank subnode-properties:
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Damlogic,meson-pinctrl-a1.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/amlogic,meson-pinctrl-a1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 - $ref: amlogic,meson-pinctrl-common.yaml#
18 - amlogic,c3-periphs-pinctrl
19 - amlogic,meson-a1-periphs-pinctrl
20 - amlogic,meson-s4-periphs-pinctrl
23 - compatible
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Damlogic,meson-pinctrl-g12a-aobus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 - $ref: amlogic,meson-pinctrl-common.yaml#
18 - amlogic,meson-g12a-aobus-pinctrl
21 - compatible
24 "^bank@[0-9a-z]+$":
25 $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio
[all …]
Drockchip,pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
16 options with option 0 being used as a GPIO.
18 Please refer to pinctrl-bindings.txt in this directory for details of the
26 various pad settings such as pull-up, etc.
29 defined as gpio sub-nodes of the pinmux controller.
34 - rockchip,px30-pinctrl
35 - rockchip,rk2928-pinctrl
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Damlogic,meson-pinctrl-g12a-periphs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 - $ref: amlogic,meson-pinctrl-common.yaml#
18 - amlogic,meson-g12a-periphs-pinctrl
21 - compatible
24 "^bank@[0-9a-z]+$":
25 $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio
[all …]
/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dgpio.txt1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
21 one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
[all …]
/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
Dpar_io.txt10 - device_type : should be "par_io".
11 - reg : offset to the register set and its length.
12 - num-ports : number of Parallel I/O ports
17 #address-cells = <1>;
18 #size-cells = <0>;
20 num-ports = <7>;
26 the new device trees. Instead, each Par I/O bank should be represented
27 via its own gpio-controller node:
30 - #gpio-cells : should be "2".
31 - compatible : should be "fsl,<chip>-qe-pario-bank",
[all …]
/Documentation/devicetree/bindings/gpio/
Dbrcm,brcmstb-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB "UPG GIO" GPIO controller
10 The controller's registers are organized as sets of eight 32-bit
11 registers with each set controlling a bank of up to 32 pins. A single
15 - Doug Berger <opendmb@gmail.com>
16 - Florian Fainelli <f.fainelli@gmail.com>
21 - enum:
[all …]
Drockchip,gpio-bank.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/gpio/rockchip,gpio-bank.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip GPIO bank
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,gpio-bank
16 - rockchip,rk3188-gpio-bank0
27 - description: APB interface clock source
28 - description: GPIO debounce reference clock source
[all …]
Dbrcm,kona-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,kona-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Kona family GPIO controller
10 The Broadcom GPIO Controller IP can be configured prior to synthesis to
11 support up to 8 banks of 32 GPIOs where each bank has its own IRQ. The
12 GPIO controller only supports edge, not level, triggering of interrupts.
15 - Ray Jui <rjui@broadcom.com>
20 - enum:
[all …]
Dgpio-nmk.txt1 Nomadik GPIO controller
4 - compatible : Should be "st,nomadik-gpio".
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller.
7 - #gpio-cells : Should be two:
10 - bits[3:0] trigger type and level flags:
11 1 = low-to-high edge triggered.
12 2 = high-to-low edge triggered.
13 4 = active high level-sensitive.
14 8 = active low level-sensitive.
[all …]
Dmicrochip,pic32-gpio.txt1 * Microchip PIC32 GPIO devices (PIO).
4 - compatible: "microchip,pic32mzda-gpio"
5 - reg: Base address and length for the device.
6 - interrupts: The port interrupt shared by all pins.
7 - gpio-controller: Marks the port as GPIO controller.
8 - #gpio-cells: Two. The first cell is the pin number and
9 the second cell is used to specify the gpio polarity as defined in
10 defined in <dt-bindings/gpio/gpio.h>:
14 - interrupt-controller: Marks the device node as an interrupt controller.
15 - #interrupt-cells: Two. The first cell is the GPIO number and second cell
[all …]
Dgpio_lpc32xx.txt1 NXP LPC32xx SoC GPIO controller
4 - compatible: must be "nxp,lpc3220-gpio"
5 - reg: Physical base address and length of the controller's registers.
6 - gpio-controller: Marks the device node as a GPIO controller.
7 - #gpio-cells: Should be 3:
8 1) bank:
9 0: GPIO P0
10 1: GPIO P1
11 2: GPIO P2
12 3: GPIO P3
[all …]
Dgpio.txt1 Specifying GPIO information for devices
5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
14 GPIO properties can contain one or more GPIO phandles, but only in exceptional
23 The following example could be used to describe GPIO pins used as device enable
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
[all …]
Drealtek,otto-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/realtek,otto-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Realtek Otto GPIO controller
10 - Sander Vanheule <sander@svanheule.net>
11 - Bert Vermeulen <bert@biot.com>
14 Realtek's GPIO controller on their MIPS switch SoCs (Otto platform) consists
15 of two banks of 32 GPIOs. These GPIOs can generate edge-triggered interrupts.
16 Each bank's interrupts are cascased into one interrupt line on the parent
[all …]
/Documentation/admin-guide/gpio/
Dgpio-sim.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
3 Configfs GPIO Simulator
6 The configfs GPIO Simulator (gpio-sim) provides a way to create simulated GPIO
8 using the standard GPIO character device interface as well as manipulated
12 ------------------------
14 The gpio-sim module registers a configfs subsystem called ``'gpio-sim'``. For
21 **Group:** ``/config/gpio-sim``
23 This is the top directory of the gpio-sim configfs tree.
25 **Group:** ``/config/gpio-sim/gpio-device``
27 **Attribute:** ``/config/gpio-sim/gpio-device/dev_name``
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