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/Documentation/devicetree/bindings/pinctrl/
Dpinmux-node.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic Pin Multiplexing Node
10 - Linus Walleij <linus.walleij@linaro.org>
13 The contents of the pin configuration child nodes are defined by the binding
14 for the individual pin controller device. The pin configuration nodes need not
15 be direct children of the pin controller device; they may be grandchildren,
18 the binding for the individual pin controller device.
[all …]
Dpinctrl-bindings.txt3 Hardware modules that control pin multiplexing or configuration parameters
4 such as pull-up/down, tri-state, drive-strength etc are designated as pin
5 controllers. Each pin controller must be represented as a node in device tree,
8 Hardware modules whose signals are affected by pin configuration are
12 For a client device to operate correctly, certain pin controllers must
13 set up certain specific pin configurations. Some client devices need a
14 single static pin configuration, e.g. set up during initialization. Others
15 need to reconfigure pins at run-time, for example to tri-state pins when the
21 for client device device tree nodes to map those state names to the pin
24 Note that pin controllers themselves may also be client devices of themselves.
[all …]
Dcnxt,cx92755-pinctrl.txt1 Conexant Digicolor CX92755 General Purpose Pin Mapping
3 This document describes the device tree binding of the pin mapping hardware
7 === Pin Controller Node ===
11 - compatible: Must be "cnxt,cx92755-pinctrl"
12 - reg: Base address of the General Purpose Pin Mapping register block and the
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells: Must be <2>. The first cell is the pin number and the
16 second cell is used to specify flags. See include/dt-bindings/gpio/gpio.h
22 compatible = "cnxt,cx92755-pinctrl";
24 gpio-controller;
[all …]
Dsprd,pinctrl.txt1 * Spreadtrum Pin Controller
3 The Spreadtrum pin controller are organized in 3 blocks (types).
9 driving level": One pin can output 3.0v or 1.8v, depending on the
11 select 3.0v, then the pin can output 3.0v. "system control" is used
16 of them, so we can not make every Spreadtrum-special configuration
23 bits in one global control register as one pin, thus we should
24 record every pin's bit offset, bit width and register offset to
25 configure this field (pin).
28 register definition, and each register described one pin is used
29 to configure the pin sleep mode, function select and sleep related
[all …]
Dpinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Pin controller device
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Rafał Miłecki <rafal@milecki.pl>
14 Pin controller devices should contain the pin configuration nodes that client
17 The contents of each of those pin configuration child nodes is defined
18 entirely by the binding for the individual pin controller device. There
20 provides generic helper bindings that the pin controller driver can use.
[all …]
Drenesas,rza1-ports.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/A1 combined Pin and GPIO controller
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
14 The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis
17 writing configuration values to per-port register sets.
[all …]
Dsamsung,pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C/S5P/Exynos SoC pin controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
15 This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
18 All the pin controller nodes should be represented in the aliases node using
22 - External GPIO interrupts (see interrupts property in pin controller node);
[all …]
Dsamsung,pinctrl-pins-cfg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-pins-cfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C/S5P/Exynos SoC pin controller - pins configuration
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
15 This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
18 Pins configuration for Samsung S3C/S5P/Exynos SoC pin controller.
[all …]
Dmarvell,armada-37xx-pinctrl.txt1 * Marvell Armada 37xx SoC pin and gpio controller
3 Each Armada 37xx SoC come with two pin and gpio controller one for the
11 GPIO and pin controller:
12 ------------------------
16 Refer to pinctrl-bindings.txt in this directory for details of the
18 of the phrase "pin configuration node".
22 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
24 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
26 - reg: The first set of register are for pinctrl/gpio and the second
28 - interrupts: list of the interrupt use by the gpio
[all …]
Datmel,at91-pinctrl.txt10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 Atmel AT91 pin configuration node is a node of a group of pins which can be
16 of the pins in that group. The 'pins' selects the function mode(also named pin
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, multi drive, etc.
21 - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
22 or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
23 - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
41 For each peripheral/bank we will describe in a u32 if a pin can be
[all …]
Dbrcm,nsp-gpio.txt4 - compatible:
5 Must be "brcm,nsp-gpio-a"
7 - reg:
11 - #gpio-cells:
12 Must be two. The first cell is the GPIO pin number (within the
13 controller's pin space) and the second cell is used for the following:
16 - gpio-controller:
19 - ngpios:
23 - interrupts:
26 - interrupt-controller:
[all …]
Drenesas,rzn1-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/N1 Pin Controller
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 - enum:
17 - renesas,r9a06g032-pinctrl # RZ/N1D
18 - renesas,r9a06g033-pinctrl # RZ/N1S
[all …]
Dcortina,gemini-pinctrl.txt1 Cortina Systems Gemini pin controller
3 This pin controller is found in the Cortina Systems Gemini SoC family,
4 see further arm/gemini.txt. It is a purely group-based multiplexing pin
7 The pin controller node must be a subnode of the system controller node.
10 - compatible: "cortina,gemini-pinctrl"
12 Subnodes of the pin controller contain pin control multiplexing set-up
13 and pin configuration of individual pins.
15 Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes
16 and generic pin config nodes.
19 - skew-delay is supported on the Ethernet pins
[all …]
Dsprd,sc9860-pinctrl.txt1 * Spreadtrum SC9860 Pin Controller
7 - compatible: Must be "sprd,sc9860-pinctrl".
8 - reg: The register address of pin controller device.
9 - pins : An array of strings, each string containing the name of a pin.
12 - function: A string containing the name of the function, values must be
14 - drive-strength: Drive strength in mA. Supported values: 2, 4, 6, 8, 10,
16 - input-schmitt-disable: Enable schmitt-trigger mode.
17 - input-schmitt-enable: Disable schmitt-trigger mode.
18 - bias-disable: Disable pin bias.
19 - bias-pull-down: Pull down on pin.
[all …]
Dfsl,imx-pinctrl.txt10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 Freescale IMX pin configuration node is a node of a group of pins which can be
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
24 Required properties for pin configuration node:
25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
[all …]
/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
Dpincfg.txt1 * Pin configuration nodes
4 - pio-map : array of pin configurations. Each pin is defined by 6
5 integers. The six numbers are respectively: port, pin, dir,
7 - port : port number of the pin; 0-6 represent port A-G in UM.
8 - pin : pin number in the port.
9 - dir : direction of the pin, should encode as follows:
11 0 = The pin is disabled
12 1 = The pin is an output
13 2 = The pin is an input
14 3 = The pin is I/O
[all …]
/Documentation/devicetree/bindings/sound/
Drt5659.txt7 - compatible : One of "realtek,rt5659" or "realtek,rt5658".
9 - reg : The I2C address of the device.
11 - interrupts : The CODEC's interrupt output.
15 - clocks: The phandle of the master clock to the CODEC
16 - clock-names: Should be "mclk"
18 - realtek,in1-differential
19 - realtek,in3-differential
20 - realtek,in4-differential
21 Boolean. Indicate MIC1/3/4 input are differential, rather than single-ended.
23 - realtek,dmic1-data-pin
[all …]
Drt5668.txt7 - compatible : "realtek,rt5668b"
9 - reg : The I2C address of the device.
13 - interrupts : The CODEC's interrupt output.
15 - realtek,dmic1-data-pin
17 1: using GPIO2 pin as dmic1 data pin
18 2: using GPIO5 pin as dmic1 data pin
20 - realtek,dmic1-clk-pin
21 0: using GPIO1 pin as dmic1 clock pin
22 1: using GPIO3 pin as dmic1 clock pin
24 - realtek,jd-src
[all …]
Drt5645.txt7 - compatible : One of "realtek,rt5645" or "realtek,rt5650".
9 - reg : The I2C address of the device.
11 - interrupts : The CODEC's interrupt output.
13 - avdd-supply: Power supply for AVDD, providing 1.8V.
15 - cpvdd-supply: Power supply for CPVDD, providing 3.5V.
19 - hp-detect-gpios:
20 a GPIO spec for the external headphone detect pin. If jd-mode = 0,
21 we will get the JD status by getting the value of hp-detect-gpios.
23 - cbj-sleeve-gpios:
28 - realtek,in2-differential
[all …]
Drt5682.txt7 - compatible : "realtek,rt5682" or "realtek,rt5682i"
9 - reg : The I2C address of the device.
11 - AVDD-supply: phandle to the regulator supplying analog power through the
12 AVDD pin
14 - MICVDD-supply: phandle to the regulator supplying power for the microphone
15 bias through the MICVDD pin. Either MICVDD or VBAT should be present.
17 - VBAT-supply: phandle to the regulator supplying battery power through the
18 VBAT pin. Either MICVDD or VBAT should be present.
20 - DBVDD-supply: phandle to the regulator supplying I/O power through the DBVDD
21 pin.
[all …]
Drealtek,rt5682s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Derek Fang <derek.fang@realtek.com>
13 Rt5682s(ALC5682I-VS) is a rt5682i variant which supports I2C only.
16 - $ref: dai-common.yaml#
30 realtek,dmic1-data-pin:
33 - 0 # dmic1 data is not used
34 - 1 # using GPIO2 pin as dmic1 data pin
35 - 2 # using GPIO5 pin as dmic1 data pin
[all …]
Drt5665.txt7 - compatible : One of "realtek,rt5665", "realtek,rt5666".
9 - reg : The I2C address of the device.
11 - interrupts : The CODEC's interrupt output.
15 - realtek,in1-differential
16 - realtek,in2-differential
17 - realtek,in3-differential
18 - realtek,in4-differential
19 Boolean. Indicate MIC1/2/3/4 input are differential, rather than single-ended.
21 - realtek,dmic1-data-pin
23 1: using GPIO4 pin as dmic1 data pin
[all …]
/Documentation/driver-api/
Dpin-control.rst2 PINCTRL (PIN CONTROL) subsystem
5 This document outlines the pin control subsystem in Linux
9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
17 Top-level interface
22 - A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
26 - PINS are equal to pads, fingers, balls or whatever packaging input or
28 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
[all …]
/Documentation/driver-api/media/drivers/
Dsaa7134-devel.rst1 .. SPDX-License-Identifier: GPL-2.0
10 ----------------
14 - 32.11 MHz -> .audio_clock=0x187de7
15 - 24.576MHz -> .audio_clock=0x200000 (xtal * .audio_clock = 51539600)
19 - saa7130 - low-price chip, doesn't have mute, that is why all those
22 - saa7134 - usual chip
24 - saa7133/35 - saa7135 is probably a marketing decision, since all those
28 --------------
32 - LifeView FlyTV Platinum FM (LR214WF)
34 - GP27 MDT2005 PB4 pin 10
[all …]
/Documentation/devicetree/bindings/net/
Dicplus-ip101ag.txt4 - IP101GR (32-pin QFN package)
5 - IP101G (die only, no package)
6 - IP101GA (48-pin LQFP package)
10 - IP101A (48-pin LQFP package)
11 - IP101AH (48-pin LQFP package)
13 Optional properties for the IP101GR (32-pin QFN package):
15 - icplus,select-rx-error:
16 pin 21 ("RXER/INTR_32") will output the receive error status.
18 - icplus,select-interrupt:
19 pin 21 ("RXER/INTR_32") will output the interrupt signal.

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